US20070247932A1 - Shift register circuit and image display comprising the same - Google Patents

Shift register circuit and image display comprising the same Download PDF

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Publication number
US20070247932A1
US20070247932A1 US11/739,399 US73939907A US2007247932A1 US 20070247932 A1 US20070247932 A1 US 20070247932A1 US 73939907 A US73939907 A US 73939907A US 2007247932 A1 US2007247932 A1 US 2007247932A1
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Prior art keywords
transistor
shift register
terminal
control electrode
node
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US11/739,399
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English (en)
Inventor
Youichi Tobita
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TOBITA, YOUICHI
Publication of US20070247932A1 publication Critical patent/US20070247932A1/en
Priority to US13/082,128 priority Critical patent/US8493309B2/en
Priority to US13/914,045 priority patent/US8816949B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to a shift register circuit and more particularly, to a shift register circuit used in such as a scan line drive circuit in an image display and comprising only the same conductivity type field effect transistor.
  • a gate line is provided with respect to each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged like a matrix, and the display image is updated by sequentially selecting and driving the gate line every cycle of one horizontal period of a display signal.
  • a gate line drive circuit for sequentially selecting and driving the pixel line, that is, the gate line
  • a shift register that makes one round of shifting for one frame period of the display signal can be used.
  • the shift register used in the gate line drive circuit comprises only the same conductivity type field effect transistor in order to reduce the steps in the manufacturing process of the display. Therefore, various kinds of shift registers comprising only an N-type or P-type field effect transistor and displays mounting it have been proposed (in Japanese Patent Application Laid Open No. 10-500243, for example).
  • the field effect transistor includes an MOS (Metal Oxide Semiconductor) transistor, a TFT (Thin Film Transistor) and the like.
  • the shift register as the gate line drive circuit is constituted such that a plurality of cascade-connected shift register circuits are provided with respect to each pixel line, that is, each gate line.
  • each of the plurality of shift register circuits that constitute the gate line drive circuit is referred to as the “unit shift register” for simplification of the description.
  • Japanese Patent Application Laid-Open No. 10-500243 discloses a unit shift register constituted such that the number of transistors in a circuit is decreased as compared with a conventional one (FIG. 2 in Japanese Patent Application Laid-Open No. 10-500243, for example).
  • a first transistor (Q 1 ) is provided as an output pull-up transistor connected between a first clock terminal (CK 1 ) to which a predetermined first clock signal is inputted and an output terminal (OUT).
  • the first transistor is turned on in response to a predetermined input signal (G n ⁇ 1 ) and turned off in response to a predetermined reset signal (G n ⁇ 1 ).
  • the output signal (G n ) of the unit shift register is outputted when the first transistor is turned on by the input signal and the first clock signal is transmitted to the output terminal.
  • the first transistor is kept in an off state so that the first clock signal is not transmitted to the output terminal.
  • the input signal is not inputted in that period.
  • the gate potential of the first transistor tries to rise due to the coupling through the overlap capacity between the gate and drain of the first transistor.
  • the gate potential exceeds the threshold voltage of the first transistor, the first transistor to be kept in the off state is unnecessarily turned on, which causes a defective operation of the unit shift register.
  • a second clock signal (/CLK) that is a complementarity signal of the first clock signal is applied to the gate of the first transistor through a first capacity element (C 2 ) in order to prevent the defective operation. That is, the variation in the gate potential of the first transistor caused by the first clock signal can be offset by the second clock signal, so that the gate potential is prevented from rising.
  • the unit shift register outputs the output signal
  • the output terminal that is, the source of the first transistor rises and becomes H (High) level. Therefore, when it is assumed that the gate potential of the first transistor is constant, the voltage between the gate and source of the first transistor is lowered while the output signal is outputted and the drive capability (current flowing capability) is lowered. In this case, the problem is that the rising and falling speeds of the output signal are lowered and it is difficult to implement the high-speed operation.
  • lowering in the drive capability of the first transistor that is, lowering in the drive capability of the unit shift register becomes a big problem.
  • a second capacity element (C 1 ) is further provided between the output terminal and the gate of the first transistor, so that the gate of the first transistor rises in voltage due to the coupling through the second capacity element at the time of outputting the output signal. That is, even when the potential of the output terminal rises, since the gate potential of the first transistor also rises, the voltage between the gate and source of the first transistor can be highly kept. Therefore, there is an effect that the drive capability of the first transistor can be prevented from being lowered when the output signal is outputted.
  • the first capacity element (C 2 ) for preventing the gate potential from rising due to the first clock signal (CLK) is connected to the gate of the first transistor (Q 1 ). Since the first capacity element functions to prevent the variation in the gate potential of the first transistor when the output signal is outputted also, the rising action of the gate of the first transistor by the second capacity element (C 1 ) is also prevented. That is, the effect of the second capacity element (C 1 ) that prevents the drive capability of the first transistor from being lowered at the time of outputting the output signal is weakened by the first capacity element (C 2 ). As a result, when the drive capability of the first transistor is not sufficiently ensured, the problem the high speed operation is difficult arises again.
  • the first capacity element that prevents the defective operation while the output signal is not outputted results in weakening the effect of the second capacity element that the drive capability of the shift register can be ensured while the output signal is outputted, so that it is said that the two operations are in antinomy relation.
  • a shift register circuit includes an input terminal, an output terminal, a first clock terminal, and a reset terminal, a first transistor for supplying a first clock signal inputted to the first clock terminal, to the output terminal, a drive circuit, and switching circuit.
  • the drive circuit drives the first transistor by charging the control electrode of the first transistor based on a signal inputted to the input terminal and discharging the control electrode of the first transistor based on a signal inputted to the reset terminal.
  • the shift register further comprises a switching circuit for making the control electrode of the first transistor and the output terminal conductive based on the first clock signal in a state when the control electrode of the first transistor is discharged.
  • the level of the control electrode of the first transistor sufficiently rises because a current does not flow in the switching circuit while the output signal (first clock signal transmitted to the output terminal through the first transistor) is outputted, so that the drive capability of the first transistor can be highly kept. Thus, the rising and falling speed of the output signal can be increased, which contributes to the high speed operation.
  • the switching circuit since the switching circuit is turned on when the output signal is not outputted (non-selected period), the control electrode of the first transistor is discharged and kept at L level. Thus, it is prevented that the first transistor is turned on and the output signal unnecessarily becomes H level in the non-selected period. That is, both effect that the defective operation is prevented in the non-selected state and effect that the drive capability is prevented from being lowered while the output signal is outputted.
  • FIG. 1 is a schematic block diagram showing the constitution of a display according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the constitution example of a gate line drive circuit using a unit shift register
  • FIG. 3 is a circuit diagram showing the constitution of a conventional unit shift register
  • FIG. 4 is a timing chart showing the operation of the conventional unit shift register
  • FIG. 5 is a timing chart showing the operation of a gate line drive circuit
  • FIG. 6 is a block diagrams showing the constitution example of a gate line drive circuit using the unit shift register
  • FIG. 7 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 1;
  • FIG. 8 is a timing chart showing the operation of the unit shift register according to the embodiment 1;
  • FIG. 9 is a view to explain the operation of the unit shift register according to the embodiment 1;
  • FIG. 10 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 1;
  • FIG. 11 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 1;
  • FIG. 12 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 2;
  • FIG. 13 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 3;
  • FIG. 14 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 4.
  • FIG. 15 is a block diagram showing the constitution example of a gate line drive circuit according to the embodiment 4.
  • FIG. 16 is a view to explain the operation of the unit shift register according to the embodiment 4.
  • FIG. 17 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 5;
  • FIG. 18 is a circuit diagram showing a variation of a level adjustment circuit according to an embodiment 6;
  • FIG. 19 is a circuit diagram showing a variation of the level adjustment circuit according to the embodiment 6;
  • FIG. 20 is a circuit diagram showing a variation of the level adjustment circuit according to the embodiment 6;
  • FIG. 21 is a circuit diagram showing a variation of the level adjustment circuit according to the embodiment 6;
  • FIG. 22 is a circuit diagram showing a variation of the level adjustment circuit according to the embodiment 6;
  • FIG. 23 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 7;
  • FIG. 24 is a timing chart showing the operation of the unit shift register according to the embodiment 7;
  • FIG. 25 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 7;
  • FIG. 26 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 7;
  • FIG. 27 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 7;
  • FIG. 28 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 8.
  • FIG. 29 is a timing chart showing the operation of the unit shift register according to the embodiment 8.
  • FIG. 30 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 8.
  • FIG. 31 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 9;
  • FIG. 32 is a timing chart showing the operation of the unit shift register according to the embodiment 9;
  • FIG. 33 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 9;
  • FIG. 34 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 10;
  • FIG. 35 is a circuit diagram showing the constitution of a unit shift register according to an embodiment 11;
  • FIG. 36 is a circuit diagram showing the constitution of a multistage shift register according to an embodiment 12;
  • FIG. 37 is a circuit diagram showing the constitution of a multistage shift register according to an embodiment 13.
  • FIG. 38 is a circuit diagram showing the constitution of a multistage shift register according to an embodiment 14.
  • FIG. 1 is a schematic block diagram showing the constitution of a display according to an embodiment 1 of the present invention and showing the whole constitution of a liquid crystal display 10 as a representative example of the display.
  • the liquid crystal display 10 comprises a liquid crystal array 20 , a gate line drive circuit (scan line drive circuit) 30 and a source driver 40 .
  • a shift register according to this embodiment of the present invention is mounted on the gate line drive circuit 30 .
  • the liquid crystal array 20 comprises a plurality of pixels 25 arranged like a matrix.
  • Gate lines GL 1 , GL 2 , . . . are connected to rows of pixels (referred to as the “pixel lines” also hereinafter), respectively and data lines DL 1 , DL 2 , . . . (collectively called the “data line DL”) are connected to the columns of pixels (referred to as the “pixel columns” also hereinafter), respectively.
  • pixels 25 in the first and second columns in the first row, and the gate line GL 1 and data lines DL 1 and DL 2 corresponding to the pixels 25 are representatively shown.
  • Each pixel 25 has a pixel switch element 26 provided between the corresponding data line DL and a pixel node Np and a capacitor 27 and a liquid crystal display element 28 connected in parallel between the pixel node Np and a common electrode node NC.
  • the orientation of a liquid crystal in the liquid crystal display element 28 varies according to the voltage difference between the pixel node Np and the common electrode node NC, and accordingly the display luminance of the liquid crystal display element 28 varies.
  • the luminance of each pixel can be controlled by a display voltage transferred to the pixel node Np through the data line DL and the pixel switch pixel 26 .
  • the gate line drive circuit 30 sequentially selects and drives the gate line GL based on a predetermined scan period.
  • the gate electrode of the pixel switch element 26 is connected to the corresponding gate line GL. While the specific gate line GL is selected, in each pixel connected to that gate line GL, the pixel switch element 26 becomes conductive and the pixel node Np is connected to the corresponding data line DL. Thus, the display voltage transferred to the pixel node Np is held by the capacitor 27 .
  • the pixel switch element 26 comprises a TFT formed on the same insulator substrate (glass substrate, a resin substrate and the like) as that of the liquid crystal display element 28 .
  • the source driver 40 outputs the display voltage sequentially set by a display signal SIG that is an N-bit digital signal to the data line DL.
  • a color display unit is formed of three pixels of R (Red), G (Green) and B (Blue), color display of about two hundred sixty thousand colors can be provided.
  • the source driver 40 comprises a shift register 50 , a data latch circuits 52 and 54 , a tone voltage generation circuit 60 , a decoder circuit 70 , and an analog amplifier 80 .
  • display signal bits DB 0 to DB 5 corresponding to each display luminance of the pixel 25 is serially generated. That is, the display signal bits DB 0 to DB 5 at each timing show the display luminance of the one pixel 25 in the liquid crystal array 20 .
  • the shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB 0 to DB 5 at a timing synchronized with the period when the setting of the display signal SIG is switched.
  • the data latch circuit 52 sequentially takes in the serially generated display signal SIG and stores the display signal SIG for one pixel line.
  • a latch signal LT inputted to the data latch circuit 54 is activated at the timing when the display signal SIG for the one pixel line is taken in the data latch circuit 52 .
  • the data latch circuit 54 responds to it and takes in the display signal SIG for the one pixel line stored in the data latch circuit 52 at that time.
  • the tone voltage generation circuit 60 comprises 63 voltage divider resistances connected in series between a high voltage VDH and a low voltage VDL and generates 64-stages tone voltages V 1 to V 64 .
  • the decoder circuit 70 decodes the display signal SIG stored in the data latch circuit 54 and selects the voltage to be outputted to each of decode output nodes Nd 1 , Nd 2 , . . . (collectively called the “decode output node Nd”) from the tone voltages V 1 to V 64 based on the above decoded result and outputs it.
  • the display voltage (one of the tone voltages V 1 to V 64 ) corresponding to the display signal SIG for the one pixel line stored in the data latch circuit 54 is outputted to the decode output node Nd at the same time (in parallel).
  • the decode output nodes Nd 1 and Nd 2 corresponding to the data lines DL 1 and DL 2 in the first and second columns are representatively shown.
  • the analog amplifier 80 outputs analog voltage corresponding to each display voltage outputted from the decoder circuit 70 to each of the decode output nodes Nd 1 , Nd 2 , . . . , to each of the data lines DL 1 , DL 2 , . . . .
  • the source driver 40 Based on the predetermined scan period, the source driver 40 outputs the display voltages corresponding to the series of the display signals SIG repeatedly to the data line DL for one pixel line, and the gate line drive circuit 30 synchronizes with the scan period and drives the gate lines GL 1 , GL 2 , . . . sequentially, whereby an image based on the display signal SIG is displayed in the liquid crystal array 20 .
  • the gate line drive circuit 30 and the source driver 40 may be provided as an external circuit of the liquid crystal array 20 .
  • FIG. 2 is a view showing the constitution of the gate line drive circuit 30 .
  • the gate line drive circuit 30 comprises multistage shift register consisting of a plurality of cascade-connected unit shift registers SR 1 , SR 2 , SR 3 , SR 4 , . . . (collectively referred to as the “unit shift register SR” hereinafter).
  • the unit shift register SR is provided with respect to each pixel line, that is, with respect to each gate line GL.
  • a clock generator 31 shown in FIG. 2 inputs two-phase clock signals CLK and /CLK having different phases to the unit shift register SR of the gate line drive circuit 30 .
  • These clock signals CLK and /CLK are controlled so as to be activated sequentially at the timing synchronized with the scan period of the display. That is, the clock signals CLK and /CLK are complementarity signals.
  • Each unit shift register SR comprises an input terminal IN, an output terminal OUT, a reset terminal RST, a first clock terminal CK 1 and a second clock terminal CK 2 .
  • either the clock signal CLK, or /CLK outputted from the clock generator 31 is supplied to the first and second clock terminals CK 1 and CK 2 of each unit shift register SR.
  • the gate line GL is connected to the output terminal OUT of the unit shift register SR. That is, the signal (output signal) outputted to the output terminal OUT becomes a horizontal (or vertical) scan pulse for activating the gate line GL.
  • a start pulse SP corresponding to the head of each frame period of the pixel signal is inputted to the input terminal IN of the first stage unit shift register SR 1 .
  • the output signals of the previous stages are inputted. That is, the input terminals IN after the second stages are connected to the output terminal OUT of the previous unit shift register SR.
  • the unit shift register SR shifts the input signal from the previous stage (output signal of the previous stage) temporally in synchronization with the clock signals CLK and /CLK and transmits it to the corresponding gate line GL and the next stage unit shift register SR (the operation of the unit shift register SR will be described in detail below).
  • the series of the unit shift registers SR function as a gate line driving unit that activates sequentially the gate line GL at the timing based on the predetermined scan period.
  • FIG. 3 is a circuit diagram showing the constitution of the conventional unit shift register.
  • a gate line drive circuit 30 since the constitution of each of the cascade-connected unit shift registers SR is the almost the same, the constitution of one unit shift register will be described only in the following description.
  • the transistor constituting the unit shift register SR is a field effect transistor having the same conductivity type, it is assumed that the transistor is an N-type TFT in this embodiment.
  • the conventional unit shift register SR comprises a first power supply terminal S 1 to which a low potential side power supply potential VSS is supplied as well as an input terminal IN, an output terminal OUT, a reset terminal RST and first and second clock terminals CK 1 and CK 2 described with reference to FIG. 2 .
  • the clock signals CLK and /CLK are controlled so as to be moved to H (High) level and L (Low) level at the same timing. That is, the clock signal /CLK falls when the clock signal CLK rises and the clock signal /CLK rises when the clock signal CLK falls.
  • the output stage of the unit shift register SR comprises a transistor Q 1 connected between the output terminal OUT and the first clock terminal CK 1 . That is, the transistor Q 1 functions as an output pull-up transistor that supplies the clock signal from the first clock terminal CK 1 to the output terminal OUT.
  • the node connected to the gate (control electrode) of the transistor Q 1 is a “node N 1 ” hereinafter.
  • a capacity element C 1 is provided between the gate and source of the transistor Q 1 (that is between the output terminal OUT and the node N 1 ), and a capacity element C 2 is provided between the node N 1 and the second clock terminal CK 2 .
  • reference sign “C 3 ” designates a load capacity of the output terminal OUT of the unit shift register SR (that is, the gate line).
  • a transistor Q 3 is connected between the node N 1 and the input terminal IN, and the transistor Q 3 is a diode-connected transistor (that is, both gate and drain of the transistor Q 3 are connected to the input terminal IN).
  • a transistor Q 4 is connected between the node N 1 and the first power supply terminal S 1 , and the gate of the transistor Q 4 is connected to the reset terminal RST.
  • the transistor Q 3 charges the node N 1 based on the signal inputted to the input terminal IN to turn on the transistor Q 1
  • the transistor Q 4 discharges the node N 1 based on the signal inputted to the reset terminal RST to turn off the transistor Q 1 . That is, the transistors Q 3 and Q 4 constitute the drive circuits to drive the transistor Q 1 .
  • FIG. 4 is a timing chart showing the operation of the conventional unit shift register shown in FIG. 3 .
  • the specific operation of the unit shift register SR shown in FIG. 3 will be described with reference to FIG. 4 hereinafter.
  • the operation of each unit shift register SR constituting the gate line drive circuit 30 is the substantially the same, the operation of the n-th unit shift register SRn will be described here representatively.
  • the description will be made assuming that the clock signal CLK is inputted to the first clock terminal CK 1 of the unit shift register SRn, and the clock signal /CLK is inputted to the second clock terminal CK 2 (for example, the unit shift registers SR 1 and SR 3 shown in FIG. 2 correspond to it). Furthermore, it is defined that an output signal of the unit shift register SR n is G n and an output signal of its previous stage (n ⁇ 1 stage) unit shift register SR is G n ⁇ 1 and an output signal of its next stage (n+1 stage) unit shift register SR is G n+1 . In addition, it is assumed that all threshold voltages of the transistors constituting the unit shift register SR n are equal and that value is set to Vth. Furthermore, it is assumed that the potentials of the clock signals CLK and /CLK at H level are equal and the value is set to VDD.
  • the node N 1 is at L level (VSS) (referred to as the “reset state” hereinafter) and the output terminal OUT is also at L level.
  • the first clock terminal CK 1 clock signal CLK
  • the second clock terminal CK 2 clock signal /CLK
  • the reset terminal RST the next stage output signal G n+1
  • the input terminal IN previously stage output signal G n ⁇ 1
  • the transistor Q 1 since the transistor Q 1 is off (cut state), the H level of the first clock terminal CK 1 (clock signal CLK) is not transmitted to the output terminal OUT and the output signal G n is kept at L level. That is, the GL n connected to this unit shift register SR n is in a non-selected state.
  • the clock signal CLK becomes H level and the clock signal /CLK becomes L level.
  • the node N 1 becomes H level in a floating state.
  • the transistor Q 1 since the transistor Q 1 is still ON, the H level of the clock signal CLK is transmitted to the output terminal OUT and the level of the output signal G n rises.
  • the level of the node N 1 rises by a specific voltage due to the coupling through the capacity element C 1 and the capacity between the gate and channel of the transistor Q 1 .
  • the level of the output signal G n varies, following the level of the first clock terminal CK 1 (clock signal CLK).
  • the output signal G n becomes H level (VDD) and the gate line GL n is activated and becomes a selected state.
  • the unit shift register SR n shown in FIG. 3 since a period while the output signal G n is not outputted (referred to as the “non-selected period” hereinafter), since the rise of the node N 1 due to the clock signal CLK is negated by the clock signal /CLK, the reset state is maintained. As a result, a defective operation during the non-selected period is prevented.
  • the unit shift register SR n keeps in the reset state in the non-selected period to keep the transistor Q 1 OFF and keep the output terminal OUT at L level (VSS) of high impedance.
  • the unit shift register SR is switched to the set state. Since the transistor Q 1 is ON in the set state, while the first clock terminal CK 1 (clock signal CLK) becomes H level, the output terminal OUT becomes H level and the output signal G n is outputted. Then, when the signal (next stage output signal G n+1 ) is inputted to the reset terminal RST, it returns to the original reset state.
  • the gate line drive circuit 30 can drive the gate lines GL 1 , GL 2 , GL 3 , . . . sequentially in the predetermined scan period.
  • FIG. 6 shows the constitution of a gate line drive circuit 30 in this case.
  • the gate line drive circuit 30 comprises a plurality of cascade-connected unit shift registers SR. That is, the output terminal OUT of the previous stage unit shift register SR is connected to the input terminal IN of the unit shift register SR. However, it is to be noted that a start pulse SP is inputted to the input terminal IN of the first unit shift register SR 1 as an input signal.
  • a clock generator 31 in this case outputs three clock signals CLK 1 , CLK 2 , CLK 3 having different phases (it is assumed that they are activated in this order). Any two of the signals CLK 1 , CLK 2 and CLK 3 are inputted to the first clock terminal CK 1 and CK 2 of the unit shift register SR.
  • the combination of the two is made such that the rise of the clock signal of the first clock terminal CK 1 and the fall of the clock signal of the second clock terminal CK 2 occur at the same time so that the potential of the node N 1 may not rise due to the clock signal of the first clock terminal CK 1 in the non-selected period (for example, when the clock signal CLK 1 is inputted to the first clock terminal CK 1 , the clock signal CLK 3 that has become H level just before the clock signal CLK 1 is to be inputted to the second clock terminal CK 2 ).
  • the output terminal OUT of the unit shift register of the next stage or two stages after is connected to the reset terminal RST of the unit shift register SR.
  • the latter stage unit shift register SR since the output signal of the latter stage unit shift register SR is inputted to the reset terminal RST of the unit shift register SR, the latter stage unit shift register SR has to be provided so that each unit shift register SR becomes the reset state.
  • at least one dummy unit shift register is to be provided next to the final stage unit shift register SR so that the final stage unit shift register SR becomes reset state by the output signal of the dummy stage unit shift register SR.
  • At least two dummy unit shift register is provided next to the final stage unit shift register SR so that the unit shift register SR of one stage before the final stage becomes the reset state by the output signal of the dummy unit shift register next to the final stage unit shift register SR and the final stage unit shift register SR becomes the reset state by the output signal of the dummy unit shift register of two stages after the final stage unit shift register SR.
  • the unit shift register SR cannot perform a normal operation until it becomes the reset state (that is, the above initial state), it is necessary to perform a dummy operation in which a dummy input signal is transmitted from the first stage to final stage and dummy stage of the unit shift registers prior to the normal operation.
  • a transistor for resetting may be separately provided between the node N 1 of the unit shift register SR and the first power supply terminal S 1 (high potential side power supply) to perform the reset operation in which the node N 1 is forcibly discharged prior to the normal operation.
  • the start pulse SP to be inputted to the first unit shift register SR 1 may be used.
  • the problem of the defective operation of the unit shift register SR shown in FIG. 3 will be described in detail.
  • the capacity element C 2 since the capacity element C 2 is connected to the gate (node N 1 ) of the transistor Q 1 in order to prevent the potential rise of the node N 1 due to the clock signal CLK, the level of the node N 1 is prevented from rising due to the above operation in the non-selected period, so that the reset state is maintained.
  • the capacity element C 2 also prevents the voltage rising of the node N 1 when the output signal G n is outputted (at times t 2 to t 3 shown in FIG. 4 ).
  • the potential of the node N 1 should rise to the higher potential as shown by a dotted line in FIG. 4 .
  • the output signal G n sharply rises as shown by a dotted line in FIG. 4 , so that the operation can be performed at higher speed.
  • the capacity element C 2 is removed from the unit shift register SR, the level of the node N 1 rises in the non-selected period due to the clock signal CLK, so that the reset state cannot be maintained and a defective operation occurs.
  • the unit shift register SR shown in FIG. 3 since the voltage rising effect of the node N 1 when the output signal G n is outputted is reduced, there is a limit in increasing the drive capability of the transistor Q 1 (that is, the drive capability of the unit shift register) to speed up the rising rate of the output signal G n , which prevents the operation from being performed at high speed.
  • the pulse width of the output signal G n is reduced to speed up the operation of the display, the potential of the gate line cannot rise to a theoretical value (VDD), which lowers a display quality.
  • FIG. 7 is a circuit diagram showing the constitution of a unit shift register SR according to the embodiment 1.
  • the output stage of the unit shift register SR comprises a transistor Q 1 connected between an output terminal OUT and a first clock terminal CK 1 , and a transistor Q 2 connected between the output terminal OUT and a first power supply terminal S 1 .
  • the transistor Q 1 is an output pull-up transistor (first transistor) in which a clock signal inputted to the first clock terminal CK 1 is supplied to the output terminal OUT
  • the transistor Q 2 is an output pull-down transistor (ninth transistor) in which the output terminal OUT is discharged by supplying the potential of the first power supply terminal S 1 to the output terminal OUT.
  • the node connected to the gate (control electrode) of the transistor Q 1 is a node N 1 .
  • the gate of the transistor Q 2 is connected to the second clock terminal CK 2 .
  • a capacity element C 1 is provided between the gate and source of the transistor Q 1 , that is, the node N 1 and the output terminal OUT.
  • Reference sign “C 3 ” designates a load capacity of the output terminal OUT (gate line) of the unit shift register SR.
  • the unit shift register SR shown in FIG. 7 does not have the capacity element C 2 shown in FIG. 3 .
  • the unit shift register SR shown in FIG. 7 also comprises a drive circuit comprising a diode-connected transistor Q 3 (eleventh transistor) connected between the node N 1 and the input terminal IN and a transistor Q 4 (tenth transistor) connected between the node N 1 and the first power supply terminal S 1 in which the gate is connected to the reset terminal RST. That is, the transistor Q 3 charges the gate (node N 1 ) of the transistor Q 1 based on the signal inputted to the input terminal IN, and the transistor Q 4 discharges the node N 1 based on the signal inputted to the reset terminal RST.
  • a drive circuit comprising a diode-connected transistor Q 3 (eleventh transistor) connected between the node N 1 and the input terminal IN and a transistor Q 4 (tenth transistor) connected between the node N 1 and the first power supply terminal S 1 in which the gate is connected to the reset terminal RST. That is, the transistor Q 3 charges the gate (node N 1 ) of the transistor Q 1 based on the signal inputted to
  • the unit shift register SR further comprises a transistor Q 5 (second transistor) connected between the node N 1 and the output terminal OUT, and the gate of the transistor Q 5 is connected to the first clock terminal CK 1 . That is, the transistor Q 5 functions as a switching circuit that connects the node N 1 to the output terminal OUT based on the signal inputted to the first clock terminal CK 1 .
  • FIG. 8 is a timing chart showing the operation of the unit shift register SR according to the embodiment 1.
  • the operation of the unit shift register SR according to this embodiment shown in FIG. 7 will be described with reference to FIG. 8 hereinafter.
  • the unit shift register SR shown in FIG. 7 can be also applied to the gate line drive circuit 30 having the constitutions shown in FIGS. 2 and 6 , here, the operation of the cascade-connected unit shift registers SR in a gate line drive circuit 30 like in FIG. 2 will be described.
  • an output signal of the unit shift register SR n is G n and an output signal of a unit shift register SR n ⁇ 1 of its previous stage (n ⁇ 1 stage) is G n ⁇ 1 and an output signal of a unit shift register SR n+1 of its next stage (n+1 stage) is G n+1 .
  • FIG. 8 is a timing chart showing the above operation.
  • the node N 1 is at L level (VSS) in an initial state (referred to as the “reset state” hereinafter). It is also assumed that the first clock terminal CK 1 (clock signal CLK) is at H level, the second clock terminal CK 2 (clock signal /CLK), the reset terminal RST (next stage output signal G n+1 ) and the input terminal IN (previous stage output signal G n ⁇ 1 ) are all at L level. In this case, since the transistors Q 1 , Q 2 and Q 5 connected to the output terminal OUT are all OFF, although the output terminal OUT is in a floating state, it is assumed that the output terminal OUT (output signal G n ) is at L level in the initial state.
  • the previous stage output signal G n ⁇ 1 returns to L level. Then, since the transistor Q 3 is turned off, the node N 1 becomes floating state, that is, H level. Although at this time the transistor Q 2 is turned off, since the transistor Q 1 is maintained in ON state and the first clock terminal CK 1 (clock signal CLK) is at L level, the output signal G n is maintained at L level.
  • the level of the output terminal OUT (output signal G n ) becomes VDD that is the same level as H level of the clock signal CLK, so that the load capacity C 3 is charged and the gate line GL n becomes the selected state.
  • the clock signal CLK is supplied to the gate of the transistor Q 5 also.
  • the operation of the transistor Q 5 at the time t 3 that is, when the output signal G n rises will be described.
  • FIG. 9 shows the operation and the upper part of the drawing is an enlarged view of the waveforms of the clock signal CLK and the output signal G n at the time t 3 in FIG. 8 .
  • V GS (Q 5 ) between the gate and source of the transistor Q 5 at that time that is, the voltage difference between the clock signal CLK and the output signal G n at the upper part (when the output signal G n rises, the source of the transistor Q 5 is on the side of the output terminal OUT and the drain is on the side of the node N 1 from the potential relation).
  • the lower part in FIG. 9 shows a current I (Q 5 ) flowing in the transistor Q 5 at that time.
  • the rise in voltage of the node N 1 at the time of the rise of the output signal G n allows for great drive capability of the transistor Q 1 , when the current I (Q 5 ) is large, the potential of the node N 1 is lowered, which lowers the above effect.
  • the transistor Q 1 since the transistor Q 1 is large in size, the output signal G n rises quickly, following the clock signal CLK, so that the voltage V GS (Q 5 ) is not so high and even if it becomes higher than the threshold voltage Vth (Q 5 ), it is only for a short time.
  • the current I (Q 5 ) flows only a little and the level lowering of the node N 1 that affects the drive capability of the transistor Q 1 is not generated.
  • the voltage V GS (Q 5 ) between the gate and source of the transistor Q 5 does not exceed the threshold voltage Vth (Q 5 )
  • the current I (Q 5 ) does not flow, which does not affect the drive capability of the transistor Q 1 at all.
  • the drive capability of the transistor Q 1 can be greatly ensured and the output signal G n rises at the time t 3 at high speed.
  • FIG. 10 is a timing chart showing the above operation and each signal waveform while the unit shift register SR n outputs the output signal G n and moves to the non-selected period. That is, a time t 6 shown in FIG. 10 corresponds to the time t 6 in FIG. 8 .
  • the clock signal /CLK and the next stage output signal G n+1 become H level and the node N 1 and the output terminal OUT (output signal G n ) are at L level.
  • the transistor Q 4 When the next stage output signal G n+1 becomes L level from the above state and the clock signal /CLK becomes L level at a time t 6 , the transistor Q 4 is turned off and the node N 1 becomes L level of a floating state. Furthermore, the level of the node N 1 is lowered by a specific voltage ( ⁇ V 1 ) due to the coupling through the overlap capacity between the gate and drain of the transistor Q 4 . In addition, since the transistor Q 2 is also turned off at this time, the output terminal OUT becomes L level of the floating state.
  • the transistor Q 5 since the transistor Q 5 is ON (in conductive state) at this time, even when the potential of the node N 1 rises, the electric charge is discharged to the load capacity C 3 immediately. Thus, even when the transistor Q 1 is turned on due to the rise of node N 1 , it is only for a short time and since the load capacity C 3 is relatively large, the rise in level of the output terminal OUT is very small ( ⁇ V 3 ). In addition, the node N 1 after discharged by the transistor Q 5 becomes the same level as that of the output terminal OUT (higher than VSS by ⁇ V 3 ).
  • the transistor Q 5 is turned off. Since the node N 1 is in the floating state, the level of the node N 1 is lowered by a voltage ( ⁇ V 4 ) that is almost equal to the above ⁇ V 2 according to the fall of the clock signal CLK due to the coupling through the gate overlap capacity between the gate and drain of the transistor Q 1 .
  • the output signal G n hardly rises in the non-selected period in which the output signal G n is not outputted ( ⁇ V 3 shown in FIG. 10 at most), so that a defective operation is prevented.
  • the output signal G n when the output signal G n is outputted (when the gate line GL n is selected), since a current does not flow in the transistor Q 5 , the level of the node N 1 sufficiently rises and the drive capability of the transistor Q 1 can be highly ensured. Thus, the output signal G n can rise and fall at high speed, which contributes to high speed of the operation. In addition, in the non-selected period in which the output signal G n is not outputted, even when the level of the node N 1 is going to rise when the clock signal CLK rises, since the transistor Q 5 is turned on, the node N 1 is discharged and its L level is maintained.
  • the unit shift register SR in this embodiment allows for both prevention of a defective operation in the non-selected period and prevention of lowering of the drive capability while the gate line is selected. As a result, operation reliability of the image display comprising the gate line drive circuit 30 having the unit shift register SR can be improved.
  • the unit shift register SR can be applied to the gate line drive circuit 30 having the constitution shown in FIG. 6 and driven by the three-phase clock signals.
  • the two stages later output terminal OUT is connected to the reset terminal RST of the unit shift register SR so as to be suitable for the conventional circuit in FIG. 3 is shown in FIG. 6
  • one stage later (the next) output terminal OUT may be connected to it.
  • a wiring structure becomes simple (refer to FIG. 11 ).
  • the rise of the clock signal of the first clock terminal CK 1 does not necessarily conform to the fall of the clock signal of the second clock terminal CK 2 .
  • the clock signals inputted to each unit shift register SR may be combined as shown in FIG. 11 (three-phase clock signals CLK 1 , CLK 2 , CLK 3 , CLK 1 , . . . become H level in this order).
  • the clock signal that will become at H level next may be inputted to the second clock terminal CK 2 (for example, when the clock signal CLK 1 is inputted to the first clock terminal CK 1 , the clock signal CLK 2 that will become H level next is inputted to the second clock terminal CK 2 ).
  • the level of the output terminal OUT that rose a little by the electric charge discharged from the node N 1 through the transistor Q 5 in the non-selected period ( ⁇ V 3 and ⁇ V 7 shown in FIG. 10 ) is quickly lowered to VSS.
  • the operation reliability of the unit shift register SR according to this embodiment can be further increased.
  • the node N 1 is charged by the previous stage output signal G n ⁇ 1 .
  • the output signal G n of the unit shift register SR n is used not only for the gate line GL n , but also for charging the node N 1 of the next stage unit shift register SR n+1 .
  • the capacity component associated with the node N 1 of the unit shift register SR includes the capacity of the capacity element C 1 and the gate capacity of the transistor Q 1 . According to the embodiment 1, the capacity component becomes a part of the load capacity C 3 of the output terminal OUT of the unit shift register SR, which causes the rising speed of the output signal to be lowered. This prevents the high-speed operation of the unit shift register SR.
  • FIG. 12 is a circuit diagram of the unit shift register SR.
  • the gate of a transistor Q 3 constituting a drive circuit is connected to an input terminal IN, and a drain is connected to a second power supply terminal S 2 to which a predetermined high potential side power supply potential VDD is supplied. That is, according to this embodiment, the node N 1 is not charged by the previous stage output signal G n ⁇ 1 , but charged by the power supply that supplies the high potential side power supply potential VDD. Except for this, it has the same constitution as that of the unit shift register SR in the embodiment 1 ( FIG. 7 ).
  • the output terminal OUT of the unit shift register SR is connected to a gate line GL and the gate of the transistor Q 3 . Since the gate capacity of the transistor Q 3 is 1/10 of the capacity component associated with the node N 1 (capacity of a capacity element C 1 and the gate capacity of the transistor Q 3 ) or less, the load capacity of the output terminal OUT of the unit shift register SR is smaller than that in the embodiment 1. Therefore, the rising speed and falling speed of the output signal can be prevented from being lowered and the above problem can be solved.
  • the unit shift register SR shown in FIG. 12 is different from the circuit shown in FIG. 7 in that the node N 1 is charged by the power supply that supplies the high potential side power supply potential VDD, its operation is the same. Therefore, the same effect as that in the embodiment 1 can be provided in this embodiment.
  • the drain potential of the transistor Q 3 is VDD even in the non-selective period, although there is concern that an electric charge is supplied to the node N 1 at L level of a floating state by a leak current of the transistor Q 3 , this concern is no problem because a transistor Q 5 is periodically turned on in synchronization with the clock signal CLK and the electric charge is discharged.
  • the unit shift register SR in the embodiment 1 since a wiring for supplying the high potential side power supply potential VDD is not needed, the area occupied by the circuit can be reduced, which contributes to high integration of the gate line drive circuit.
  • a display in which a shift register of a gate line drive circuit comprises an amorphous silicon TFT (a-Si TFT) is easy to be enlarged and has high productivity, so that it is widely used as a screen of a notebook personal computer or a big screen display.
  • a-Si TFT amorphous silicon TFT
  • FIG. 13 is a circuit diagram showing the constitution of the unit shift register according to the embodiment 3.
  • the source of a transistor Q 2 is connected to a first clock terminal CK 1 . That is, the main electrode (drain) of the transistor Q 2 is connected to an output terminal OUT and a clock signal CLK having a phase different from that of a clock signal /CKL to be inputted to a control electrode (gate) is supplied to another main electrode (source).
  • this embodiment can be applied to a unit shift register SR of a gate line drive circuit 30 driven by three-phase clock signals.
  • either one of the two clock signals other than that inputted to the gate of the transistor Q 2 may be inputted to the source of the transistor Q 2 .
  • this embodiment can be applied to the circuit in the embodiment 2 ( FIG. 12 ).
  • the potential of the node N 1 at the time of moving to the set state rises to VDD ⁇ Vth (Q 3 ) theoretically by the charging (precharge) of the transistor Q 3 .
  • charging speed of the node N 1 is not relatively high, when the frequency of the clock signal becomes high and the pulse width of the input signal (previous stage output signal) becomes narrow, it is hard for the node N 1 to reach the maximum precharge level (VDD ⁇ Vth (Q 3 )).
  • Reason for that includes the fact that the transistor Q 3 operates in a source follower mode at the time of the precharging of the node N 1 .
  • FIG. 14 is a circuit diagram showing the constitution of the unit shift register SR according to the embodiment 4.
  • a drive circuit for driving a transistor Q 1 comprises transistors Q 6 and Q 7 and a capacity element C 4 in addition to transistors Q 3 and Q 4 .
  • the transistor Q 3 is connected between the node N 1 and a second power supply terminal S 2
  • the transistor Q 4 is connected between the node N 1 and a first power supply terminal S 1 .
  • the gate of the transistor Q 4 is connected to a reset terminal RST.
  • a previous stage output signal G n ⁇ 1 is not directly inputted to the gate of the transistor Q 3 .
  • the unit shift register SR has two input terminals such as a first input terminal IN 1 and a second input terminal IN 2 .
  • the gate node of the transistor Q 3 is a node N 2
  • the transistor Q 6 whose gate is connected to the first input terminal IN 1 is connected between the node N 2 and the second power supply terminal S 2 .
  • the capacity element C 4 is connected between the node N 2 and the second input terminal IN 2 .
  • the transistor Q 7 whose gate is connected to the reset terminal RST is connected between the node N 2 and the first power supply terminal S 1 .
  • the transistor Q 8 whose gate is connected to a first clock terminal CK 1 is connected between the node N 2 and the output terminal OUT and it is a transistor for preventing the node N 2 from becoming a floating state.
  • a gate line drive circuit 30 is constituted by the unit shift register SR shown in FIG. 14
  • the plurality of unit shift registers SR are cascade-connected as shown in FIG. 15 .
  • Three-phase clock signals generated from a clock generator 31 are controlled such that CLK 1 , CLK 2 , CLK 3 , CLK 1 , . . . are activated in this order.
  • first and second start pulses SP 1 and SP 2 are inputted to the first and second input terminals IN 1 and IN 2 of the first stage unit shift register SR 1 as input signals, respectively.
  • the first and second start pulses SP 1 and SP 2 are signals that become H level at the timing corresponding to the head of each frame of an image signal but the phases of them are shifted. That is, the first start pulse SP 1 becomes H level at a timing earlier than that of the second start pulse SP 2 , and the second start pulse SP 2 is controlled to become H level after the first start pulse SP 1 has returned to L level.
  • the second start pulse SP 2 is inputted to a first input terminal IN 1 , and a second input terminal IN 2 is connected to the output terminal OUT of the first stage unit shift register SR 1 .
  • a first input terminal IN 1 is connected to the output terminal OUR of the previous stage unit shift register SR and a second input terminal IN 2 is connected to the output terminal OUT of the two stages before unit shift register SR.
  • the reset terminal RST of each unit shift register SR is connected to the next stage output terminal OUT.
  • FIG. 16 is a timing chart showing the operation of the unit shift register SR according to this embodiment.
  • a description will be made of the operation of an n-th unit shift register SR n assuming that the clock signal CLK 1 is inputted to its first clock terminal CK 1 and the clock signal CLK 2 is inputted to its second clock terminal CK 2 (for example, it corresponds to the unit shift registers SR 1 and SR 4 in FIG. 15 ).
  • a gate drive signal outputted from the unit shift register SR is G n
  • output signals of the previous stage and two stages before unit shift registers SR are G n ⁇ 1 and G n ⁇ 2 , respectively
  • a gate line drive signal outputted from the next stage unit shift register SR is G n+1 .
  • H levels of the clock signals CLK 1 , CLK 2 , CLK 3 , the first start pulse SP 1 and the second start pulse SP 2 are equal to each other and the level is equal to a high potential side power supply potential VDD.
  • the node N 1 and the node N 2 are at L level (VSS) (referred to as the “reset state” hereinafter).
  • the first clock terminal CK 1 clock signal CLK 1
  • the first input terminal IN 1 two stages before output signal G n ⁇ 2
  • the input terminal IN 2 previous stage output signal G n ⁇ 1
  • the reset terminal RST next stage output signal G n+1
  • the node N 2 can be charged at high speed.
  • VDD ⁇ Vth (Q 6 ) a theoretical value
  • the precharged node N 2 further rises due to the coupling through the capacity element C 4 of the unit shift register SR.
  • the node N 2 after the level has risen is higher than that before the level rise by the amplitude (VDD) of the previous stage output signal G n ⁇ 1 , it becomes 2 ⁇ VDD ⁇ Vth (Q 6 ).
  • the transistor Q 3 charges the node N 1 not in the source follower mode but in the operation in a non-saturation region (non-saturation operation).
  • the node N 1 is charged at high speed and becomes H level, and the node N 1 reaches VDD level without any loss in the threshold voltage Vth.
  • the transistor Q 1 is turned on.
  • the node N 1 since the loss in the threshold voltage of the transistor Q 3 is accompanied at the time of precharging of the node N 1 , even when the pulse width of the clock signal is sufficiently large, the node N 1 only rises to VDD ⁇ Vth (Q 3 ) at most. Meanwhile, according to this embodiment, the node N 1 can be charged to the level higher than that by Vth (Q 3 ) or more even for a short time.
  • the clock signal CLK 1 of the first clock terminal CK 1 becomes H level at a time t 5
  • the transistor Q 1 since the transistor Q 1 is ON and the transistor Q 2 is OFF at this time, the level of the output signal G n of the output terminal OUT rises.
  • the level of the node N 1 rises due to the capacity coupling through the capacity element C 1 and the gate capacity of the transistor Q 1 by a specific voltage.
  • the level of the output terminal OUT that is, the output signal G n rises at high speed, following the clock signal CLK 1 .
  • the H level of the output signal G n is VDD that is the same level of the H level of the clock signal CLK 1 .
  • the output signal G n also returns to L level and the gate line returns to the non-selected state. At this time, the level of the node N 1 is lowered to the previous state of VDD.
  • the next stage output signal G n+1 becomes H level. Accordingly, the transistors Q 4 and Q 7 are turned on and the nodes N 1 and N 2 return to L level of the reset state. Thus, although the transistor Q 1 is turned off, since the transistor Q 2 is turned on at this time, the L level of the output signal G n is maintained. Then, when the clock signal CLK 2 returns to L level at a time t 8 , the next stage output signal G n+1 returns to L level and then the unit shift register SR n enters a non-selected period.
  • the operation in the non-selected period is almost the same as that in the embodiment 1 basically, and every time the clock signal CLK 1 is inputted to the first clock terminal CK 1 , the transistor Q 5 is turned on (conductive state). Thus, even when the level of the node N 1 is going to rise when the clock signal CLK 1 rises, the node N 1 is discharged through the transistor Q 5 , so that its L level is maintained. Furthermore, in this non-selected period, the transistor Q 8 is also turned on every time the clock signal CLK 1 is inputted and the node N 2 is discharged. Thus, the electric charge due to the leak current of the transistor Q 6 is stored in the node N 2 and the node N 2 is prevented from becoming H level. Thus, the transistors Q 5 and Q 8 prevent the transistor Q 1 from being turned on and prevent the output signal G n from becoming H level unnecessarily in the non-selected time.
  • the node N 1 can be precharged to higher level at higher speed, the rising and falling speed of the output signal can be more improved, which contributes to the high speed of the operation.
  • the transistor Q 5 operates similar to the embodiment 1, the effect that the defective operation is prevented in the non-selected period can be provided like in the embodiment 1.
  • the embodiment 3 can be applied to this embodiment.
  • the unit shift register SR in the embodiment 1 when the voltage V GS (Q 5 ) between the gate and source of the transistor Q 5 exceeds its threshold voltage Vth (Q 5 ) at the time of rising of the output signal (G n ), the current (I (Q 5 )) flows from the node 1 to the output terminal OUT through the transistor Q 5 .
  • V GS (Q 5 ) between the gate and source of the transistor Q 5 exceeds its threshold voltage Vth (Q 5 ) at the time of rising of the output signal (G n )
  • the current (I (Q 5 )) flows from the node 1 to the output terminal OUT through the transistor Q 5 .
  • An embodiment 5 proposes a unit shift register SR to solve the above problem.
  • FIG. 17 is a circuit diagram showing the unit shift register according to the embodiment 5.
  • the gate of a transistor Q 5 and a first clock terminal CK 1 are not directly connected and a level adjustment circuit 100 is interposed therebetween.
  • the level adjustment circuit 100 lowers the H level of a clock signal inputted to the first clock terminal CK 1 by a predetermined value (reduces the absolute value of the H level based on L level) and then supplies it to the gate of the transistor Q 5 . That is, the level adjustment circuit 100 functions to reduce the amplitude of the clock signal inputted to the first clock terminal CK 1 by the predetermined value.
  • the level adjustment circuit 100 in the example shown in FIG. 17 comprises transistors Q 9 and Q 10 .
  • the transistor Q 9 third transistor
  • the transistor Q 10 fourth transistor
  • the transistor Q 10 is connected between the node N 3 and a first power supply terminal S 1 and its gate is connected to a second clock terminal CK 2 .
  • the unit shift register SR in the embodiment 5 will be described hereinafter.
  • the unit shift register SR is driven by two-phase clock signals CLK and /CLK and the clock signal CLK is inputted to the first clock terminal CK 1 and the clock signal /CLK is inputted to the second clock terminal CK 2 .
  • the clock signal CLK is supplied to the gate of the transistor Q 5 through the level adjustment circuit 100 .
  • the clock signal CLK becomes H level
  • a signal whose level is reduced from the H level of the clock signal CLK by the threshold voltage of the transistor Q 9 that is, a signal whose level is reduced from the amplitude of the clock signal CLK by the threshold voltage is supplied to the gate of the transistor Q 5 (at this time, the clock signal /CLK is at L level and the transistor Q 10 is OFF).
  • transistor Q 9 functions as a diode in which the first clock terminal CK 1 is an anode and the node N 3 is cathode (that is, a conducting direction (charge direction) is from the first clock terminal CK 1 to the node N 3 ), when the clock signal CLK returns to L level, the node N 3 of the transistor Q 9 cannot be discharged. However, since the clock signal /CLK becomes H level at this time, the node N 3 is discharged through the transistor Q 10 and becomes L level. As a result, the transistor Q 5 operates almost similar to the embodiment 1.
  • An embodiment 6 shows a variation of the level adjustment circuit 100 described in the embodiment 5.
  • a level adjustment circuit 100 in which two diode-connected transistors Q 9 and Q 10 connected between a node N 3 and a first clock terminal CK 1 in series may be used as shown in FIG. 18 . Since the H level of the signal supplied to the gate of the transistor Q 5 is reduced by the threshold voltage of the transistor Q 11 as compared with the level adjustment circuit 100 shown in FIG. 17 , the current flowing in the transistor Q 5 can be further effectively prevented.
  • the source of the transistor Q 10 is connected to the first power supply terminal S 1 in FIG. 17 , it may be connected to the first clock terminal CK 1 as shown in FIG. 19 .
  • the clock signal /CLK becomes L level and the transistor Q 10 is turned off, since the clock signal CLK inputted to the source becomes H level, the same state equivalent to a case where the gate of the transistor Q 10 is negatively biased with respect to the source is provided.
  • the threshold voltage of the positively shifted transistor Q 10 returns to the negative direction and makes a recovery, the operation life of the circuit can be elongated.
  • the gate width of the transistor Q 5 is large and its gate capacity is considerably large compared with the parasitic capacity (not shown) associated with the node N 3 , it is considered that the level of the node N 3 rises due to the coupling through the overlap capacity between the gate and drain of the transistor Q 5 at the time of the rising of the output signal G n .
  • the transistor Q 5 is turned on while the output signal G n is at H level, which causes the level of the node N 1 to be lowered.
  • a diode-connected transistor Q 12 in which a forward direction (discharge direction) is from the node N 3 to the first clock terminal CK 1 may be provided between the node N 3 and the first clock terminal CK 1 in a level adjustment circuit 100 .
  • the transistor Q 12 when the level of the node N 3 rises more than the sum of the H level (VDD) of the clock signal CLK and the threshold voltage (Vth (Q 12 )) of the transistor Q 12 , a current flows from the node N 3 to the first clock terminal CK 1 to clamp the level of the node N 3 at the VDD+Vth (Q 12 ) level.
  • the transistor Q 12 is provided in the level adjustment circuit 100 shown in FIG. 17 as shown in FIG. 20
  • the transistor Q 12 may be provided in the level adjustment circuit 100 shown in FIG. 18 as shown in FIG. 21 or it may be provided in the level adjustment circuit 100 shown in FIG. 19 as shown in FIG. 22 .
  • FIG. 23 is a circuit diagram showing a unit shift register SR according to an embodiment 7 of the present invention. This embodiment is effective in the case where the power supply for supplying the high potential side power supply potential VDD is used as a charging power supply of the node N 1 through the transistor Q 3 like the embodiment 2 ( FIG. 12 ).
  • the transistor Q 5 is OFF and the node N 1 is at L level of the floating state, so that the electric charges due to the leak current of the transistor Q 3 are stored in the node N 1 .
  • the potential of the node N 1 rises when the leak current is large.
  • the clock signal CLK becomes H level
  • the level of the node N 1 rises due to coupling through the overlap capacity of the transistor Q 1 .
  • the transistor Q 1 is likely to be turned on even in the non-selected period, and a defective operation could be generated.
  • the unit shift register SR shown in FIG. 23 is provided to solve the above problem.
  • the unit shift register will be described hereinafter.
  • a circuit comprising transistors Q 13 to Q 15 is connected to the circuit shown in FIG. 12 .
  • the transistor Q 13 is connected between a node N 1 and a first power supply terminal S 1 .
  • the transistors Q 14 and Q 16 are connected in parallel between the node N 4 and the first power supply terminal S 1 .
  • the gate of the transistor Q 14 is connected to the node N 1 and the gate of the transistor Q 16 is connected to a first clock terminal CK 1 .
  • the transistor Q 15 is a diode-connected transistor and connected between the node N 4 and a second clock terminal CK 2 . That is, the gate and drain of the transistor Q 15 are connected to the second clock terminal CK 2 .
  • the on resistance of the transistor Q 14 is sufficiently smaller than that of the transistor Q 15 . Therefore, in a case where it is assumed that a clock signal /CLK is at H level, when the node N 1 becomes H level and the transistor Q 14 is turned on, the node N 4 becomes L level. That is, the transistors Q 14 and Q 15 constitute a ratio inverter in which the node N 1 is an input node and the node N 4 is an output node, and the transistor Q 14 (sixth transistor) functions as a driver element of the inverter and the transistor Q 15 (seventh transistor) functions as a load element. However, since in this inverter, the clock signal /CLK is used as a power supply to be supplied to the drain of the transistor Q 15 , the inverter is activated while the clock signal /CLK is at H level.
  • the transistor Q 16 is turned on when the clock signal CLK is at H level, and discharges the node N 4 . That is, the transistor Q 16 is a transistor (eighth transistor) that discharges the output node (node N 4 ) of the inverter when the clock signal /CLK is at L level and the inverter is inactive.
  • the transistor Q 13 is a transistor (fifth transistor) that discharges the node N 1 based on the output of the inverter comprising the transistors Q 14 and Q 15 .
  • This transistor Q 13 only have to flow a current as small as a leak current of the transistor Q 3 , so that its on resistance is not necessarily low. Therefore, the transistor Q 13 may be small in size.
  • FIG. 24 is a timing chart showing the operation of the unit shift register SR shown in FIG. 23 .
  • the operation of the unit shift register SR will be described with reference to FIG. 23 hereinafter, since its basic operation is the same as that described with reference to FIG. 8 , the operation related to the circuit comprising the transistors Q 13 to Q 15 will be mainly described.
  • the node N 1 is in a reset state at L level and the first clock terminal CK 1 (clock signal CLK) is at H level, and the second clock terminal CK 2 (clock signal /CLK), a reset terminal RST (next stage output signal G n+1 ) and an input terminal IN (previous stage output signal G n ⁇ 1 ) are at L level.
  • the transistor Q 3 is turned on and the level of the node N 1 rises.
  • the inverter comprising the transistors Q 14 and Q 15 is activated. Since the transistor Q 15 is turned on at this time, the level of the node N 4 rises and the transistor Q 13 is going to be conductive, but since the on resistance of the transistor Q 3 is set sufficiently low as compared with the on resistance of the transistor Q 13 , the potential of the node N 1 rises and becomes H level (VDD ⁇ Vth) here. Accordingly, the transistor Q 14 is turned on and the node N 4 becomes L level determined by the on resistance ratio between the transistors Q 15 and Q 14 . As a result, the unit shift register SR becomes the set state and the transistor Q 1 is turned on.
  • the transistor Q 3 is turned off and the node N 1 becomes a floating state of H level.
  • the clock signal /CLK also becomes L level, the transistor Q 15 is turned off and the inverter comprising the transistors Q 14 and Q 15 becomes inactive.
  • the level of the node N 4 becomes VSS.
  • the clock signal /CLK becomes H level and the next stage output signal G n+1 becomes H level.
  • the transistor Q 4 is turned on and the level of the node N 1 falls and accordingly the transistor Q 14 is turned off.
  • the transistor Q 15 is turned on and the inverter comprising the transistors Q 14 and 15 is activated, so that the node N 4 becomes H level and the transistor Q 13 is turned on. Accordingly, the node N 1 becomes the reset state of L level.
  • the transistor Q 15 When the clock signal /CLK becomes L level at a time t 6 , the transistor Q 15 is turned off and the inverter comprising the transistors Q 14 and Q 15 is inactivated. However, since the node N 4 becomes H level of the floating state, the transistor Q 13 is still ON and electric charge due to the leak current of the transistor Q 3 is prevented from being accumulated in the node N 1 .
  • the node N 1 is discharged (pulled down) through the transistor Q 5 and when the clock signal /CLK becomes H level, it is discharged through the transistor Q 13 . That is, since this operation is repeated in the non-selected period, the level of the node N 1 is prevented from rising.
  • the node N 1 is prevented from becoming the floating state in the non-selected period of the unit shift register SR, it is prevented that the potential of the node N 1 rises due to the leak current of the transistor Q 3 . That is, a defective operation in the non-selected period can be further prevented and the reliability of the operation can be improved.
  • the node N 1 is discharged by the two transistors such as the transistors Q 5 and Q 13 alternately. That is, since their gates are not continuously biased in the non-selected period but biased at the timing when the clock signals CLK and /CLK become H level, it has an advantage that the problem in the shift of the threshold voltages of the transistors Q 5 and Q 13 is alleviated.
  • the transistor Q 15 is diode-connected and the clock signal /CLK is supplied to both gate and drain thereof in FIG. 23
  • the clock signal /CLK may be supplied to only the gate of the transistor Q 5 and another voltage supply may be supplied to the drain.
  • the drain of the transistor Q 15 may be connected to a second power supply terminal S 2 and the high potential side power supply potential VDD may be supplied.
  • the source of the transistor Q 16 may be connected to the second clock terminal CK 2 and the clock signal /CLK may be supplied.
  • the clock signal CLK inputted to the gate of the transistor Q 16 becomes L level and the transistor Q 16 is turned off, since the clock signal /CLK inputted to the source becomes H level, a state equivalent to the case where the gate of the transistor Q 16 is negatively biased with respect to the source is provided.
  • the positively shifted threshold voltage returns to the negative direction and makes a recovery, the drive capability of the transistor Q 16 is prevented from being lowered.
  • the transistor Q 16 can be reduced in size.
  • the gate of the transistor Q 2 may be connected to the node N 4 .
  • the level of the node N 4 in the non-selected period becomes H level when the clock signal /CLK rises, and becomes L level when the clock signal CLK rises, so that the same operation as the above can be implemented.
  • the degree of freedom in the layout of the circuit can be increased and the area occupied by the circuit can be easily reduced.
  • the clock signal CLK is directly inputted to the gate of the transistor Q 5 in the unit shift register SR shown in FIG. 23
  • the level adjustment circuit 100 shown in the embodiments 5 and 6 may be used as a matter of course.
  • the source of the transistor Q 2 is connected to the first power supply terminal S 1 in FIG. 23 , it may be connected to the first clock terminal CK 1 like in the embodiment 3 ( FIG. 13 ) as a matter of course.
  • FIG. 28 is a circuit diagram showing a unit shift register SR according to an embodiment 8 of the present invention.
  • a constitution in which a transistor Q 16 (eighth transistor) for discharging an output node (node N 4 ) when an inverter comprising transistors Q 14 and Q 15 is inactive is connected between a second clock terminal CK 2 and the node N 4 is provided in the circuit shown in FIG. 23 .
  • the gate of the transistor Q 16 is connected to the node N 4 . That is, the transistor Q 16 is diode-connected and functions as a one-way switching element in which a forward direction is from the node N 4 to a second clock terminal CK 2 .
  • FIG. 29 is a timing chart showing the operation of the unit shift register SR in FIG. 28 . Since operations until a time t 6 are the same as those of the unit shift register SR shown in 23 described with reference to FIG. 24 , their description will be omitted here.
  • this embodiment is different from the embodiment 7 in that the timing when the node N 4 is discharged is at the time of falling of the clock signal /CLK (time t 6 ) and the level of the node N 4 after discharged is at the threshold voltage of the transistor Q 16 , other operations are almost the same and the same effect can be provided.
  • the transistor Q 15 is diode-connected and the clock signal /CLK is supplied to both gate and drain thereof in FIG. 28
  • the clock signal /CLK may be supplied to only the gate of the transistor Q 5 and another voltage supply may be supplied to the drain.
  • the drain of the transistor Q 15 may be connected to a second power supply terminal S 2 and the high potential side power supply potential VDD may be supplied to it (refer to FIG. 25 ).
  • the gate of the transistor Q 2 may be connected to the node N 4 . Since the level of the node N 4 in the non-selected period follows the level of the clock signal /CLK, the same operation as the above can be performed in this constitution. Thus, the degree of freedom of the layout of the circuit is increased and the area occupied by the circuit can be easily reduced.
  • the clock signal CLK is directly inputted to the gate of the transistor Q 5 in the unit shift register SR shown in FIG. 28 , the level adjustment circuit 100 shown in the embodiments 5 and 6 ( FIGS. 17 to 22 ) may be used.
  • the source of the transistor Q 2 is connected to the first power supply terminal S 1 in FIG. 28 , it may be connected to the first clock terminal CK 1 like in the embodiment 3 ( FIG. 13 ).
  • FIG. 31 is a circuit diagram showing a unit shift register SR according to an embodiment 9.
  • the transistors Q 15 and Q 16 shown in FIG. 23 are replaced with a capacity element C 4 .
  • the capacity element C 4 is connected between a node N 4 and a second clock terminal CK 2 .
  • a transistor Q 14 is connected between the node N 4 and a first power supply terminal S 1 like in FIG. 23 , and its gate is connected to a node N 1 .
  • the circuit comprising the transistor Q 14 and the capacity element C 4 also functions as an inverter that is activated when a clock signal /CLK becomes H level. That is, when its input node (node N 1 ) is at L level, since the transistor Q 14 is OFF, its output node (node N 4 ) becomes H level due to coupling through the capacity element C 4 when the clock signal /CLK becomes H level. Meanwhile, in a case where the input node (node N 1 ) is at H level, since the transistor Q 14 is OFF, even when the clock signal /CLK becomes H level, the output node (node N 4 ) does not rise but becomes L level.
  • FIG. 32 is a timing chart showing the operation of the unit shift register SR shown in FIG. 31 .
  • the operation of the unit shift register SR will be described with reference to FIG. 32 , since its basic operation is the same as that described with reference to FIG. 29 , the behavior of the level of the node N 4 will be mainly described.
  • the node N 1 is in a reset state at L level and the first clock terminal CK 1 (clock signal CLK) is at H level, and the second clock terminal CK 2 (clock signal /CLK), a reset terminal RST (next stage output signal G n+1 ), and an input terminal IN (previous stage output signal G n ⁇ 1 ) are at L level.
  • the clock signal /CLK rises at a time t 1 .
  • the level of the node N 4 rises due to the capacity coupling through the capacity element C 4 , since the transistor Q 3 is turned on and the node N 1 becomes H level at this time, the transistor Q 14 is turned on and the node N 4 is immediately discharged to VSS level. That is, although the node N 4 becomes H level instantly, since the node N 2 is charged by the transistor Q 3 at this time, the node N 1 becomes H level without any problem.
  • the clock signal /CLK falls and the level of the node N 4 falls at a time t 2 , it returns to VSS level immediately because the node N 1 is at H level and the transistor Q 14 is ON.
  • the clock signal /CLK falls and the level of the node N 4 falls at a time t 6 at the same time.
  • the level of the node N 1 is at VSS level, when the voltage between the gate (node N 1 ) and the source (here, node N 4 in view of potential relation) of the transistor Q 14 becomes Vth or more, the transistor Q 14 is turned on. As a result, the level of the node N 4 becomes ⁇ Vth (Q 14 ) that is lower than VSS by the threshold voltage of the transistor Q 14 .
  • the transistor Q 13 Since the transistor Q 13 is OFF at this time, the node N 1 becomes a floating state and the electric charge due to the leak current of the transistor Q 3 is accumulated in the node N 1 . However, when the clock signal CLK becomes H level at a time t 7 just after that, since the transistor Q 5 is turned on, the electric charge of the node N 1 is discharged through the transistor Q 5 like in the embodiment 1.
  • the node N 1 becomes the floating state again and the electric charge due to the leak current of the transistor Q 3 starts to be accumulated.
  • the clock signal /CLK becomes H level at a time t 9 just after that, the node N 4 rises by a predetermined voltage ( ⁇ V shown in FIG. 32 ) and becomes H level due to the coupling through the capacity element C 4 .
  • the node N 1 is at L level and the transistor Q 13 is OFF, while the clock signal /CLK is at H level, the H level of the node N 4 is maintained. Since the rising voltage value ( ⁇ V) is determined by the capacity element C 4 and the parasitic capacity of the node N 4 , the capacity element C 4 is set to the value previously so as to be sufficiently at H level.
  • the gate of the transistor Q 2 may be connected to the node N 4 . Since the level of the node N 4 in the non-selected period follows the level of the clock signal /CLK, the same operation as the above can be performed even in such constitution. Thus, the degree of freedom of the layout of the circuit can be increased and the area occupied by the circuit can be easily reduced. However, it is to be noted that since the parasitic capacity value of the node N 4 is increased, it is necessary to increase the capacity value of the capacity element C 4 considerably to keep the voltage value ( ⁇ V) that rises at the time t 9 great.
  • the clock signal CLK is directly inputted to the gate of the transistor Q 5 in the unit shift register SR shown in FIG. 31 , the level adjustment circuit 100 shown in the embodiments 5 and 6 ( FIGS. 17 to 22 ) may be used of course.
  • the source of the transistor Q 2 is connected to the first power supply terminal S 1 in FIG. 31 , it may be connected to the first clock terminal CK 1 like in the embodiment 3 ( FIG. 13 ).
  • FIG. 34 is a circuit diagram showing a unit shift register SR according to an embodiment 10.
  • the gate of the transistor Q 14 is connected to the input terminal IN in the unit shift register SR in the embodiment 7 ( FIG. 23 ). That is, to the gate of the transistor Q 14 of the unit shift register SR, its previous stage output signal (a start pulse SP in the case of the first stage) is inputted.
  • the transistor Q 14 of the circuit in FIG. 23 is turned on while the node N 1 is at H level (for times t 1 to t 5 in FIG. 24 ), the transistor Q 14 of the unit shift register SR in FIG. 34 is turned on while the input terminal IN (previous stage output signal or start pulse SP) is at H level (for times t 1 to t 2 in FIG. 24 ). Therefore, although the timing of the unit shift register SR in the embodiment 10 when the transistor Q 14 returns to OFF is earlier, since a transistor Q 16 is turned on just after the transistor Q 14 has returned to OFF to discharge the node N 4 , the operation of the unit shift register SR is almost the same as that of the embodiment 7. Therefore, the same effect as that in the embodiment 7 can be provided in this embodiment also.
  • the transistor Q 14 in FIG. 23 is turned on after the node N 1 has started to be charged, the transistor Q 14 in FIG. 34 is immediately turned on when the previous stage output signal rises. Therefore, according to this embodiment, since the transistor Q 13 can be surely turned on when the node N 1 starts to be charged, the node N 1 can be easily charged.
  • the parasitic capacity associated with the node N 1 is smaller by the gate capacity of the transistor Q 14 as compared with the circuit in FIG. 23 . Therefore, the node N 1 can rise more effectively when the output signal is outputted (selected period), which contributes to the drive capability of the transistor Q 1 , that is, the improvement in the drive capability of the unit shift register SR.
  • this embodiment can be widely applied to the unit shift register SR (embodiments 7 to 9) comprising the inverter containing the transistor Q 14 .
  • the level adjustment circuit 100 shown in the embodiments 5 and 6 ( FIGS. 17 to 22 ) can be applied to the unit shift register SR in this embodiment.
  • the source of the transistor Q 2 may be connected to the first clock terminal CK 1 like in the embodiment 3.
  • FIG. 35 is a circuit diagram showing a unit shift register SR according to an embodiment 11 of the present invention. According to this embodiment, the source of the transistor Q 13 is connected to the first clock terminal CK 1 in the unit shift register SR in the embodiment 7 ( FIG. 23 ).
  • a node N 4 of a n-th unit shift register SR n becomes repeatedly H level approximately in synchronization with a clock signal /CLK in a non-selected period (more specifically, it becomes H level when the clock signal /CLK rises and becomes L level when a clock signal CLK rises). Since the source of the transistor Q 13 is fixed to the potential VSS in the circuit shown in FIG. 23 , the gate is repeatedly positively biased, so that its threshold voltage is likely to be shifted.
  • this embodiment can be widely applied to the unit shift register SR (embodiments 7 to 10) containing the transistor Q 13 .
  • the level adjustment circuit 100 shown in the embodiments 5 and 6 ( FIGS. 17 to 22 ) can be applied to the unit shift register SR in this embodiment.
  • the source of the transistor Q 2 may be connected to the first clock terminal CK 1 like in the embodiment 3.
  • each unit shift register SR has the level adjustment circuit 100 in the embodiment 5 ( FIG. 17 ), the plurality of unit shift registers can share one level adjustment circuit 100 .
  • FIG. 36 is a view showing a shift register according to an embodiment 12, in which multistage (plural-stage) shift register comprises the plurality of cascade-connected unit shift registers SR.
  • multistage (plural-stage) shift register comprises the plurality of cascade-connected unit shift registers SR.
  • FIG. 36 four stages from n-th to (n+3)th circuits are shown (it is assumed that n is an odd number).
  • the multistage shift register comprises a level adjustment circuit (common level adjustment circuit) 100 A shared by odd-stage unit shift registers SR and a level adjustment circuit (common level adjustment circuit) 100 B shared by even-stage unit shift registers SR. Therefore, the gate node (node N 3 in FIG. 17 ) of odd-stage transistors Q 5 are shared and similarly, the gate node of even-stage transistors Q 5 are shared.
  • the common node N 3 in the odd stages is referred to as the “node N 3 A” and the common node N 3 in the even stages is referred to as the “node N 3 B”.
  • the common level adjustment circuits 100 A and 100 B have the same circuit constitution as that of the level adjustment circuit 100 shown in FIG. 17 . That is, transistors Q 9 A and Q 9 B in FIG. 36 correspond to the transistor Q 9 shown in FIG. 17 , transistors Q 10 A and Q 10 B in FIG. 36 correspond to the transistor Q 10 shown in FIG. 17 , and clock terminals CK 1 A and CK 1 B in FIG. 36 correspond to the first clock terminal CK 1 shown in FIG. 17 .
  • the common level adjustment circuits 100 A and 100 B may have any circuit constitution shown in FIGS. 17 to 22 .
  • the common level adjustment circuit 100 A generates a signal having an amplitude smaller than that of the clock signal CLK and supplies it to the node N 3 A (more specifically, the node N 3 A becomes H level at the time of rising of the clock signal CLK and becomes L level at the time of rising of the clock signal /CLK).
  • the common level adjustment circuit 100 B generates a signal having an amplitude smaller than that of the clock signal /CLK and supplies it to the node N 3 B (more specifically, the node N 3 B becomes H level at the time of rising of the clock signal /CLK and becomes L level at the time of rising of the clock signal CLK).
  • each unit shift register SR can perform the same operation as that of the unit shift register SR shown in FIG. 17 , so that the same effect as that of the embodiment 5 is provided. Furthermore, since the plurality of unit shift registers SR share the common level adjustment circuits 100 A and 100 B, which contributes to the reduction in the area where the circuit is formed.
  • the gate node (node N 3 A) of the transistor Q 5 is shared by the odd-stage unit shift registers SR and similarly, the gate node (node N 3 B) of the transistor Q 5 is shared by the even-stage unit shift registers SR. That is, the gate capacities of the transistors Q 5 of the unit shift registers SR contribute to the parasitic capacities of the nodes N 3 A and N 3 B. Therefore, the parasitic capacity associated with the gate node of the transistor Q 5 in each unit shift register SR is considerably large as compared with the circuit shown in FIG. 17 , so that the above problem does not arise. Therefore, there is no need to provide the transistor Q 12 in the common level adjustment circuits 100 A and 100 B unlike the level adjustment circuit 100 shown in FIG. 20 .
  • the unit shift register SR has the circuit constitution shown in FIG. 17 is shown in FIG. 36 , it can be widely applied to the unit shift register SR comprising the level adjustment circuit 100 .
  • FIG. 37 is a view showing the constitution of a shift register according to an embodiment 13, in which a plurality of unit shift registers SR are cascade-connected in the multistage shift register. In this drawing also, four stages from n-th to (n+3)th circuits are shown (it is assumed that n is a odd number).
  • a transistor Q 10 of the transistors Q 9 and Q 10 constituting the level adjustment circuit 100 is shared and the transistor Q 9 is provided in each of the unit shift registers SR. That is, common level adjustment circuits 100 A and 100 B comprise only transistors Q 10 A and Q 10 B, respectively.
  • the current (I (Q 5 )) flowing in the transistor Q 5 at the time of the rising of the output signal affects the relation of the timing between the rising of the gate of the transistor Q 5 (clock signal CLK in the example of FIG. 9 ) and the rising of the output signal.
  • the timing when the gate of the transistor Q 5 becomes H level is almost constant in each unit shift register SR, the variation in current of the transistor Q 5 is prevented. Therefore, the electric charge can be prevented from leaking from the node N 1 to the output terminal OUT when the output signal rises.
  • FIG. 38 is a view showing the constitution of a multistage shift register according to an embodiment 14 of the present invention.
  • a plurality of unit shift registers SR share common level adjustment circuits 100 A and 100 B like in the embodiments 12 and 13.
  • FIG. 38 shows the arrangements of the plurality of unit shift registers SR and the common level adjustment circuits 100 A and 100 B.
  • the current flowing in the transistor Q 5 at the time of rising of the output signal is affected by the timing relation between the rising of the gate of the transistor Q 5 and the rising of the output signal. Therefore, it is preferable that the timing relation is constant among all unit shift registers SR.
  • a multistage shift register constituting a gate line drive circuit 30 of a display comprises several hundreds of cascade-connected unit shift registers SR ( 640 stages in the display of VGA size, for example).
  • the length of the wiring (clock wiring) required when the unit shift registers SR share the clock signals CLK and /CLK is several centimeters, so that the influence of the parasitic impedance of the clock wiring cannot be ignored.
  • the common level adjustment circuits 100 A and 100 B are arranged close to the unit shift register SR 1 that is closest to the external connection terminals 102 A and 102 B. That is, it means that the unit shift registers SR 1 , ST 2 , . . . , SR n are connected in this order from the side closer to the common level adjustment circuits 100 A and 100 B in the wiring as the nodes N 3 A and N 3 B. That is, the distance from the unit shift register SR to the external connection terminals 102 A and 102 B and the distance from the unit shift register SR to the common level adjustment circuits 100 A and 100 B are almost equal to each other.
  • the signals (having amplitudes smaller than the clock signals CLK and /CLK) outputted from the common level adjustment circuits 100 A and 100 B are transmitted to each unit shift register SR through the wiring of the nodes N 3 A and N 3 B, and the same delay as that of the clock wirings 101 A and 101 B is generated in these wiring theoretically. Therefore, according to this embodiment, the phase relation between the clock signals CLK and /CLK from the external connection terminals 102 A and 102 B and the signals from the common level adjustment circuits 100 A and 100 B can be almost constant over all of the unit shift registers SR.
  • the common level adjustment circuits 100 A and 100 B are provided close to the unit shift register SR 1 .
  • a unit shift register SR other than the first stage unit shift register SR 1 is closest to the external connection terminals 102 A and 102 B depending on its layout. That is, the common level adjustment circuits 100 A and 100 B only have to be arranged close to the external connection terminals 102 A and 102 B or close to the unit shift register SR that is closest to the external connection terminals 102 A and 102 B.

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US20110182399A1 (en) 2011-07-28
US8493309B2 (en) 2013-07-23
KR100857479B1 (ko) 2008-09-08
JP2007317344A (ja) 2007-12-06
TW200746169A (en) 2007-12-16
US8816949B2 (en) 2014-08-26
JP5079350B2 (ja) 2012-11-21
US20130272487A1 (en) 2013-10-17

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