Classifications

• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D7/00—Electroplating characterised by the article coated
  • C25D7/12—Semiconductors
  • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D3/00—Electroplating: Baths therefor
  • C25D3/02—Electroplating: Baths therefor from solutions
  • C25D3/38—Electroplating: Baths therefor from solutions of copper
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/34—Pretreatment of metallic surfaces to be electroplated
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
  • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

Definitions

• the present invention relates in general to an electroplating composition intended for coating a surface of a substrate with copper, especially a surface consisting of an electrically resistive material, in particular for the coating of a copper-diffusion barrier layer.
• the invention is especially applicable in the field of microelectronics for the fabrication of interconnects in integrated circuits. It is also applicable in other fields of electronics, for the fabrication of inter-connects in printed circuits (called printed circuit boards or printed wire boards) or for the fabrication of passive elements, such as inductors, or in the electromechanical field in integrated circuits or in microsystems (called microelectromechanical systems).
• electroroplating is understood here to mean a method of covering a surface of a substrate with a metallic or organometallic coating, in which the substrate is electrically biased and brought into contact with a liquid that contains precursors of the said metallic or organometallic coating, so as to form the said coating.
• the electroplating is for example carried out by passing a current between the substrate to be coated which constitutes an electrode (the cathode in the case of a metallic or organometallic coating) and a second electrode (the anode) in a bath containing a source of precursors of the coating material (for example metal ions in the case of a metallic coating) and optionally various agents intended to improve the properties of the formed coating (uniformity and fineness of the deposit, resistivity, etc.), optionally with a reference electrode being present.
• a source of precursors of the coating material for example metal ions in the case of a metallic coating
• various agents intended to improve the properties of the formed coating optionally with a reference electrode being present.
• Copper electroplating is used in particular in the microelectronics field for the fabrication of interconnects in integrated circuits.
• Integrated circuits are generally fabricated by forming active semiconductor devices, especially transistors, on the surface of silicon wafers, the said semiconductor devices being connected together by a system of metal interconnects consisting of “lines” and “contacts”, also called “vias”, placed in superimposed levels and obtained by respectively filling “trenches” and “wells” also called “interconnection holes”, made in the dielectric layers.
• the interconnects are generally produced by a sequence of steps comprising:
• the barrier layer generally has too high a resistance for copper to be electrochemically deposited homogeneously or uniformly at the wafer scale, an effect known to those skilled in the art by the term “ohmic drop”.
• the high resistance of the barrier layer results both from the high resistivity of its constituent materials (generally metal nitrides) and from its small thickness (generally from a few nm to a few tens of nm, depending on the integrated circuit generation), which thickness is imposed by the small size of the interconnect features.
• a seed layer is generally necessary, prior to the copper electroplating step, to cover the barrier layer—using a non-electrochemical method—with a thin layer of metallic copper, called a seed layer.
• This seed layer like the barrier layer, is currently produced by vapor phase deposition techniques such as PVD (physical vapor deposition) or CVD (chemical vapor deposition).
• the thickness of the copper seed layers at the present time is around 30 nm and should rapidly move towards 10 nm or less.
• CVD deposition produces a conformal copper layer, that is to say one that accurately matches the topography of the surface to be coated, and does so for a wide range of aspect ratios.
• adhesion to the diffusion barriers of the copper layers formed by chemical deposition is poor. This limits in practice the benefit of this type of process since strong adhesion between the copper and the barrier is required in order to ensure reliability of the structures constituting the interconnects.
• PVD deposition is presently preferred from the industrial standpoint because it allows surfaces having a high resistance to be coated with better adhesion of the copper to the barrier than obtained with CVD processes.
• the thickness of the coating deposited by PVD is directly proportional to the solid angle seen from the surface to be coated. Consequently, those portions of the surface having salient angles are covered with a thicker layer than those portions of the surface having re-entrant angles.
• the copper seed layers formed by physical vapor deposition are not conformal, and therefore do not have a uniform thickness at every point on the surface of the substrate.
• shadow or overhang effects are observed at the sharp edges of trenches or vias, up to the point of obstructing their apertures and then making it impossible to fill them.
• the sidewalls of the trenches and vias may be covered with an insufficient thickness of the seed layer, which then results in imperfect subsequent filling, missing material or voids.
• the seed layer produced on the sidewalls of the features exhibits by nature an adhesion that differs from that deposited on the flat surface of the substrate (at the top and bottom of the trenches and vias). This may lead to inferior reliability properties, such as resistance to electromigration. In other words, the non-conformal coverage does not solely result in differences in thickness as lack of continuity and poor adhesion of the layer on the sidewalls of the trenches and vias may also arise therefrom.
• the electroplating technique presented here constitutes an advantageous alternative to chemical vapor deposition or physical vapor deposition processes, and to the more conventional metal electroplating techniques, which cannot be implemented on resistive substrates.
• Sheet resistance is a quantity used by those skilled in the art for measuring electrical resistance of thin films or layers. It is expressed in ohms/square and is equivalent to the resistivity for a two-dimensional system, that is to say one in which the current flows in the plane of the layer and not in a plane perpendicular to this layer. Mathematically, the value of the sheet resistance is obtained by dividing the resistivity (expressed in ohms ⁇ m or microohms ⁇ cm) of the constituent material of the layer by the thickness (expressed in m or nm) of this layer.
• conventional copper electroplating is mainly used for filling the trenches and wells in the damascene process by applying a DC current to a wafer covered beforehand with a seed layer and immersed in an acid copper sulphate bath containing additives.
• This process for filling the trenches and wells with metallic copper is described for example by Rosenberg et al., in “Copper metallization for high performance silicon technology”, Ann. Rev. Mater. Sci (2000), 30, 229-62.
• Copper electroplating has also been recommended, for example in U.S. Pat. No. 6,811,675, for filling any voids in the seed layer or for repairing this layer (seed repair or seed enhancement).
• a first step is carried out, preferably by a physical vapor deposition process, in which a non-uniform “ultrathin” (thickness of about 20 nm) copper seed layer is deposited and then in a second step the conformality of the layer is improved by electroplating using an alkaline electroplating solution (the pH of which is greater than 9) containing copper sulphate, a copper complexing agent, preferably citric acid, and optionally boric acid in order to improve the brightness of the coating and/or ammonium sulphate for reducing the resistivity of the coating.
• the current density applied during electroplating is between 1 mA/cm 2 and 5 mA/cm 2 .
• the object of the present invention is to solve a new technical problem, namely of how to provide a novel electroplating composition which makes it possible in particular to produce continuous and conformal copper seed layers having a thickness of the order of 10 nm or less and exhibiting excellent adhesion to diffusion barriers that may have a high surface resistance of up to a few megohms/square.
• the solution according to the present invention for solving this technical problem consists of an electroplating composition intended in particular for coating a copper-diffusion barrier layer in the fabrication of interconnects for integrated circuits, characterized in that it comprises, in solution in a solvent:
• the copper complexing agents that can be used within the context of the present invention may be chosen from:
• the nitrogen heterocycles that constitute one of the preferred classes of complexing agents that can be used within the context of the present invention may be defined as monocyclic or polycyclic compounds, whether fused or not, having 1 to 8 nitrogen atoms, each ring of which contains 5 to 6 members and may or may not be substituted with 1 to 8 atoms or groups of atoms chosen from halogens, hydroxyl and alkyl groups having from 1 to 6 carbon atoms.
• the electroplating composition according to the invention may include one or more complexing agents.
• Such agents which constitute the copper complexing agents currently preferred according to the invention, are especially pyridine, 2,2′-bipyridine and the mixtures thereof.
• the electroplating composition according to the invention includes a source of copper ions, in particular cupric (Cu 2+ ) ions.
• the source of copper ions is a copper salt such as in particular copper sulphate, copper chloride, copper nitrate or copper acetate, preferably copper sulphate.
• the source of copper ions is present within the electroplating composition with a concentration of between 0.4 and 40 mM.
• the copper ion source/copper complexing agent(s) molar ratio in the electroplating composition according to the invention is between 0.1 and 2.5, preferably between 0.3 and 1.3.
• the electroplating composition according to the invention has a pH of less than 7, preferably between 3.5 and 6.5.
• the pH of the composition may optionally be adjusted within the aforementioned pH range by means of a buffer, such as one of those described in “Handbook of Chemistry and Physics”, 84th edition, David R. Lide, CRC Press.
• a currently preferred electroplating composition according to the invention comprises, in aqueous solution:
• the electroplating solution according to the invention may be employed in a standard electroplating method that includes a step in which a coating is formed on a surface of a substrate during which the said surface is biased for a time long enough to form the said coating.
• Embodiments involving more specific potential or current protocols may be preferred when it is desired for the coatings to have particular specifications, and especially coatings that are thin (with a thickness of less than 20 nm, and preferably less than 10 nm), adherent, conformal and uniform.
• the improvement in the adherence of the seed layer to the barrier layer makes it possible, surprisingly, to improve the adhesion of the “seed layer/fill layer or thick copper or thick layer” assembly, that is to say the “operational” adhesion of the assembly for which the seed layer is produced.
• the adhesion of a single seed layer In general, it is difficult for the adhesion of a single seed layer to be measured directly, especially owing to its small thickness, but the results obtained have shown that the adhesion of the seed layers produced according to the present invention is obviously very high.
• the energy of adhesion of the “seed layer/fill layer or thick copper or thick layer” assembly to the barrier layer which energy is the operational property of interest that it is actually to be optimized, is easier and more useful to determine. For example, this adhesion may be determined by peeling an adhesive tape bonded to the upper surface of the assembly, for example using a pulling test system.
• adhesion measured in this way or interfacial energy expressed in J/m 2 , characterizes overall both the adherence of the seed layer to the barrier, and that of the thick copper layer to the seed layer. It does not give precise information about one or the other interface, but it does allow the desired operational property to be quantified, namely the strength of the copper/barrier interface. Consequently, in the present description, “adhesion of the seed layer”, “adhesion of the thick copper layer to the seed layer” and the “strength of the copper/barrier interface after filling” will thus be used interchangeably.
• electroplating compositions according to the invention will preferably be used in an electroplating method comprising:
• the step of forming the coating by electroplating is carried out for a duration sufficient to form the desired coating.
• This duration may be easily determined by a person skilled in the art, the growth of the film being a function of the charge, which is equal to the time integral of the electric current flowing in the circuit over the deposition time (Faraday's law).
• the surface to be coated is biased, either in galvanostatic mode (with a fixed set current) or in potentiostatic mode (with a fixed set potential, optionally relative to a reference electrode) or else in pulsed mode (either the current or the voltage being pulsed).
• a satisfactory coating can be obtained by biasing in galvanostatic mode, preferably within the current range from 0.1 mA/cm 2 (milliamps per square centimetre) to 5 mA/cm 2 , and more particularly from 0.1 mA/cm 2 to 1 mA/cm 2 .
• a satisfactory coating may also be obtained by biasing in potentiostatic mode, by imposing a cell voltage in such a way that the resulting cell current lies within the same current range as indicated previously (0.1 mA/cm 2 to 5 mA/cm 2 , and more particularly from 0.1 mA/cm 2 to 1 mA/cm 2 ).
• the cell voltage depends in particular on cell design parameters, such as the distance from the counterelectrode or the presence of a membrane, it will be easy for a person skilled in the art to determine the cell voltage by measuring and adjusting the current obtained for a given potential and a given configuration.
• a satisfactory coating may also be obtained by biasing in pulsed mode, preferably so as to impose voltage pulses.
• this step may be carried out by imposing voltage pulses corresponding to a maximum current per unit area within the range from 0.1 mA/cm 2 to 5 mA/cm 2 , and more particularly from 0.1 mA/cm 2 to 1 mA/cm 2 , and to a minimum current per unit area within the range from 0 mA/cm 2 to 0.5 mA/cm 2 , and more particularly from 0 mA/cm 2 to 0.1 mA/cm 2 .
• the duration of bias at the maximum voltage may be between 0.15 and 5 seconds, for example around 2 seconds for a voltage corresponding to a maximum current per unit area of around 0.5 mA/cm 2
• the duration of bias at the minimum voltage may be between 0.15 and 7 seconds, for example around 3 seconds, for a voltage corresponding to a minimum current per unit area of around 0.05 mA/cm 2 .
• the number of cycles to be performed during this step depends on the desired thickness of the coating.
• the latter method of implementing the invention has been used in particular to produce copper seed layers on highly resistive substrates, the sheet resistance of which may be up to 100 000 ohms/square, or even a few megohms/square.
• the abovementioned “hot exit” step is carried out in potentiostatic mode, that is to say by keeping the electric potential of the coated substrate (wafer) at a fixed value, this potential being measured either relative to the counterelectrode of the circuit or relative to a reference electrode, preferably at the same voltage level as during the coating deposition step when this is also carried out in potentiostatic mode.
• a second object of the present invention is the use of electroplating compositions described above for coating a copper-diffusion barrier layer in the fabrication of interconnects for integrated circuits.
• compositions according to the invention are used to deposit a copper seed layer on silicon substrates coated with a copper-diffusion barrier layer. These examples are especially applicable in the fabrication of copper interconnect structures for integrated circuits.
• the substrate used in this example consisted of a 200 mm diameter silicon wafer covered with a silica layer having a thickness of 400 nm, itself coated with a tantalum nitride (TaN) layer having a thickness of 15 nm deposited by reactive sputtering and with a tantalum (Ta) layer having a thickness of 10 nm, also deposited by sputtering.
• TaN tantalum nitride
• Ta tantalum
• This TaN/Ta “bilayer” constitutes a copper-diffusion barrier as used in “double damascene” structures in the fabrication of copper interconnects for integrated circuits.
• the electroplating solution used in this example was an aqueous solution containing: 0.3 g/l (or 1.7 mM) of 2,2′-bipyridine; 0.6 g/l (or 2.4 mM) of CuSO 4 .5H 2 O; and 0.3 ml/l (or 3.3 mM) of pyridine.
• the pH of the solution was between 5.8 and 6.2.
• This equipment comprised an electroplating deposition cell in which the seed layer was deposited and a rinse/dry station used after deposition.
• the electroplating deposition cell comprised an anode, made either of an inert metal (for example platinum-coated titanium) or of a metal identical to that constituting the seed layer, in this case copper, the silicon wafer coated with the TaN/Ta barrier layer constituting the cathode of this cell.
• an inert metal for example platinum-coated titanium
• a metal identical to that constituting the seed layer, in this case copper the silicon wafer coated with the TaN/Ta barrier layer constituting the cathode of this cell.
• This cell also included a stabilized power supply for delivering up to 30 V and 4 A and a device for electrically contacting the cathode, physically isolated from the solution by a seal.
• This electrical contacting device generally had a ring shape and allowed the substrate to be biased at various contact points placed uniformly around the said substrate.
• a device for supporting the wafer to be coated including means for rotating the said wafer at a predetermined speed.
• the electroplating method used in this example comprised the following various consecutive steps.
• This step was divided into two substeps:
• the aforementioned substrate was introduced into the electroplating deposition cell so that the face having the TaN/Ta barrier layer came into contact with the electrical contacting device, the latter not yet being electrically powered.
• the assembly formed by the electrical contacting device and the substrate which hereafter will be referred as the “cathode assembly”, was bought into contact, for example by immersion, with the electroplating solution. This contacting step, generally lasting 5 seconds or less (for example 2 seconds), was carried out while the device was still not electrically powered.
• the cathode assembly was preferably then kept in the electroplating solution without being biased for a period of at least 5 seconds (for example around 30 seconds).
• the cathode assembly was then biased in potentiostatic mode by imposing a cell voltage corresponding to a current per unit area of generally between 0.4 mA/cm 2 and 0.8 mA/cm 2 (for example 0.6 mA/cm 2 ) and at the same time rotated at a speed of 20 to 60 rounds per minute (for example 40 rounds per minute).
• This step dependsed, as will have been understood, on the targeted thickness of the seed layer. This duration can be easily determined by a person skilled in the art, the growth of the film depending on the charge passed in the circuit.
• the deposition rate was about 1 nm per coulomb of charge passed in the circuit.
• the duration of the electroplating step was around 50 seconds for obtaining a coating having a thickness of 10 nm, and around 200 seconds for obtaining a coating having a thickness of 40 nm.
• This step may be divided into two substeps:
• the copper-coated cathode assembly was withdrawn from the electroplating solution with a zero speed of rotation, while being maintained under voltage bias. The duration of this phase was about 2 seconds.
• the speed of rotation was then increased to 500 rounds per minute for 10 seconds, the cathode assembly bias being cut off during this final phase.
• a pre-rinse with deionized water was carried out in the cell.
• the substrate coated with the seed layer was then transferred into the rinsing/drying module in order to be rinsed with deionized water.
• the rinsing water was then removed, and then a drying operation under a stream of nitrogen was carried out.
• the exit step and in particular the removal of the cathode assembly from the electroplating solution, was carried out under voltage bias at the same level as during the step of forming the coating.
• Conformality was assessed by observing scanning electron microscope cross sections and comparing the thickness of the seed layer on the horizontal surfaces with that on the vertical surfaces.
• the sheet resistance was measured using a “4-point” measurement instrument well known to those skilled in the art.
• the adhesion or interfacial energy was measured after electrochemical deposition of a 500 nm thick copper layer (plating layer) on the seed layer. This measurement was carried out using an apparatus (pulling test system) that applied an increasing vertical pulling force on the surface via a strong adhesive tape until the copper layer (seed layer and plating layer) separates from the substrate.
• the work of this force (force multiplied by length of the layer that has delaminated) is equivalent to the energy that had to be supplied in order to separate the copper layer from its substrate. By dividing this energy by the area that has delaminated, the energy per unit area is obtained.
• the substrate used in this example consisted of a silicon coupon 6 cm in length and 2 cm in width, coated with a silica layer having a thickness of 400 nm, itself coated with a tantalum nitride (TaN) layer having a thickness of 15 nm deposited by reactive sputtering and with a tantalum (Ta) layer having a thickness of 10 nm deposited by sputtering.
• TaN tantalum nitride
• Ta tantalum
• This TaN/Ta “bilayer” constitutes a copper-diffusion barrier as used in “double damascene” structures in the fabrication of the copper interconnects for integrated circuits.
• the electroplating solution used in this example was an aqueous solution containing CuSO 4 .5H 2 O and 2,2′-bipyridine.
• the copper/complexing agent (2,2′-bipyridine) molar ratio varied between 0.1 and 2.5 (for example 1.4) with a CuSO 4 (H 2 O) 5 concentration of 0.2 g/l (or 0.8 mM) for example.
• the pH of the solution was between 4.5 and 5.
• This example used a glass electroplating cell made up of two parts: the cell intended to contain the electroplating solution and a “cover” for maintaining the various electrodes in operative position.
• the electroplating cell had three electrodes:
• Connectors are used to bring into electrical contact the electrodes which are linked via electrical wires to a potentiostat supplying up to 10V and 2 A.
• the electroplating method used in this example comprised the following various consecutive steps.
• the electroplating solution was poured into the cell.
• the various electrodes were placed on the cover of the electroplating cell.
• the electrodes were brought into contact with the electroplating solution under bias.
• the cathode was biased either in galvanostatic mode, within a current range from 1 mA (or 0.125 mA/cm 2 ) to 4 mA (or 0.5 mA/cm 2 ) (for example 2 mA (or 0.25 mA/cm 2 )), or in potentiostatic mode in a potential range from 2 V to 5 V (for example 2 V), or in cyclic voltammetry mode with a potential ramp ranging within a range of potentials from 2 V to 5 V (for example 2 V), a sweep speed of between 20 and 500 mV/s (for example 50 mV/s) and a number of cycles between 2 and 10 (for example 2).
• Degassing with argon may be employed—it allows some hydrodynamic regime to be established in the cell.
• this step depended on the electrochemical deposition mode used (galvanostatic or cyclic voltametry mode). In general, it was between 2 and 15 minutes. For the same deposition mode, this duration depends on the targeted thickness of the seed layer and can be easily determined by a person skilled in the art, the growth of the film being a function of the charge passed in the circuit.
• electrochemical deposition mode galvanostatic or cyclic voltametry mode
• the deposition rate was about 31 nm per coulomb of charge passed in the circuit.
• the duration of the electroplating step in cyclic voltammetry mode was about 480 s in order to obtain a coating having a thickness of about 30 nm.
• the cathode was then disconnected, and thoroughly rinsed with 18 M ⁇ deionized water, then dried using an argon gun with a gas pressure of around 2 bar.
• the copper seed layer having a thickness of 30 nm, had a sheet resistance of 4 ohms/square measured by the method described in Example 1.
• the substrate used in this example was identical to that of Example 2.
• the solution used in this example was an aqueous solution containing 2,2′-bipyridine, pyridine and CuSO 4 (H 2 O) 5 .
• the copper/complexing agents (2,2′-bipyridine and pyridine) molar ratio varied between 0.1 and 2.5 (for example 0.5) with a CUSO 4 (H 2 O) 5 concentration of 0.2 g/l (or 0.8 mM) for example, for mass concentrations of the two complexing agents of the same order of magnitude.
• the pH of the solution was between 5.8 and 6.2.
• the copper seed layers having a thickness of 20 nm and 10 nm, had a sheet resistance of 8 ohms/square and 18 ohms/square respectively, measured by the method described in Example 1.
• the substrate used in this example was identical to that of Example 2.
• the solution used in this example was an aqueous solution containing 3,5-dimethylpyridine and CuSO 4 (H 2 O) 5 .
• the copper/complexing agent (3,5-dimethylpyridine) molar ratio varied between 0.1 and 2.5 (Example 1) with a CuSO 4 (H 2 O) 5 concentration of 0.2 g/l (or 0.8 nM) for example.
• the pH of the solution was between 4.5 and 5.
• the copper seed layers having a thickness of 25 nm and 35 nm, had a sheet resistance of 5 ohms/square and 4 ohms/square respectively, measured by the method described in Example 1.
• the substrate used in this example was identical to that of Example 2.
• the solution used in this example was an aqueous solution containing tetraethylpentamine with a concentration of 0.36 g/l (or 1.9 mM) and CuSO 4 (H 2 O) 5 with a concentration of 0.6 g/l (or 2.4 mM).
• the copper/complexing agent (tetraethylpentamine) molar ratio was 1.26, but could vary between 0.1 and 2.5, for example with a CuSO 4 (H 2 O) 5 concentration of 0.6 g/l.
• the pH of the solution was 5.1.
• the electroplating method used in this example comprised the following various consecutive steps.
• the electroplating solution was poured into the cell.
• the various electrodes were placed on the cover of the electroplating cell.
• the electrodes were brought into contact with the electroplating solution. At this stage, the assembly thus formed was not yet electrically biased (it was at its open-circuit potential).
• the assembly was maintained in this state (i.e. under no electrical bias) for a period of 10 to 60 seconds (for example 30 seconds).
• the cathode was biased in galvanostatic mode within the current range from 2 mA (or 0.25 mA/cm 2 ) to 8 mA (or 1 mA/cm 2 ) (for example 6 mA (or 0.75 mA/cm 2 )).
• Degassing with argon may be employed—it allows some hydrodynamic regime to be established in the cell.
• This step depended on the targeted thickness of the seed layer and could easily be determined by a person skilled in the art, the growth of the film being a function of the charge passed in the circuit.
• the deposition rate was about 33 nm per coulomb of charge passed in the circuit.
• the duration of the electroplating step was about 200 seconds in order to obtain a coating having a thickness of about 40 nm.
• the cathode was then removed from the solution, the bias still being applied.
• the cathode was then disconnected, and thoroughly rinsed with 18 M ⁇ deionized water, then dried using an argon gun with a gas pressure of around 2 bar.
• the copper seed layer having a thickness of 40 nm, had a sheet resistance of 8 ohms/square measured by the method described in Example 1.
• the substrate used in this example consisted of a silicon coupon 6 cm in length by 2 cm in width, coated with a silica layer having a thickness of 400 nm, itself coated with a ruthenium (Ru) layer having a thickness of 30 nm deposited by sputtering.
• the sheet resistance of this substrate was 7.5 ohms/square.
• This Ru layer may constitute a copper-diffusion barrier as used in “double damascene” structures in the fabrication of cover interconnects for advanced integrated circuits.
• the electroplating method used in this example was identical to that of Example 5.
• This copper seed layer had a sheet resistance of 2.5 ohms/square measured by the method described in Example 1.

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• 2005
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  • 2006-09-20 CN CN2006800336529A patent/CN101263247B/zh active Active
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  • 2006-09-20 KR KR1020087006027A patent/KR101350530B1/ko active IP Right Grant
  • 2006-09-20 EP EP06831203.2A patent/EP1937875B1/fr active Active
  • 2006-09-20 CA CA002622917A patent/CA2622917A1/fr not_active Abandoned
  • 2006-09-20 US US11/992,323 patent/US9133560B2/en active Active
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  • 2006-09-20 WO PCT/FR2006/050914 patent/WO2007034116A2/fr active Application Filing
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