US20070050741A1 - Pattern verification method, program thereof, and manufacturing method of semiconductor device - Google Patents

Pattern verification method, program thereof, and manufacturing method of semiconductor device Download PDF

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Publication number
US20070050741A1
US20070050741A1 US11/505,917 US50591706A US2007050741A1 US 20070050741 A1 US20070050741 A1 US 20070050741A1 US 50591706 A US50591706 A US 50591706A US 2007050741 A1 US2007050741 A1 US 2007050741A1
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Prior art keywords
pattern
simulation
integrated circuit
verification
patterns
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Abandoned
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US11/505,917
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English (en)
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Ryuji Ogawa
Koji Hashimoto
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Toshiba Corp
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Individual
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HASHIMOTO, KOJI, OGAWA, RYUJI
Publication of US20070050741A1 publication Critical patent/US20070050741A1/en
Priority to US12/585,073 priority Critical patent/US7987435B2/en
Priority to US13/067,567 priority patent/US8127265B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Definitions

  • the present invention relates to an optical and X-ray lithography technology in manufacture of a semiconductor integrated circuit, a liquid crystal panel or the like, and more particularly to a verification method (lithography simulation) of a semiconductor integrated circuit, a verification program thereof, and a manufacturing method of a semiconductor device.
  • Jpn. Pat. Appln. KOKAI Publication No. 2003-92237 provides means for setting semiconductor process conditions and mask pattern shapes avoiding occurrence of crystal defects based on simulation and setting robust semiconductor process conditions with respect to unevenness or fluctuations in semiconductor manufacturing process conditions or unevenness in mask pattern shapes.
  • a recent lithography verification tool takes the same amount of time as an optical proximity correction (OPC) processing time even under one set of conditions, and cannot feed back an error result to a design layout in a realistic turnaround time (TAT).
  • OPC optical proximity correction
  • an integrated circuit pattern verification method which includes:
  • an integrated circuit pattern verification method which includes:
  • FIG. 1 is a view showing a flowchart of a pattern verification method according to a first embodiment
  • FIG. 2 is a view showing an example of wiring lines according to the first embodiment
  • FIG. 3 is a view illustrating extraction of wiring lines having widths which are not greater than a preset size
  • FIG. 4 is a view illustrating extraction of wiring lines having spaces which are not greater than a preset size
  • FIG. 5 is a view illustrating target edges in lithography simulation
  • FIG. 6 is a view showing a flowchart of a pattern verification method according to a second embodiment
  • FIG. 7 is a view illustrating weighting of evaluation target edges
  • FIG. 8 is a view showing a flowchart of a pattern verification method according to a fourth embodiment
  • FIGS. 9A and 9B are views illustrating a pattern verification method of MISFET
  • FIG. 10 is a view showing a flowchart of a pattern verification method according to a fifth embodiment
  • FIG. 11 is a view showing a flowchart of a pattern verification method according to a sixth embodiment.
  • FIG. 12 is a view illustrating objective ranges in edge evaluation
  • FIG. 13 is a view showing a flowchart of a pattern verification method according to a seventh embodiment
  • FIG. 14 is a view showing a flowchart of a pattern verification method according to a ninth embodiment.
  • FIG. 15 is a system chart when the pattern verification method according to the present invention is executed by using a computer.
  • FIG. 16 is a flowchart showing a manufacturing method of a semiconductor device based on mask data created by using the pattern verification method according to the present invention.
  • lithography verification of a design layout in a full chip when performing lithography verification of a design layout in a full chip, highly accurate lithography verification is effected with respect to an important pattern or a critical pattern in terms of a device, and rough lithography verification is carried out with respect to a pattern which is not very important in terms of a device and has a large allowed tolerance.
  • a TAT can be improved without decreasing a verification accuracy, and a systematic defect such as a problem in lithography or OPC can be found before manufacturing a semiconductor device, thereby avoiding a reduction in a process yield of a semiconductor device.
  • OPC optical proximity correction
  • PPC process proximity correction
  • the OPC technique is a very effective technique, and current fine processing cannot be achieved without this technique.
  • the OPC technique must be exercised within limits (design rules, a pattern layout, an edge length, an evaluation point, hierarchical processing and others), and cases where contradictory correction is required on rare occasions or correction cannot be sufficiently performed are increased with miniaturization. Such a problem will be referred to as an OPC problem hereinafter.
  • lithography rule check lithography simulation is executed with respect to a pattern after OPC, an obtained pattern is compared with a design pattern, and a deviation between these patterns is checked to detect a part which can be a problem in terms of a device. Error contents can be sorted into error types (open, short circuit, shortening and others), error level (fatal (greatly reducing a process yield)) OPC problems (which will be referred to as fatal errors hereinafter), OPC problems which are not fatal but do not have sufficient margins (which will be referred to as gray zone errors hereinafter), and others.
  • the following embodiments according to the present invention includes performing sorting based on pattern sizes or pattern types in the lithography rule check; executing highly accurate lithography simulation with respect to a pattern group sorted into patterns having widths or spaces which are not greater than a preset size or important patterns; and executing simulation with a reduced simulation accuracy or simple dimension check with respect to patterns having widths or spaces which are not smaller than a preset size or non-important patterns sorted based on a device importance level.
  • a TAT can be improved without lowering a verification accuracy, and a systematic defect such as a lithography/OPC problem can be found before manufacture of a mask and a semiconductor device, thereby avoiding a reduction in a process yield.
  • FIG. 1 is a flowchart showing a pattern verification method according to the first embodiment. Step numbers are given to steps specific to the embodiment. This is also applied to the following embodiments.
  • layout data is subjected to OPC processing to acquire OPCed data.
  • extraction of patterns having widths which are not greater than a preset size (a step 1 - 1 ) and extraction of patterns having spaces which are not greater than a preset size (a step 1 - 2 ) are executed.
  • edges of the extracted patterns are extracted (a step S 1 - 3 ).
  • verification means that lithography simulation is carried out, an obtained pattern is compared with a design pattern to check a deviation so that a part which may result in a problem in terms of a device is detected.
  • manufacture of a mask begins.
  • a retouch method is examined to carry out mask pattern correction, a design pattern correction or OPC correction.
  • the control directly advances to manufacture of a mask.
  • the control returns to OPC processing to repeat the OPC processing and the subsequent processing.
  • FIG. 2 shows an example of a wiring pattern in the OPCed data, and wiring lines 101 to 104 exist. Wiring lines having wiring widths which are not greater than a present size are extracted from these wiring lines at the step 1 - 1 , and it is assumed that the wiring lines 101 , 102 and 104 are extracted in this case ( FIG. 3 ).
  • step 1 - 2 pattern spaces which are not greater than a preset size are extracted from the OPCed data.
  • a space 105 between the wiring lines 101 and 102 and a space 107 between the wiring lines 103 and 104 are extracted as illustrated in FIG. 4 .
  • edges of the extracted wiring width and wiring spaces are extracted as indicated by solid lines in FIG. 5 .
  • the width of the wiring line 103 is not extracted, the space 107 of the same is extracted, and hence an edge portion 113 is extracted.
  • the above-described lithography simulation is executed with respect to the edges extracted in this manner.
  • lithography simulation is restricted to parts where a systematic defect such as open, short circuit or shortening is apt to occur in manufacture of a semiconductor device, thereby enabling more efficient verification in a short time.
  • FIG. 6 is a flow chart concerning a pattern evaluation method according to the second embodiment.
  • patterns having widths and spaces which are not greater than preset sizes are extracted from layout data like FIGS. 2 to 4 in the first embodiment (steps 2 - 1 , 2 - 2 ). Since pattern shapes are better than those in OPCed data, patterns can be extracted with a high level of fidelity.
  • the extracted edges are sorted into high and low accuracy simulation groups at a step 2 - 3 , edge extraction and sorting information is output at a step 2 - 4 , and the OPCed data is subjected to edge sorting based on the output data at a step 2 - 5 .
  • evaluation points of the edges with the high accuracy grade are increased, and evaluation points of the edges with the low accuracy grade are reduced.
  • the number of simulation evaluation points 122 is increased by increasing edge division points 121 of the edges with the high accuracy grade as shown in FIG. 7 .
  • the edges with the increased evaluation points are highly accurately evaluated, and the accuracy is reduced to a necessary minimum level with respect to the edges with the reduced evaluation points, thereby reducing a TAT.
  • a dense pattern can be defined as a line-and-space pattern which is not greater than a preset size or a pattern having large interconnection numbers per unit area.
  • a sparse pattern means patterns other than the dense pattern.
  • step 2 - 1 dense patterns and sparse patterns are extracted.
  • step 2 - 3 patterns sorted as the dense pattern are determined as edges subjected to evaluation with a high accuracy, and patterns sorted as the sparse pattern are determined as edges subjected to evaluation with a reduced simulation accuracy.
  • lithography simulation can be restricted to parts where a systematic defect such as open, short circuit or shortening is apt to occur in manufacture of a semiconductor device, thereby enabling more efficient verification in a short time.
  • FIG. 8 is a flowchart showing a pattern verification method according to the fourth embodiment.
  • a portion (an And portion) where a logical product of a gate wiring line (Poly) 131 and a source/drain diffusion layer (Diffusion) 132 can be taken is extracted as a Gate portion.
  • a gate wiring line (Poly) 131 and a source/drain diffusion layer (Diffusion) 132 can be taken is extracted as a Gate portion.
  • 141 in FIG. 9B is extracted as a Gate portion.
  • a gate wiring (Poly) or a metal portion contained in a region within 100 nm from a Contact/Via 133 is extracted as a Contact/Via containing portion.
  • a gate wiring (Poly) or a metal portion contained in a region within 100 nm from a Contact/Via 133 is extracted as a Contact/Via containing portion.
  • 142 in FIG. 9B is extracted as the Contact/Via containing portion.
  • a gate wiring line (Poly) untouching a Contact other than Gate portions is extracted as an End Cap portion.
  • a gate wiring line (Poly) untouching a Contact other than Gate portions is extracted as an End Cap portion.
  • 143 in FIG. 9B is extracted as the End Cap portion.
  • wiring lines (Poly/Metal) untouching the Contact/Via are extracted as dummy pattern portions.
  • 144 in FIG. 9B is extracted as the dummy pattern portion.
  • edges are sorted in accordance with pattern types. If a plurality of pattern types correspond to one edge, edges are sorted in such a manner that simulation conditions to be applied become conditions which are severe for manufacture of a semiconductor.
  • edge extraction and sorting information is output at a step 4 - 6 , and OPCed data is subjected to edge processing based on the output data at a step 4 - 7 , and simulation conditions corresponding to pattern types are applied at a step 4 - 8 .
  • lithography simulation can be restricted to parts where a systematic defect is apt to occur because of circuit characteristics of a semiconductor device, and verification can be more efficiently carried out in a short time.
  • FIG. 10 is a flowchart showing a pattern verification method according to the fifth embodiment.
  • a simulation model corresponding to respective conditions is applied in accordance with each simulation point with respect to patterns sorted based on pattern types, sizes or densities at a step 5 - 1 .
  • simulation using a highly accurate simulation model is applied to a pattern group sorted into patterns having small pattern size values, patterns which are important in terms of a device or dense patterns.
  • the simulation model is one of a vector model, a step model on an exposure mask, a step model on a processing substrate, an edge model, a resist material model and a resist process model, and the highly accurate simulation model includes more such models.
  • Simulation is separately performed by using each simulation model having a necessary minimum accuracy optimized in accordance with each pattern and edge sorted at the steps 5 - 3 , 5 - 4 and 5 - 5 , and verification is executed at a step 5 - 6 . Consequently, edges requiring a verification accuracy are evaluated by using a simulation model with a higher accuracy, and edges requiring no verification accuracy in particular are evaluated by using a simulation model with a reduced necessary minimum accuracy, thereby shortening a TAT.
  • FIG. 11 is a flowchart showing a pattern verification method according to the sixth embodiment.
  • an objective range corresponding to respective conditions is applied in accordance with each simulation point with respect to patterns sorted based on pattern types, sizes or densities.
  • simulation having an extensively set objective range is applied to a pattern group sorted into patterns with small pattern dimension values, patterns which are important in terms of a device or dense patterns.
  • an objective range 151 applied when performing simulation with an evaluation point of each of edges subjected to highly accurate evaluation is set wider than an objective range 152 applied when performing simulation concerning edges requiring no highly accurate evaluation.
  • FIG. 13 is a flowchart showing a pattern evaluation method according to the seventh embodiment.
  • error causes corresponding to respective conditions are applied to patterns sorted based on pattern types, sizes or densities at a step 7 - 1 in the drawing in accordance with each simulation point.
  • the number of error causes is increased with respect to a pattern group sorted into patterns having small pattern size values, patterns important in terms of a device or dense patterns.
  • the error cause is one of an error concerning a mask, an error concerning an illumination system, an error concerning a focusing system and an error concerning a resist, and in particular, the error concerning the illumination system is unevenness in dose amounts in manufacture and the error concerning the focusing system is unevenness in focus amounts in manufacture.
  • Simulation in which respective error causes optimized in accordance with each sorted pattern and edge are taken is separately carried out at steps 7 - 3 , 7 - 4 and 7 - 5 , and verification is executed at a step 7 - 6 .
  • simulation considering an influence of more error causes is performed with respect to an edge requiring a verification accuracy, and an influence of necessary minimum error causes alone is taken in with respect to an edge which does not require a verification accuracy in particular, thereby shortening a TAT.
  • MDP mask design processing
  • OPC optical proximity correction
  • isolated patterns separated from other patterns by 1 ⁇ m or more have the same optical influence by peripheral patterns, and hence they have the same dimension after OPC. Since such a pattern type having the same optical influence has the same OPC result, the rule-based check (DRC) can suffice even if lithography simulation is not performed.
  • DRC rule-based check
  • a cell array pattern in which the same cell patterns are aligned with the same pitch like an SRAM or a DRAM is of course included.
  • FIG. 14 is a flowchart showing a pattern verification method according to a ninth embodiment.
  • Simulation conditions steps 9 - 2 , 9 - 3 and 9 - 4
  • verification specifications steps 9 - 5 , 9 - 6 and 9 - 7
  • steps 9 - 2 , 9 - 3 and 9 - 4 are applied to patterns sorted based on pattern types, sizes or densities in accordance with each simulation point at a step 9 - 1 .
  • lithography conditions at the steps 9 - 2 , 9 - 3 and 9 - 4 may be all the same.
  • a verification specification which is rigorous in manufacture of a semiconductor is applied to a pattern group sorted into patterns having small pattern size values, patterns which are important in terms of a device or dense patterns.
  • the rigorous verification specification in manufacture of a semiconductor means that a tolerance with respect to a wafer target dimension is small or the number of verification items is large.
  • verification is carried out by using respective verification specifications optimized in accordance with each sorted pattern and edge. That is, verification is carried out with small tolerances for more verification items with respect to edges requiring a verification accuracy, and a verification specification with a necessary minimum number of large tolerances is used with respect to edges which do not require a verification accuracy in particular, thereby reducing patterns whose verification time must be decreased and which must be retouched after verification. As a result, an entire TAT including a retouch rework time after verification can be reduced.
  • the procedures described in the foregoing embodiment can be executed in such a computer system 10 as shown in FIG. 15 .
  • the computer system 10 is provided with a CPU 11 , a memory 12 , input/output portions 13 and 14 , writes the above-mentioned procedures as a program in a recording medium 15 such as a magnetic disk, an optical disk like a CD, a DVD or an MO or a semiconductor memory, and reads this program.
  • a computer system can be incorporated in various kinds of apparatuses or applied to various kinds of apparatuses by being transmitted by a communication medium.
  • mask data obtained in the first to ninth embodiments can be used to manufacture a semiconductor device. That is, as shown in a flowchart of FIG. 16 , a mask is created, a predetermined film is formed on a semiconductor wafer, and patterning is performed by lithography. After repeating this process for the necessary number of times, the semiconductor wafer is diced into a plurality of chips. Each chip is die-bonded to a predetermined package, and a terminal of the package is bonded to a wiring line (a pad) on the chip, thereby manufacturing a semiconductor device.
  • a pattern verification time can be reduced, and a regular dicing process, mount process, die-bonding process, packaging process and others can be carried out with respect to the wafer on which the thus obtained verified pattern is formed, thereby producing a semiconductor device.
  • the pattern verification method of the present invention can adopt the following conformations.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
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