US20060278951A1 - Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same - Google Patents

Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same Download PDF

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Publication number
US20060278951A1
US20060278951A1 US11/416,736 US41673606A US2006278951A1 US 20060278951 A1 US20060278951 A1 US 20060278951A1 US 41673606 A US41673606 A US 41673606A US 2006278951 A1 US2006278951 A1 US 2006278951A1
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insulating layer
region
trench isolation
field effect
effect transistor
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US11/416,736
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Myoung-Soo Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS, CO., LTD. reassignment SAMSUNG ELECTRONICS, CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, MYOUNG-SOO
Publication of US20060278951A1 publication Critical patent/US20060278951A1/en
Priority to US12/498,652 priority Critical patent/US8416599B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a Metal Oxide Semiconductor (MOS) Field Effect Transistor having a trench isolation region and a method of fabricating the same.
  • MOS Metal Oxide Semiconductor
  • a low voltage transistor for logic operated at a low voltage and an LCD driving transistor operated at a high voltage should both be embodied together on the same semiconductor substrate.
  • a high voltage transistor has a structure such as a Modified Lightly Doped Drain (MLDD) and a Field Lightly Doped Drain (FLDD), which includes a thick gate oxide layer.
  • MLDD Modified Lightly Doped Drain
  • FLDD Field Lightly Doped Drain
  • a layer used for gap fill is not a thermal oxide layer but an undoped silicate glass (USG) layer or a Chemical Vapor Deposition (CVD) oxide layer such as a High Density Plasma (HDP)-CVD oxide layer.
  • a nitride liner is typically used.
  • FIG. 1 is a sectional view of a conventional high voltage MOS Field Effect Transistor having a trench isolation region.
  • a P-type well 101 doped with a P-type impurity or an N-type well doped with an N-type impurity ion is formed on an upper surface of a semiconductor substrate 100 .
  • a trench isolation region 107 with an STI structure filled with an insulating material is then formed in a predetermined portion of the well 101 .
  • An active region 102 is defined by the trench isolation region 107 .
  • a source region and a drain region (not shown) spaced apart from each other by a prescribed distance are formed within the active region 102 Additionally, a channel region is disposed between the source and the drain regions.
  • a gate electrode 106 is formed on the channel region by interposing a gate insulating layer 105 .
  • the gate insulating layer 105 is mainly composed of thermal oxide, in which a thinning phenomenon of an oxide layer disposed on an upper edge of the trench-etched STI structure occurs.
  • the above-mentioned thinning phenomenon occurs due to the following: a compressive stress induced on a silicon substrate caused by (i) oxidation of the surface of the silicon substrate and a sidewall of the STI structure, (ii) a stress upon a gap fill layer with the STI structure, and (iii) an interruption of the migration of a oxidation reaction gas by a nitride liner formed within the STI structure when thermal oxidation is performed to form a gate oxide layer in the STI structure.
  • the above-mentioned thinning phenomenon leads to what is known as an edge crowding which in turn results in an STI structure being formed structurally with a dent around a boundary between the device isolation region (or a field region) and an adjacent active region. Furthermore, as a result of the oxide layer being thinned due the above mentioned dent, the nitride liner disposed within the STI isolation region becomes a site for trapping charges to an upper portion of the nitride liner, thereby turning on the transistor via the oxide layer. In addition, the above-mentioned thinning phenomenon and dent results in the threshold voltage of the transistor being lowered by the leakage current on the boundary portion of the trench isolation region and the active region to cause malfunctioning of the semiconductor transistor.
  • MOS Field Effect Transistor having a trench isolation region which prevents the occurrence of a leakage current on a boundary of the trench isolation region and an active region
  • MOS Field Effect Transistor includes a trench isolation region disposed in a predetermined portion of a semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other within the active region with a channel region disposed between the source region and the drain region, and a gate electrode which crosses over the channel region disposed between the source region and the drain region.
  • the MOS Field Effect Transistor further includes a gate insulating layer disposed between the gate electrode and the channel region, and an edge insulating layer thicker than the gate insulating layer which is disposed on a lower surface of the gate electrode around a boundary of the trench isolation region and the active region.
  • the edge insulating layer may comprise a plurality of layers, and an uppermost layer of the edge insulating layer and the gate insulating layer may be composed of an identical material.
  • the edge insulating layer may have a triple-layered structure of a lower oxide layer/an intermediary insulating layer/an upper oxide layer.
  • the intermediary insulating layer is composed of a material selected from a group consisting of nitride, aluminum oxide and tantalum oxide.
  • the edge insulating layer is wider than the gate electrode on the boundary of the trench isolation region and the active region, and the trench isolation region may include a nitride liner.
  • a method of fabricating a MOS Field Effect Transistor having a trench isolation region includes forming a trench isolation region in a predetermined portion of a semiconductor substrate to define an active region. After forming a first insulating layer pattern that covers at least a boundary of the trench isolation region and the active region and exposes a channel region of the transistor, a second insulating layer is formed on an at least substantially an entire surface of the semiconductor substrate where the first insulating layer pattern is formed. Then, a gate electrode is formed on at least substantially an entire surface of the semiconductor substrate where the second insulating layer and first insulating layer pattern have been formed and wherein the gate electrode crosses over the boundary of the trench isolation region and the active region.
  • a source region and a drain region spaced apart from each other within the active region may be formed. Otherwise, after forming the gate electrode, a source region and a drain region spaced apart from each other within the active region are formed using the gate electrode as an ion implantation mask.
  • an edge insulating layer underlying a gate electrode around a trench isolation region and an active region is thicker than a gate insulating layer disposed on an upper surface of a channel region. Therefore, a dent induced on a boundary of the trench isolation region and the active region is prevented to relieve an electric field that concentrates on the boundary, thereby inhibiting a leakage current. Furthermore, an edge gate insulating pattern and a central gate insulating layer are readily fabricated using deposition and etching that are generally employed in typical fabrication processes for semiconductor devices.
  • FIG. 1 is a sectional view of a MOS Field Effect transistor having a trench isolation region fabricated using a conventional technique
  • FIG. 2 is a layout of a MOS Field Effect transistor having a trench isolation region according to an exemplary embodiment of the present invention.
  • FIGS. 3 through 7 are sectional views illustrating a method of fabricating the MOS Field Effect transistor having the trench isolation region according to an exemplary embodiment of the present invention.
  • FIGS. 2 through 7 illustrate a structure of a MOS Field Effect transistor according to an exemplary embodiment of the present invention.
  • FIG. 2 is a layout thereof
  • FIG. 7 is a sectional view illustrating a high voltage (HV) region with a high voltage transistor, taken along a line A-A′ of FIG. 2 .
  • a low voltage (LV) region formed with a low voltage transistor thereon may be formed in the identical substrate.
  • a high voltage transistor for driving a Liquid Crystal Display (LCD) is formed in the HV region
  • a low voltage transistor for logic may be formed in the LV region.
  • the exemplary embodiments of the present invention is not limited to the afore-mentioned LDI structure, but may be applied to various types of semiconductor devices as long as a high voltage transistor is formed at least in the HV region.
  • a trench-shaped isolation region 202 is disposed in a predetermined portion of a semiconductor substrate 201 composed of single-crystalline silicon.
  • the trench isolation region 202 defines an active region 209 where a transistor is operated.
  • a gate electrode 208 is disposed on an upper portion of the active region 209 , and extends by crossing over the trench isolation region 202 .
  • a source region/a drain region 211 spaced apart from each other by a predetermined interval are formed within the active region 209 .
  • a channel region is disposed between the source region and the drain region 211 , and the gate electrode 208 extends over the channel region.
  • the source/drain regions 211 which are formed perpendicularly to a lengthwise direction of the gate electrode 208 form relatively low density regions, and a high density region 213 doped with an impurity ion with a density higher than that of the source/drain regions 211 is partially formed, thereby constituting a Double Diffused Drain (DDD) structure.
  • the high density region 213 is formed where source/drain contacts 214 will be formed after forming an interlayer insulating layer and then forming contact holes by a subsequent process, thereby securing an ohmic contact.
  • An edge insulating layer 207 in the form of a triple layer formed by stacking a first insulating layer 203 , a second insulating layer 204 , and a third insulating layer 205 is interposed between the gate electrode 208 and the boundary of the trench isolation region 202 and the active region 209 .
  • a gate insulating layer with the single-layered structure e.g., the third insulating layer 205 , is formed between the active region 209 and the gate electrode 208 .
  • the gate insulating layer 205 may have a thickness of about 150 to about 1000 angstroms ( ⁇ ), and the edge insulating layer 207 contacting the gate insulating layer may have a thickness of about 200 to about 10000 ⁇ .
  • the edge insulating layer 207 with the triple-layered structure prevents the formation of a dent around the boundary of the trench isolation region 202 and the active region 209 . In turn, the thinning of the insulating layer is prevented to inhibit the leakage current generated on the boundary.
  • FIG. 2 is the layout
  • FIGS. 3 through 7 are sectional views illustrating the high voltage region, taken along the line A-A′ of FIG. 2 .
  • the isolation region 202 with the Shallow Trench Isolation (STI) structure is formed on a predetermined portion of a semiconductor substrate 201 composed of, e.g., single-crystalline silicon.
  • the trench-type isolation region 202 defines the active region 209 .
  • a buffer oxide layer and an oxidation preventing layer are formed on the entire or substantially the entire surface of the semiconductor substrate 201 .
  • the buffer oxide layer may be composed of thermal oxide
  • the oxidation preventing layer may be composed of silicon nitride.
  • a photoresist pattern is formed on the oxidation preventing layer. The photoresist pattern covers an upper surface of the active region 209 , and exposes a region that will be the trench isolation region 202 .
  • the oxidation preventing layer and the buffer oxide layer are etched to form sequentially stacked a buffer oxide layer pattern and an oxidation preventing layer pattern.
  • the stacked buffer oxide layer pattern and the oxidation preventing layer pattern cover the active region 209 , and expose a portion where the isolation region 202 will be formed.
  • the trench isolation region 202 is formed.
  • the trench isolation region 202 is formed using a gap-fill insulating material such as thermal oxide, nitride liner and oxide along an inner wall of the trench.
  • an ion implantation mask such as a photoresist mask, a silicon oxide layer and a silicon nitride layer mask is formed on the entire or substantially the entire surface of the semiconductor substrate 201 using photolithography. Then, the source/drain regions 211 are formed in the active region 209 using ion implantation at a low density.
  • the source/drain regions 211 are lightly doped diffusion layers, which are formed by implanting phosphorus with a density of about 2.0 ⁇ l 2 to about 5.0E15 at an energy of about 150 KeV to about 300 KeV.
  • the light voltage region is covered with an ion implantation mask so as not to be doped with an ion.
  • the source/drain regions 211 can be formed after the gate electrode 208 shown in FIG. 7 is patterned, and then used as an ion implantation mask.
  • the first insulating layer 203 and the second insulating layer 204 are sequentially stacked on the entire or substantially the entire surface of the semiconductor substrate 201 .
  • the first insulating layer 203 is composed of, e.g., oxide.
  • the oxide layer is formed to have a thickness of about 50 to about 500 ⁇ , and preferably about 100 to about 200 ⁇ , using a chemical vapour deposition (CVD) process.
  • the second insulating layer 204 is formed.
  • the second insulating layer 204 is stacked using CVD to a thickness of about 50 to about 500 ⁇ , and preferably about 100 to about 200 ⁇ .
  • the second insulating layer 204 may be composed of diverse kinds of insulating materials, e.g., a nitride group such as silicon nitride, or a metal oxide group such as alumina or tantalum.
  • the first insulating layer 203 and the second insulating layer 204 are removed using photolithography, thereby exposing the semiconductor substrate 201 of the active region 209 including the channel region disposed between the source/drain regions 211 .
  • the first insulating layer 203 and the second insulating layer 204 are left on the boundary of the trench isolation region 202 and the active region 209 .
  • the first insulating layer 202 and the third insulating layer 204 in the source/drain regions 211 direction are wider than the gate electrode 208 on the boundary of the trench isolation region 202 and the active region 209 .
  • the third insulating layer 205 is stacked on the entire or substantially the entire surface of the resultant structure.
  • the third insulating layer 205 may be composed of, e.g., oxide.
  • the oxide layer is stacked to a thickness of about 200 to about 2000 ⁇ , and preferably about 500 to about 700 ⁇ , using CVD.
  • the third insulating layer 205 acts as a single-layered gate insulating layer on the lower surface of the gate electrode 208 , and partially constitutes the edge insulating layer 207 together with the first insulating layer 202 and the second insulating layer 203 on the boundary of the trench isolation region 202 and the active region 209 .
  • the triple-layered structure comprising the oxide layer/the nitride layer/the oxide layer of the edge insulating layer 207 is equivalent to a structure of a layer acting as a dielectric film formed between upper and lower conductive material layers formed when forming a capacitor of a semiconductor device. Accordingly, when fabricating a semiconductor transistor that requires a capacitor, the dielectric film can be formed by the forming of the edge insulating layer without separately performing a process of forming a field transistor. Generally, a high voltage transistor and a capacitor are used together in chips for driving LCD panels, and the dielectric film with the foregoing triple structure of oxide/nitride/oxide applied to the capacitor is available in terms of simplifying the fabricating process. Such a capacitor may be formed on both the high voltage region and the low voltage region.
  • the edge insulating layer 207 has the triple-layered structure of the first insulating layer 203 , the second insulating layer 204 , the third insulating layer 205 in this exemplary embodiment.
  • the edge insulating layer 207 may alternatively have a double-layered structure by taking into consideration the etch selectivity between the insulating layers. For example, an oxide layer/an oxide layer structure may be applied.
  • the triple-layered structure of the first insulating layer 203 , the second insulating layer 204 , and the third insulating layer 205 may be etched and patterned in accordance with a particular design.
  • the triple-layered structure may be patterned before or after forming the gate electrode.
  • the triple-layered structure may be patterned before forming the gate electrode 208 .
  • the gate electrode 208 is formed. Furthermore, the third insulating layer 205 is etched or remains unchanged to form the gate insulating layer relatively thin in the light voltage region formed on a periphery of the semiconductor substrate 201 .
  • the source/drain regions 211 may be formed after forming the gate electrode 208 , using the gate electrode 208 as an ion implantation mask as described above.
  • the triple layer on the source/drain regions 211 within the high voltage transistor region is partially etched, and a high density impurity ion is doped to a portion on the source/drain regions 211 from which the triple-layered insulating layer is removed to form the high density region 213 .
  • Source/drain contacts 214 are formed in the high density region 213 by a subsequent process, so that the high density region 213 is doped with the impurity ion with a density relatively higher than the density of the source/drain regions 211 .
  • the gate electrode 208 may be composed of, e.g., polysilicon.
  • a gate electrode for a low voltage transistor may be simultaneously formed in the low voltage region.
  • a thick interlayer insulating layer composed of, e.g., oxide, is formed on the entire or substantially the entire surface of the semiconductor substrate 201 .
  • contact holes for source/drain contacts are formed, and filled with a conductive material to form the source/drain contacts 214 .
  • a thick edge insulating layer is formed on a boundary of a trench isolation region and an active region to prevent dents and thinning of an oxide layer on the boundary portion. Therefore, a leakage current generated due to concentration of an electric field on the boundary portion is prevented.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
US11/416,736 2005-06-09 2006-05-03 Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same Abandoned US20060278951A1 (en)

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KR20060130917A (ko) 2006-12-20
CN1877858B (zh) 2010-09-29
US8416599B2 (en) 2013-04-09

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