US20050195629A1 - Interchangeable connection arrays for double-sided memory module placement - Google Patents

Interchangeable connection arrays for double-sided memory module placement Download PDF

Info

Publication number
US20050195629A1
US20050195629A1 US10/792,350 US79235004A US2005195629A1 US 20050195629 A1 US20050195629 A1 US 20050195629A1 US 79235004 A US79235004 A US 79235004A US 2005195629 A1 US2005195629 A1 US 2005195629A1
Authority
US
United States
Prior art keywords
memory
columns
connections
signals
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/792,350
Other languages
English (en)
Inventor
Michael Leddige
Kuljit Bains
John Sprietsma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tahoe Research Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/792,350 priority Critical patent/US20050195629A1/en
Application filed by Individual filed Critical Individual
Assigned to INTEL CORPORATION (A DELAWARE CORPORATION) reassignment INTEL CORPORATION (A DELAWARE CORPORATION) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAINS, KULJIT, SPRIETSMA, JOHN T., LEDDIGE, MICHAEL W.
Priority to AT05713488T priority patent/ATE472801T1/de
Priority to EP05713488A priority patent/EP1723654B1/en
Priority to DE602005022053T priority patent/DE602005022053D1/de
Priority to CN2005800066525A priority patent/CN1926632B/zh
Priority to JP2007500868A priority patent/JP2007525769A/ja
Priority to PCT/US2005/004595 priority patent/WO2005093757A1/en
Priority to TW094104530A priority patent/TWI295063B/zh
Publication of US20050195629A1 publication Critical patent/US20050195629A1/en
Priority to US11/899,497 priority patent/US8099687B2/en
Priority to US13/339,525 priority patent/US8438515B2/en
Priority to US13/888,627 priority patent/US8775991B2/en
Assigned to TAHOE RESEARCH, LTD. reassignment TAHOE RESEARCH, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
US10/792,350 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement Abandoned US20050195629A1 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
US10/792,350 US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement
AT05713488T ATE472801T1 (de) 2004-03-02 2005-02-14 Austauschbare verbindungs-arrays für doppelseitige dimm-plazierung
EP05713488A EP1723654B1 (en) 2004-03-02 2005-02-14 Interchangeable connection arrays for double-sided dimm placement
DE602005022053T DE602005022053D1 (de) 2004-03-02 2005-02-14 Austauschbare verbindungs-arrays für doppelseitige dimm-plazierung
CN2005800066525A CN1926632B (zh) 2004-03-02 2005-02-14 用于双面dimm放置的可互换连接阵列
JP2007500868A JP2007525769A (ja) 2004-03-02 2005-02-14 両面ｄｉｍｍ配置用の交換可能接続アレイ
PCT/US2005/004595 WO2005093757A1 (en) 2004-03-02 2005-02-14 Interchangeable connection arrays for double-sided dimm placement
TW094104530A TWI295063B (en) 2004-03-02 2005-02-16 Interchangeable connection arrays for double-sided dimm placement
US11/899,497 US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13/339,525 US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13/888,627 US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/792,350 US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/899,497 Continuation US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement

Publications (1)

Publication Number Publication Date
US20050195629A1 true US20050195629A1 (en) 2005-09-08

Family

ID=34911834

Family Applications (4)

Application Number Title Priority Date Filing Date
US10/792,350 Abandoned US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement
US11/899,497 Expired - Fee Related US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13/339,525 Expired - Lifetime US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13/888,627 Expired - Lifetime US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Family Applications After (3)

Application Number Title Priority Date Filing Date
US11/899,497 Expired - Fee Related US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13/339,525 Expired - Lifetime US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13/888,627 Expired - Lifetime US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Country Status (8)

Country Link
US (4) US20050195629A1 (zh)
EP (1) EP1723654B1 (zh)
JP (1) JP2007525769A (zh)
CN (1) CN1926632B (zh)
AT (1) ATE472801T1 (zh)
DE (1) DE602005022053D1 (zh)
TW (1) TWI295063B (zh)
WO (1) WO2005093757A1 (zh)

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060170097A1 (en) * 2005-02-02 2006-08-03 Moon-Jung Kim Printed wires arrangement for in-line memory (IMM) module
US20080037353A1 (en) * 2006-07-31 2008-02-14 Metaram, Inc. Interface circuit system and method for performing power saving operations during a command-related latency
US20080062734A1 (en) * 2004-03-02 2008-03-13 Leddige Michael W Interchangeable connection arrays for double-sided DIMM placement
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
EP2419971A1 (en) * 2009-04-17 2012-02-22 Hewlett-Packard Company Method and system for reducing trace length and capacitance in a large memory footprint background
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US20130314968A1 (en) * 2011-02-09 2013-11-28 Ian Shaeffer Offsetting clock package pins in a clamshell topology to improve signal integrity
US20140159237A1 (en) * 2012-12-10 2014-06-12 Heung-Kyu Kwon Semiconductor package and method for routing the package
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20180027682A1 (en) * 2016-07-22 2018-01-25 Intel Corporation Thermally Efficient Compute Resource Apparatuses and Methods
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US20180324951A1 (en) * 2015-11-13 2018-11-08 Intel Corporation Electronic assembly that includes a substrate bridge
US10217721B2 (en) * 2017-05-05 2019-02-26 Apple Inc. Dual-sided memory module with channels aligned in opposition

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006005955B4 (de) * 2005-02-02 2007-01-25 Samsung Electronics Co., Ltd., Suwon Inline-Speichermodul
US8856434B2 (en) 2008-09-26 2014-10-07 Cypress Semiconductor Corporation Memory system and method
US8095747B2 (en) * 2008-09-26 2012-01-10 Cypress Semiconductor Corporation Memory system and method
CN101727970B (zh) * 2009-11-03 2012-11-21 深圳市共进电子股份有限公司 一种减小sdram产生辐射的方法
CN102289400B (zh) * 2011-09-05 2013-07-31 浪潮电子信息产业股份有限公司 一种提高dimm测试效率的方法
CN102508749B (zh) * 2011-10-19 2013-08-14 浪潮集团有限公司 一种实现dimm测试的方法
TW201347051A (zh) 2012-01-27 2013-11-16 Mosaid Technologies Inc 連接記憶體晶粒形成記憶體系統的方法與設備
US9786354B2 (en) * 2013-07-10 2017-10-10 Samsung Electronics Co., Ltd. Memory module
US9934143B2 (en) 2013-09-26 2018-04-03 Intel Corporation Mapping a physical address differently to different memory devices in a group
JP6067541B2 (ja) * 2013-11-08 2017-01-25 株式会社東芝 メモリシステムおよびメモリシステムのアセンブリ方法
US9265152B2 (en) 2013-12-17 2016-02-16 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Dual side staggered surface mount dual in-line memory module
WO2017018991A1 (en) * 2015-07-24 2017-02-02 Hewlett Packard Enterprise Development Lp Modification of a bus channel
CN107180000B (zh) * 2016-03-10 2020-04-14 华为技术有限公司 存储装置及数据访问方法
US10199084B2 (en) * 2016-03-28 2019-02-05 Intel Corporation Techniques to use chip select signals for a dual in-line memory module
US9818457B1 (en) 2016-09-30 2017-11-14 Intel Corporation Extended platform with additional memory module slots per CPU socket
US10216657B2 (en) 2016-09-30 2019-02-26 Intel Corporation Extended platform with additional memory module slots per CPU socket and configured for increased performance
KR102596491B1 (ko) 2016-12-13 2023-10-30 삼성전자주식회사 반도체 장치
JP6847797B2 (ja) * 2017-09-21 2021-03-24 キオクシア株式会社 半導体記憶装置
TWM564884U (zh) * 2018-03-28 2018-08-01 緯創資通股份有限公司 主機板及電腦裝置
EP3547363B1 (en) * 2018-03-29 2022-12-21 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic assembly and electronic system with impedance matched interconnect structures
US10410950B1 (en) * 2018-05-11 2019-09-10 Micron Technology, Inc. Heat spreaders for use with semiconductor devices
US20190157253A1 (en) * 2019-01-22 2019-05-23 Intel Corporation Circuit Systems Having Memory Modules With Reverse Orientations
CN113490926A (zh) 2019-02-28 2021-10-08 拉姆伯斯公司 四通道dram
JP6833086B2 (ja) * 2020-02-26 2021-02-24 キオクシア株式会社 システム

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307769B1 (en) * 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
US20040230932A1 (en) * 2002-09-27 2004-11-18 Rory Dickmann Method for controlling semiconductor chips and control apparatus
US20050007807A1 (en) * 2002-10-17 2005-01-13 Martin Chris G. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
US20050030815A1 (en) * 2002-05-21 2005-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US20050036350A1 (en) * 2003-08-13 2005-02-17 So Byung-Se Memory module
US20060171247A1 (en) * 2005-02-03 2006-08-03 Wolfgang Hoppe Semiconductor memory module with bus architecture
US20060233037A1 (en) * 2003-09-19 2006-10-19 Rory Dickman Method and apparatus for operating electronic semiconductor chips via signal lines

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208782A (en) * 1989-02-09 1993-05-04 Hitachi, Ltd. Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement
EP0473796A4 (en) * 1990-03-15 1994-05-25 Fujitsu Ltd Semiconductor device having a plurality of chips
JPH07135301A (ja) * 1993-09-16 1995-05-23 Mitsubishi Electric Corp 半導体記憶装置
JPH07288282A (ja) * 1994-04-18 1995-10-31 Hitachi Ltd 半導体装置
JP3718008B2 (ja) * 1996-02-26 2005-11-16 株式会社日立製作所 メモリモジュールおよびその製造方法
JP3904296B2 (ja) * 1996-11-12 2007-04-11 新潟精密株式会社 メモリシステム
US6202110B1 (en) * 1997-03-31 2001-03-13 International Business Machines Corporation Memory cards with symmetrical pinout for back-to-back mounting in computer system
JP2000340737A (ja) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体パッケージとその実装体
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6574724B1 (en) * 2000-02-18 2003-06-03 Texas Instruments Incorporated Microprocessor with non-aligned scaled and unscaled addressing
US6449166B1 (en) * 2000-08-24 2002-09-10 High Connection Density, Inc. High capacity memory module with higher density and improved manufacturability
KR100454123B1 (ko) * 2001-12-06 2004-10-26 삼성전자주식회사 반도체 집적 회로 장치 및 그것을 구비한 모듈
US6875930B2 (en) * 2002-04-18 2005-04-05 Hewlett-Packard Development Company, L.P. Optimized conductor routing for multiple components on a printed circuit board
JP4242117B2 (ja) * 2002-07-11 2009-03-18 株式会社ルネサステクノロジ 記憶装置
JP2004055009A (ja) * 2002-07-18 2004-02-19 Renesas Technology Corp 半導体メモリモジュール
DE10238812B4 (de) * 2002-08-23 2005-05-25 Infineon Technologies Ag Halbleiterspeichervorrichtung mit veränderbarer Kontaktbelegung und entsprechende Halbleitervorrichtung
DE10258199B4 (de) * 2002-12-12 2005-03-10 Infineon Technologies Ag Schaltungsanordnung mit einer Anzahl von integrierten Schaltungsbauelementen auf einem Trägersubstrat und Verfahren zum Test einer derartigen Schaltungsanordnung
US7183643B2 (en) * 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US20050195629A1 (en) 2004-03-02 2005-09-08 Leddige Michael W. Interchangeable connection arrays for double-sided memory module placement
US7260691B2 (en) * 2004-06-30 2007-08-21 Intel Corporation Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins
US7417883B2 (en) * 2004-12-30 2008-08-26 Intel Corporation I/O data interconnect reuse as repeater
US7359279B2 (en) * 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
JP4321543B2 (ja) 2006-04-12 2009-08-26 トヨタ自動車株式会社 車両周辺監視装置
DE102006051514B4 (de) * 2006-10-31 2010-01-21 Qimonda Ag Speichermodul und Verfahren zum Betreiben eines Speichermoduls
US8689508B2 (en) * 2008-05-28 2014-04-08 Steeltec Supply, Inc. Extra strength backing stud having notched flanges
JP2009293938A (ja) 2008-06-02 2009-12-17 Denso Corp 転回検出装置、プログラム、および車両方位検出装置
JP2011031779A (ja) 2009-08-03 2011-02-17 Kanto Auto Works Ltd クリップ

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307769B1 (en) * 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
US20050030815A1 (en) * 2002-05-21 2005-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US20040230932A1 (en) * 2002-09-27 2004-11-18 Rory Dickmann Method for controlling semiconductor chips and control apparatus
US20050007807A1 (en) * 2002-10-17 2005-01-13 Martin Chris G. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
US20050036350A1 (en) * 2003-08-13 2005-02-17 So Byung-Se Memory module
US20060233037A1 (en) * 2003-09-19 2006-10-19 Rory Dickman Method and apparatus for operating electronic semiconductor chips via signal lines
US20060171247A1 (en) * 2005-02-03 2006-08-03 Wolfgang Hoppe Semiconductor memory module with bus architecture

Cited By (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8775991B2 (en) 2004-03-02 2014-07-08 Intel Corporation Interchangeable connection arrays for double-sided DIMM placement
US20080062734A1 (en) * 2004-03-02 2008-03-13 Leddige Michael W Interchangeable connection arrays for double-sided DIMM placement
US8099687B2 (en) * 2004-03-02 2012-01-17 Intel Corporation Interchangeable connection arrays for double-sided DIMM placement
US20060170097A1 (en) * 2005-02-02 2006-08-03 Moon-Jung Kim Printed wires arrangement for in-line memory (IMM) module
US7394160B2 (en) * 2005-02-02 2008-07-01 Samsung Electronics Co., Ltd. Printed wires arrangement for in-line memory (IMM) module
US8615679B2 (en) 2005-06-24 2013-12-24 Google Inc. Memory modules with reliability and serviceability functions
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8386833B2 (en) 2005-06-24 2013-02-26 Google Inc. Memory systems and memory modules
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US8811065B2 (en) 2005-09-02 2014-08-19 Google Inc. Performing error detection on DRAMs
US8797779B2 (en) 2006-02-09 2014-08-05 Google Inc. Memory module with memory stack and interface with enhanced capabilites
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8566556B2 (en) 2006-02-09 2013-10-22 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8340953B2 (en) 2006-07-31 2012-12-25 Google, Inc. Memory circuit simulation with power saving capabilities
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8745321B2 (en) 2006-07-31 2014-06-03 Google Inc. Simulating a memory standard
US8671244B2 (en) 2006-07-31 2014-03-11 Google Inc. Simulating a memory standard
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8112266B2 (en) 2006-07-31 2012-02-07 Google Inc. Apparatus for simulating an aspect of a memory circuit
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8631220B2 (en) 2006-07-31 2014-01-14 Google Inc. Adjusting the timing of signals associated with a memory system
US8595419B2 (en) 2006-07-31 2013-11-26 Google Inc. Memory apparatus operable to perform a power-saving operation
US20080037353A1 (en) * 2006-07-31 2008-02-14 Metaram, Inc. Interface circuit system and method for performing power saving operations during a command-related latency
US8601204B2 (en) 2006-07-31 2013-12-03 Google Inc. Simulating a refresh operation latency
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US8370566B2 (en) 2006-10-05 2013-02-05 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8751732B2 (en) 2006-10-05 2014-06-10 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8760936B1 (en) 2006-11-13 2014-06-24 Google Inc. Multi-rank partial width memory modules
US8446781B1 (en) 2006-11-13 2013-05-21 Google Inc. Multi-rank partial width memory modules
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8675429B1 (en) 2007-11-16 2014-03-18 Google Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8730670B1 (en) 2007-12-18 2014-05-20 Google Inc. Embossed heat spreader
US8705240B1 (en) 2007-12-18 2014-04-22 Google Inc. Embossed heat spreader
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8631193B2 (en) 2008-02-21 2014-01-14 Google Inc. Emulation of abstracted DIMMS using abstracted DRAMS
US8762675B2 (en) 2008-06-23 2014-06-24 Google Inc. Memory system for synchronous data transmission
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8819356B2 (en) 2008-07-25 2014-08-26 Google Inc. Configurable multirank memory system with interface circuit
US8866023B2 (en) * 2009-04-17 2014-10-21 Hewlett-Packard Development Company, L.P. Method and system for reducing trace length and capacitance in a large memory footprint
EP2419971A1 (en) * 2009-04-17 2012-02-22 Hewlett-Packard Company Method and system for reducing trace length and capacitance in a large memory footprint background
EP2419971A4 (en) * 2009-04-17 2013-03-27 Hewlett Packard Co METHOD AND SYSTEM FOR REDUCING LENGTH AND TRACE CAPACITY IN IMPORTANT MEMORY FOOTPRINT
US20120175160A1 (en) * 2009-04-17 2012-07-12 Kadri Rachid M Method and system for reducing trace length and capacitance in a large memory footprint
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US20130314968A1 (en) * 2011-02-09 2013-11-28 Ian Shaeffer Offsetting clock package pins in a clamshell topology to improve signal integrity
US9336834B2 (en) * 2011-02-09 2016-05-10 Rambus Inc. Offsetting clock package pins in a clamshell topology to improve signal integrity
US20140159237A1 (en) * 2012-12-10 2014-06-12 Heung-Kyu Kwon Semiconductor package and method for routing the package
US10056321B2 (en) * 2012-12-10 2018-08-21 Samsung Electronics Co., Ltd. Semiconductor package and method for routing the package
US20180324951A1 (en) * 2015-11-13 2018-11-08 Intel Corporation Electronic assembly that includes a substrate bridge
US10492299B2 (en) * 2015-11-13 2019-11-26 Intel Corporation Electronic assembly that includes a substrate bridge
US20180027682A1 (en) * 2016-07-22 2018-01-25 Intel Corporation Thermally Efficient Compute Resource Apparatuses and Methods
US10674238B2 (en) * 2016-07-22 2020-06-02 Intel Corporation Thermally efficient compute resource apparatuses and methods
US10217721B2 (en) * 2017-05-05 2019-02-26 Apple Inc. Dual-sided memory module with channels aligned in opposition
CN110582809A (zh) * 2017-05-05 2019-12-17 苹果公司 具有相对对准的通道的双侧面存储器模块
US10804243B2 (en) 2017-05-05 2020-10-13 Apple Inc. Dual-sided memory module with channels aligned in opposition

Also Published As

Publication number Publication date
EP1723654B1 (en) 2010-06-30
JP2007525769A (ja) 2007-09-06
US20120199973A1 (en) 2012-08-09
US20130341790A1 (en) 2013-12-26
ATE472801T1 (de) 2010-07-15
US8775991B2 (en) 2014-07-08
US8099687B2 (en) 2012-01-17
US20080062734A1 (en) 2008-03-13
DE602005022053D1 (de) 2010-08-12
CN1926632A (zh) 2007-03-07
WO2005093757A1 (en) 2005-10-06
US8438515B2 (en) 2013-05-07
CN1926632B (zh) 2011-08-03
TW200540876A (en) 2005-12-16
TWI295063B (en) 2008-03-21
EP1723654A1 (en) 2006-11-22

Similar Documents

Publication Publication Date Title
US8099687B2 (en) Interchangeable connection arrays for double-sided DIMM placement
JP5473317B2 (ja) メモリモジュールおよびそのレイアウト方法
JP4707446B2 (ja) 半導体装置
US20130138898A1 (en) Memory module including plural memory devices and command address register buffer
US9076500B2 (en) Memory module including plural memory devices and data register buffer
US8344518B2 (en) Apparatus for stacking integrated circuits
KR20080076010A (ko) 반도체 메모리 장치와 이 장치의 단자 배치 방법, 및 이장치를 구비한 메모리 모듈과 이 모듈의 기판의 단자 및라인 배치 방법
KR101245380B1 (ko) 메모리 모듈
US10217721B2 (en) Dual-sided memory module with channels aligned in opposition
US20110058401A1 (en) Semiconductor memory device having pad electrodes arranged in plural rows
US8908450B1 (en) Double capacity computer memory device
US8183676B2 (en) Memory circuit having memory chips parallel connected to ports and corresponding production method
US20070189049A1 (en) Semiconductor memory module
CN113886313B (zh) 存储器子系统寄存器时钟驱动器时钟t型配线
US9226398B1 (en) Printed circuit board and package substrate having additional conductive pathway space
US9426916B1 (en) Arrangement of memory devices in a multi-rank memory module
US20030067082A1 (en) Apparatus and methods for stacking integrated circuit devices with interconnected stacking structure
KR20130130597A (ko) 신호 무결성이 개선된 반도체 장치
JP2014078281A (ja) メモリモジュールおよびそのレイアウト方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION (A DELAWARE CORPORATION), CALIFO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEDDIGE, MICHAEL W.;BAINS, KULJIT;SPRIETSMA, JOHN T.;REEL/FRAME:015084/0142;SIGNING DATES FROM 20040301 TO 20040302

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: TAHOE RESEARCH, LTD., IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061175/0176

Effective date: 20220718