TWI295063B - Interchangeable connection arrays for double-sided dimm placement - Google Patents
Interchangeable connection arrays for double-sided dimm placement Download PDFInfo
- Publication number
- TWI295063B TWI295063B TW094104530A TW94104530A TWI295063B TW I295063 B TWI295063 B TW I295063B TW 094104530 A TW094104530 A TW 094104530A TW 94104530 A TW94104530 A TW 94104530A TW I295063 B TWI295063 B TW I295063B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- interchangeable
- connection
- signals
- module
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Description
1295063 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於一種用於雙側雙面貼裝記憶模組( DIMM)設置的可互換連接陣歹[J。 【先前技術】 目前,諸如雙面貼裝記憶模組(DIMM )等的記憶封 裝可駐在印刷電路板(PCB )或其他基底兩側上。此增加 系統的記憶密度。記憶信號可路由整個基底好幾年。藉由 基底兩側上的記憶封裝,信號路由及完整性成爲一大問題 〇 路由整個基底的信號可連接到封裝相對側上之DIMM 的球或連接。例如,到基底一側上的封裝最近側之信號一 般將結束必須到基底另一側上的封裝最遠側。使封裝另一 側的DIMM”顛倒”以裝設在另一側上,自信號開始使枏關 連接可在封裝另一側上。 【發明內容】及【實施方式】 圖1爲裝設在基底上的雙側雙面貼裝記憶模組( DIMM )之習知實施例。雙側意指記憶模組裝設在基底的 相對側上。基底10可以是在其上裝設有DIMMs之多層 PCB或任何其他基底。記憶模組1 2a及1 2b彼此裝設在基 底的相對側上,如同記憶模組1 4 a及M b —般。基底1〇 具有內部的路由信號軌跡1 6a及1 6b。通過通孔1 3的導體 -5- 12950(¾牛 2A :第 94104530 ., 中文說明書替換頁 號專利申請案 yt>. ιζ. 〇 1年月日修正替換頁 民國年III·月3 1日修正- 棒1 8使焊球或其他連接可自模組1 2a連接到第一信號軌 跡 1 6 a。 在大於信號軌跡的間距上製造通孔1 3以提供額外寬 度,及使用幾個通孔可限制可路由整個單層基底1 〇之軌 跡數目。此增加額外層數和成本。此外,爲了避免短路信 號進入基底10的內部電源和地面層,典型上在電源平面 層使用反墊片,此影響電源運送到模組內的記憶體。 雙倍資料率記憶體(DDR )使用時脈信號的上升和下 降邊緣以操作記憶體,結果記憶體速度是使用時脈信號的 前緣或下降緣的兩倍。DDR3是DDR的第三版。在DDR3 中,和其他記憶體類型一樣,命令/位址匯流排是菊輪式 鏈接或”定點飛行’’式匯流排。此匯流排類型由於雙側記憶 體裝設導致的不相等路由長度所以有信號完整性的問題。 如圖1所示,信號16a具有在連接20和26之間的第 一路由長度。第二路由長度在模組12b上的連接26和模 組14a上的球30之間第二路由長度遠短於第一路由長度 。由於第一路由長度自連接22到連接24,及第二路由長 度自模組12a上的連接24到模組14b上的連接32,所以 類似的長度差異出現在信號16b。必須注意的是,連接20 ,22,24,26,30,32,34,及36在此文中被圖示成焊球 ,但是用於設置積體電路晶錠和基底之間的連接可以是任 何連接類型。 路由長度的差異導致不統一的有效通道阻抗。此限制 裝置接收可識別信號的能力。典型上,系統被設計成具有 -6- (3) (3)1295063 非常規律且相等間隔的負載並且線路被調整成符合負載。 若沒有阻抗相配,則信號完整性變得有問題及無法支援較 高的資料率。 在一方法中,習知技術建議在晶銳本身的半導體中執 行路由。使用在晶錠中的邏輯”鏡射’’信號,連接重新被定 義成不同信號。資料路徑中需要的邏輯在路徑中導入潛在 因素,與到裝置製造中的耗用時間。 可以互換在記憶模組中的各種連接之實體連接,避免 資料路徑中的邏輯導入,同時提供與鏡射相同的優點。例 子圖示在圖2中。 此實施例中的路由長度已經統一。雖然此處所使用的 統一性可當作一例子,但是此處所用的”統一 ”一詞並不意 味它們完全相同,統一性意味著在負載之間信號路徑中的 阻抗彼此相當符合。現在路由長度1是自連接2 0到連接 30的長度,路由長度2是自連接30到下一裝置上的同一 信號(未圖示)之連接的長度。負載現在的間隔更統一, 使裝置可以良好的信號完整性支援更高的資料率。 此外’圖2所示的配置之通孔數目已減少。自底側記 憶模組1 2b及1 4b的遠側之資料互換已移到近側,使信號 可共用通孔。通孔數目的減少緩和軌跡間隔上的限制,使 使更多軌跡可位在指定層。依次,此可減少基底中需要的 層數,減少成本,與減輕電源和地面的短路。 爲了可實施此方法,必須有一些能夠在模組兩側之間 互換的信號。爲了更容易瞭解可互換信號的定義,討論在 (4) (4)1295063 基底上如何設計記憶模組是有幫助的。如圖3所示’記憶 控制器3 8具有64位元組的資料輸入。在基底1 0上的每 一模組4Oa-40h是X8模組;每一個都可接收8位元組記 憶。 必須注意的是在本發明的一實施例中,可互換的信號 可被選擇成可最佳化不同封裝類型的足印。例如記憶模組 4〇a所示,將資料線配置成封裝是X4/X8封裝,資料線不 是X4專用的DOO-3,就是X8封裝專用的DQ0-7。若封裝 是X16封裝,則存在所有資料線及DQ0-15可用於可互換 性。再者,儘管資料線在諸如DQ[0:7]及DQ[8:15]等位元 組嚷道’內可互換,但是若可互換性被侷限於諸如DQ[〇:3] ,DQ[4:7],DQ[8:1 1],及 D Q [ 1 2 : 1 5 ]等半位元組內,則可 增加可互換信號適用於不同的封裝類型。 可互換性實際上發生在控制器38。DRAM及DIMM” 不知道”什麼在資料上,不知道那資料事賨上是DQ 1或 DQ15專用的。因此,這些信號可互換。其他信號類型已 被識別當作可互換的,下面將更進一步討論。必須注意的 是,儘管控制器之外的資料是6 4位元組,但是也有位址 和以排爲主的信號以菊輪式鏈接或$點飛行’方式自控制 器發送。信號沿著匯流排通過及距離爲相關連接道路由長 度想要統一的此匯流排之間的距離。如圖2所示的自連接 傳輸之信號的互換提供此統一性。 在大部分的記憶體設計中,可互換性是可以的。例如 ,圖4的記憶系統利用雙側記憶基底。除了面向觀看者一 -8- (5) (5)1295063 側上的模組40a-4Oh以外,諸如42a等模組位在遠離觀看 者的一側上。被配置在此種系統中的記憶模組通常使甩諸 如晶片選擇(C S )等以排爲主的信號定址。在此特定實施 例中,兩不同排專用的位址和以排爲主的信號被圖示成在 控制器外。通常,以排爲主的信號不可互換。 同樣地,可使用諸如圖示在圖5a及5b者等,層’記 憶模組執行可互換性。圖5a圖示兩記憶晶錠44a及44b 之間的連接是內部的及它們使用諸如球46等共同連接陣 列之疊層記憶體配置的例子。在圖5b中,每一模組44 a 及44b具有它們自己外部的連接陣列,諸如焊球46a及 4 6b等。可互換性也可利用在此配置中。 模組通常被配置成列和行的連接陣列。如同討論關於 圖6-8 —般,連接配置將被假設成在至少四行,雖然三行 也可以。此假設依據典型1 5或16列連接乘以9行的 DRAM設計。通常,在中間3行沒有連接,在模組钓每一’ 側1留有3行。 在可互換信號的討論中,可使用幾種不同信號縮寫。 在下表中是這些縮寫,包括說明。 -9- (6)1295063 縮寫 信號名稱 註解 vss 核心接地 在基底中通常連接 在一起 VSSQ I/O接地 VDD 核心電源 在基底中通常連接 在一起 VDDQ I/O電源 RFU 儲存作未來使用 CLK/CLK# dRam輸入時脈 DQ[〇:15] 資料信號 低和高位元組( 0:7 ^ 8:15) DQS/DQS# 到dram內的資料時脈 專用選通脈衝 低和高位元組之用 DM 資料遮罩信號 低和高位元組之用 VREFDQ 資料用電壓參考接腳 CS 晶片選擇 CKE 時脈致能 ODT 晶鏡上終端 — RAS 列位址選擇 CAS 行位址選擇 WE 寫入致能 RST 重設 ZQ 阻抗校準接腳 sCS 疊層晶片選擇 sCKE 疊層時脈致能 sODT 疊層晶銳上終端 sZQ 疊層阻抗校準接腳 A[0: 1 5] 位址 B A [ 0 : 3 ] 堆積位址 VREFCA 命令/位址專用電壓參考 ----- -10- 12950驗牛 2A :第 94104530 • ^ 中;έ說明書替換頁 號專利申請案 民圓 96.12. 31年月日修正替換頁 |〇_6部12月31曰修正 通常,可互換信號將包括諸如DQ[0:7]及DQ[8:15]等 位元組’線道’內的D Q信號。堆積位址和B A [ 0 : 1 ]可互換。 在諸如A [ 3 : 9 ]等一列內的位址連接可互換。雖然在此例中 未圖示,但是,通常VDD和VSS連接位置可循環遞移動 以共用通孔。 圖6爲考慮到可互換信號的記憶模組設計之一般實施 例。如所示,例子爲1 6 X 9陣列的連接。陣列已被配置在 九行中,每一側上的外面兩行51,52,5 8,及59被識別作 可互換信號使用及中間兩行53及57被識別作不可互換信 號使用。每一側上的外面兩行是可互換的,提供四個可互 換行,或只有每一側上的外面一行只提供兩可互換行。 圖7圖示更特別的1 6 X 9連接設計實施例。在此例中 ,VDDQ及VSSQ具有對共用前面到後面的通孔之位置。 另外,A3及A4、A5及A6、和A7及A8可共用在DIMM 位準的通孔。此特別設計另外具有DIMM每一列只有4信 號的優點,使信號軌跡有更好的軌跡間隔,另外增加信號 完整性。在行5 2的儲存作未來使用(RF.U )連接,列J及 L可被用於sODT,及sCS。同樣地,在行58的RFU,列 J可被用於sCKE,及列D用於sZQ。 利用修正這些規則可以獲得1 5 X 9連接設計。若對地 面圖型可達成2 ·· 1定量供應信號,及去掉2連接,則可以 利用可互換連接達成1 5 X 9連接設計。此實施例圖示在圖 8。在此實施例中,已去掉0DT信號,堆積位址3 ( BA3 )及位址1 5 ( A1 5 )共用連接。在行5 2的RFU連接,列 -11 - (8) (8)1295063 L變成ΒΑ0。 利用這些可能設計,對圖1及2是有幫助的。臆測連 接20及22對應於連接陣列之行1的位置,及連接24及 2 6對應於行9的位置。在圖1中,此導致不均等的路由長 度和額外通孔。若控制器將互換行1及9之間的信號’則 移動已事先使用連接22的信號到行9和已事先使用連接 2 6的信號到行1 ’結果如圖2所示。連接2 2及2 ό維持在 相同位置,已路由到那些行的信號被互換’使得連接20 及22,和24及26可連接在一起。連接陣列的外面行之間 的可互換信號之可利用性使得可最佳化雙側DIMM或其他 模組設置的連接設計。 可互換信號當然可以有另外的調整和變化。例如’可 互換信號也可應用到疊置DRAM計數。此外,可利用封裝 類型的變化。例如,可使用X16封裝類型,與X4/X8封 裝類型。 如此,雖然以此觀點實施例說明記憶模組中的可互換 連接之方法和設備,但是除了下面申請專利範圍所陳述之 外,此種特定參考並不可被視作本發明的範圍限制。 【圖式簡單說明】 藉由篸照圖式閱讀揭示可更加瞭解本發明的實施例, 其中 : 圖1爲雙側雙面貼裝記憶模組裝設之習知實施例。 圖2爲雙側雙面貼裝記憶模組裝設之實施例。 -12- 1295063 Ο) 圖3爲基底上的記憶封裝之其他配置。 圖4爲使用雙側記憶模組的記憶系統之實施例。 圖5a及5b爲疊層記憶模組的其他實施例。 圖6爲具有可互換性的雙面貼裝記憶模組之實施例的 連接圖。 圖7爲雙面貼裝記憶模組的另一實施例之連接圖。 圖8爲雙面貼裝記億模組的另一實施例之連接圖。 圖9爲設計雙面貼裝記憶模組的方法之實施例的方塊 圖0 【主要元件之符號說明】 10 : 棊底 12a ·· 記憶 模 組 12b : 記憶 模 組 13: 通孔 14a ·· 記憶 模 組 14b ·· 記憶 模 組 16a - 第一 信 號 軌 跡 16b : 第二 信 號 軌 跡 18 : 導體棒 2 0 ·· 連接 22 : 連接 24 : 連接 2 6 :連接 - 13- (10) 1295063 28a:第一路由長度 28b:第二路由長度 3 0 :連接 3 2 :連接 3 4 :連接 3 6 :連接
3 8 :記憶控制器 40a :記憶模組
4 0 b :記憶模組 40c :記憶模組 4 0 d :記憶模組 40e :記憶模組 40f :記憶模組 4 0 g :記憶模組 40h :記憶模組 4 2 a :記憶模組 4 4a:記憶晶銳 4 4 b :記憶晶f定 4 6 ··球 4 6 a :焊球 4 6 b :焊球
Claims (1)
1295063 Γ___ ‘‘ 卓6. PW正替換頁 十、申請專利範圍 附件4A: 第94 1 04530號專利申請案 中文申請專利範圍替換本 民國96年12月31日修正 ^ 1 · 一種記憶系統,包含: - 第一記憶模組,裝設在基底的第一側上,該第一記憶 g 模組包含: 連接陣列,以列和行排列成具有第一和第二外面行, 及在第一和第二外面行的連接可互換以安排該連接爲在各 個連接上的信號行經一致的路由長度; 第二記憶模組,裝設在基底的第二側上,包含: 連接陣列,以列和行排列成具有第一和第二外面行, 及在第一和第二外面行的連接可互換以安排該連接爲在各 個連接上的信號行經一致的路由長度;和 ϋ 記憶控制器,藉由傳輸原先欲用於在第一外面行的連 接的信號至在第一外面行的連接已互換的第二外面行中的 連接,用以控制記憶模組的第一和第二外面行之間的信號 之互換。 2. 如申請專利範圍第1項之記憶系統,其中該基底 另外包含多層印刷電路板。 3. 如申請專利範圍第2項之記憶系統,其中在該多 層印刷電路板中包含信號軌跡。 4.如申請專利範圍第1項之記憶系統,其中該記億 1295063 「I6·赁31日修正替換頁丨 模組被封裝在選自由X 1 6和X4/X 8所組成的群組的封裝 中〇 5· —種記憶裝置,包含: 記憶陣列,具有以列和行排列的記憶連接陣列; 模組,用以接收記憶陣列;和 模組上的連接器,具有以列和行排列的連接器連接陣 列,使得記憶連接和連接器連接可互換,以使在各個連接 器連接上的訊號行經一致的路由長度。 6 ·如申請專利範圍第5項之記憶裝置,其中該模組 另外包含雙面貼裝記憶模組。 7 ·如申請專利範圍第6項之記憶裝置,其中該模組 選自由X16封裝和X4/X8所組成的群組的封裝。 8. 一種設計記憶裝置之方法,包含: 決定一組可互換的記憶信號和一組固定的記憶信號; 將一組可互換的記憶信號排列在連接陣列的外面行; 及 將一組固定的記憶信號排列在連接陣列的內面行。 9. 如申請專利範圍第8項之方法,其中決定一組可 互換的記憶信號另外包含識別在一列內的位址連接作可互 換的。 10. 如申請專利範圍第8項之方法,其中決定一組可 互換的信號另外包含識別記憶庫位址連接作可互換的。 11. 如申請專利範圍第8項之方法,其中將一組可互 換的記憶信號排列在連接陣列的外面行另外包含將一組可 -2 - 1295063 ye. 12. 31 1年月曰修正替換頁 互換的記憶信號排列在連接陣列之每一側上的兩外面行。 1 2 ·如申請專利範圍第8項之方法,其中將一組可互 換的記憶信號排列在連接陣列的外面行另外包含將一組可 互換的記憶信號排列在連接陣列之每一側上的一外面行。
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JP2007525769A (ja) | 2007-09-06 |
TW200540876A (en) | 2005-12-16 |
US20050195629A1 (en) | 2005-09-08 |
WO2005093757A1 (en) | 2005-10-06 |
US20080062734A1 (en) | 2008-03-13 |
EP1723654B1 (en) | 2010-06-30 |
EP1723654A1 (en) | 2006-11-22 |
US20130341790A1 (en) | 2013-12-26 |
ATE472801T1 (de) | 2010-07-15 |
CN1926632B (zh) | 2011-08-03 |
DE602005022053D1 (de) | 2010-08-12 |
US20120199973A1 (en) | 2012-08-09 |
CN1926632A (zh) | 2007-03-07 |
US8099687B2 (en) | 2012-01-17 |
US8438515B2 (en) | 2013-05-07 |
US8775991B2 (en) | 2014-07-08 |
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