US20050103749A1 - Method and device for anisotropic etching of high aspect ratio - Google Patents

Method and device for anisotropic etching of high aspect ratio Download PDF

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Publication number
US20050103749A1
US20050103749A1 US10/500,654 US50065404A US2005103749A1 US 20050103749 A1 US20050103749 A1 US 20050103749A1 US 50065404 A US50065404 A US 50065404A US 2005103749 A1 US2005103749 A1 US 2005103749A1
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Prior art keywords
gas
substrate
etching
plasma
depassivation
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Michel Puech
Emile van der Drift
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Alcatel Lucent SAS
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Alcatel SA
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Assigned to ALCATEL reassignment ALCATEL ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BLAUW, MICHEL, ZILSTRA, TONY, VAN DER DRIFT, EMILE, PUECH, MICHEL
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00619—Forming high aspect ratio structures having deep steep walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0111—Bulk micromachining
    • B81C2201/0112—Bosch process

Definitions

  • the present invention relates to methods and apparatuses used for making micro-relief at the surface of substrates, in particular silicon substrates.
  • the invention relates more particularly to methods and apparatuses enabling such relief to be made by anisotropic chemical attack by plasma, for making silicon-based components, e.g. semiconductor components for electronics, or parts for micromechanical components.
  • silicon-based components e.g. semiconductor components for electronics, or parts for micromechanical components.
  • MEMS micro-electro-mechanical systems
  • Another example is the desire to make holes having a diameter of about 10 ⁇ m through the entire thickness of a silicon wafer in order to make connection sockets: once metal-plated, such holes would enable electrical connections to be made with the outside without using gold wires, as is conventional. That would make it possible to provide connections that are highly reproducible, and above all much shorter, thereby reducing stray inductance and thus presenting a great advantage for high frequency applications.
  • the micromachining of silicon substrates is presently performed by plasma etching techniques.
  • the technique that is the most widespread for this purpose at present is fluorinated gas plasma etching as described in documents U.S. Pat. No. 5,501,893 and U.S. Pat. No. 4,985,114. That technique consists in protecting part of the silicon substrate by a mask, and in subjecting the substrate as protected in part in this way to an alternating succession of attack steps using a plasma of etching gas, and of passivation steps using a plasma of passivation gas. During each attack step, the plasma of etching gas such as sulfur hexafluoride SF 6 makes cavities in those zones of the substrate that are not protected by the mask.
  • etching gas such as sulfur hexafluoride SF 6
  • the plasma of passivation gas such as a fluorocarbon gas, e.g. C 4 F 8 , deposits a protective polymer film on the wall of the cavity.
  • passivation gas such as a fluorocarbon gas, e.g. C 4 F 8
  • the passivation serves, during the subsequent attack step, to ensure that the plasma of etching gas does not attack the side wall of the cavity.
  • attack takes place selectively in the bottom of the cavity, after the plasma of etching gas has removed the protective polymer film from the bottom of the cavity.
  • a first solution has been to increase the energy of the ions during the etching step, by increasing the bias voltage of the substrate. This reduces the number of ions lost against the walls of the trench, and it is possible to benefit from a larger number of ions for breaking up the layer of polymer in the bottom of the trench. It has thus been possible to increase the aspect ratio a little, but only from a ratio of 20 to a ratio of 23.
  • that solution presents the major drawback of increasing the rate at which the mask itself is attacked, which mask is made of silica or of photosensitive resin, thereby reducing the selectivity of the etching.
  • a second solution which has been devised is to increase the flux of ions reaching the surface of the substrate, in the hope that there will then be sufficient ions to break up the polymer film in the bottoms of the cavities.
  • a first technique has been to increase the power of the plasma source. That enables the aspect ratio to be increased up to about 27, while also degrading selectivity compared with the mask, as in the preceding solution.
  • the substrate has been placed closer to the plasma source, and that also makes it possible to increase the aspect ratio up to about 27.
  • uniformity of etching is then degraded, i.e. the depth of etching varies as a function of the zone under consideration in the substrate.
  • a third solution that has been devised is to reduce the working pressure so as to increase the mean free path length of the particles, thereby reducing collisions between particles and increasing the directivity of ions.
  • That solution does not enable aspect ratio to be increased significantly, and it presents the drawback of considerably reducing the rate at which the silicon is etched, which is contrary to the looked-for object.
  • Curve A represents the usual method of etching by alternating steps of attack by means of a plasma of fluorinated gas and steps of passivation by a plasma of fluorocarbon gas, in accordance with document U.S. Pat. No. 5,501,893.
  • Curve B shows the result obtained by increasing the bias voltage of the substrate, i.e. by increasing the bombardment energy of the plasma ions.
  • Curve C shows the result obtained by moving the substrate closer to the plasma source.
  • Curve D shows the result obtained by reducing the pressure of the atmosphere in the etching chamber by a factor of 2.
  • each curve reveals how etching speed or the speed at which cavities are excavated, varies progressively as a function of the depth the cavity has reached. It can be seen that for each curve, the etching speed decreases progressively as a function of cavity depth. For each curve, a depth maximum is reached, and this maximum determines the maximum aspect ratio that can be achieved by the method.
  • Curve A shows a maximum aspect ratio of about 21.
  • Curve B shows a maximum aspect ratio of about 23.
  • Curve C shows a maximum aspect ratio of about 29.
  • Curve D shows a maximum aspect ratio of about 23.
  • An object of the present invention is to implement etching of silicon with anisotropy that is almost perfect, without undercut attack and without the cavity tapering progressively, down to depths that are considerably increased, making it possible to achieve aspect ratios greater than 30.
  • the invention also seeks to implement such etching at speeds that are at least as fast if not faster than the etching speeds achieved by known methods of alternating steps of attack by fluorinated gas plasma and passivation by fluorocarbon gas plasma.
  • the invention provides a method of etching silicon anisotropically, in which a silicon substrate protected in part by a mask is subjected to an alternating succession of attack steps using a plasma of etching gas to make cavities in zones of the substrate that are not protected by the mask, and passivation steps using a plasma of passivation gas for depositing protective polymer on the walls of the cavities that result from the attack steps,
  • the method includes a selective depassivation pulse step after each passivation step.
  • each selective depassivation pulse step does not overlap the preceding passivation step, and does not overlap the following attack step.
  • the etching gas may be a fluorine gas such as SF 6 , CF 4 , or NF 3 .
  • SF 6 fluorine gas
  • CF 4 CF 4
  • NF 3 NF 3
  • the passivation gas may be a fluorocarbon gas such as CHF 3 , C 2 F 6 , C 2 F 4 , C 4 F 8 , or mixtures thereof.
  • the cleaning gas may advantageously contain oxygen.
  • oxygen As a cleaning gas, it is possible to use at least one of the following gases: O 2 , SO 2 , CO, CO 2 , NO, NO 2 , N 2 O, and mixtures thereof.
  • the invention provides apparatus for anisotropic etching of a silicon substrate, to implement a method as defined above, the apparatus comprising:
  • the invention enables silicon-based components to be made having micro-relief presenting an aspect ratio of more than 30, e.g. by using a method as defined above.
  • Such components are themselves novel in character since it has not been possible to make them until now.
  • FIG. 1 shows the profile of trenches made using a prior art etching method
  • FIG. 2 is a graph plotting curves of etching speed as a function of aspect ratio for various prior art etching methods
  • FIG. 3 is a graph plotting the speed with which a protective polymer film is attacked, as a function of the substrate bias voltage, firstly for attack using SF 6 , and secondly for attack using an oxygen plasma;
  • FIG. 4 is a diagram of etching apparatus constituting an embodiment of the invention.
  • FIG. 5 is a timing chart showing the steps of the method in an implementation of the invention.
  • FIG. 6 is a diagram showing the way in which a cavity is formed during a sequence of four successive steps in the method of FIG. 5 ;
  • FIG. 7 shows the profiles of trenches being made by an etching method of the invention.
  • Such apparatus comprises a gastight enclosure 1 shaped to receive and contain a substrate 2 for etching.
  • the substrate 2 is placed on a support 3 , itself negatively biased relative to ground by bias means comprising a bias source 4 .
  • a vacuum-generator device 6 is connected to the enclosure 1 via a pipe 7 , and comprises, for example, a primary pump and a secondary pump, enabling a suitable vacuum to be created and maintained inside the enclosure 1 .
  • the substrate 2 is oriented in the enclosure 1 in such a manner that its surface 2 a for working is visible.
  • the plasma generation means 8 Facing the surface 2 a that is to be machined, there are plasma generation means 8 for generating a plasma 9 that is directed towards the surface 2 a that is to be machined and that is attracted by the substrate 2 biased by the bias source 4 .
  • the plasma generation means 8 comprise a microwave or radiofrequency generator 10 that acts, via a transducer or radiofrequency applicator 11 to excite atoms of gas in a plasma generation zone 12 .
  • the apparatus also includes means 13 for selectively injecting into the enclosure 1 etching gas, passivation gas, and depassivation gas.
  • these gas injection means 13 comprise a gas inlet 14 for admitting gas into the enclosure 1 , preferably upstream from the plasma generation zone 12 , the gas inlet 14 being connected by pipes 15 and control valves 16 , 17 , and 18 respectively to an etching gas source 19 , to a passivation gas source 20 , and to a cleaning gas source 21 .
  • the control valves 16 , 17 , and 18 are actuated by control means 22 to control the injection of gas in the successive steps of etching, passivation, and depassivation in the method that is described below.
  • FIG. 5 show respectively the times during which the valve 16 is open to admit etching gas, the times during which the valve 17 is open to admit passivation gas, and the times during which the valve 18 is open to admit cleaning gas. It can be seen that the steps of the method are pulse steps, i.e. of limited duration between stop periods.
  • the first step a) of attack consists in opening the valve 16 to generate a plasma 9 of etching gas.
  • the first step a) of attack is followed by a non-overlapping, second step b) of passivation during which the valve 16 is closed and the valve 17 is open in order to generate a plasma 9 of passivation gas. Thereafter, the valve 17 is closed, and during a selective depassivation step c), the valve 18 is opened to generate a plasma 9 of cleaning gas. Thereafter the valve 18 is closed and the operations are restarted in a step d) by opening the valve 16 again to generate a plasma of etching gas, and so on.
  • the successive steps a), b), c), and d) do not overlap one another. Nevertheless, without going beyond the ambit of the invention, it would be possible to make provision for a step c) that overlaps one and/or the other of adjacent steps b) and d).
  • step a) of generating a plasma of etching gas there is admitted into the enclosure 1 an etching gas of the fluorinated gas type, such as SF 6 , CF 4 , or NF 3 , for example.
  • etching gas of the fluorinated gas type such as SF 6 , CF 4 , or NF 3 , for example.
  • excellent results are obtained using sulfur hexafluoride SF 6 .
  • the atoms of fluorine generated by the plasma attack the exposed surface area of silicon in isotropic manner.
  • FIG. 6 is a diagram showing the action of the plasmas on the substrate: the substrate 2 is shown in fragmentary section at a large scale, at the location where a cavity 2 b is to be made: the substrate 2 is covered by a mask 2 c which includes an opening 2 d in register with the cavity 2 b that is to be made.
  • the opening 2 d the surface of the substrate 2 remains visible and accessible to the plasma.
  • the substrate 2 is shown before etching.
  • FIG. 6 there is shown the action of the plasma of etching gas SF 6 attacking the silicon of the substrate 2 isotropically in register with the opening 2 d so as to make a first segment 2 b 1 of the cavity 2 b .
  • the duration of the etching step between instants t 1 and t 2 in FIG. 5 is selected so that the first segment 2 b 1 of the cavity presents a shape that differs little from the desired shape, i.e. with a side wall 2 e that is substantially perpendicular to the surface 2 a of the substrate.
  • a first segment 2 b 1 having a depth of a few micrometers can be appropriate.
  • the substrate 2 may be biased at about 20 volts (V) to 80 V, the pressure of the gaseous atmosphere 5 inside the enclosure 1 may be about 10 pascals (Pa) to 100 Pa, and the flow rate of the etching gas may be about 10 standard cubic centimeters per minute (sccm) to 200 sccm.
  • V volts
  • Pa pascals
  • sccm standard cubic centimeters per minute
  • a plasma of passivation gas is generated by using a fluorocarbon gas such as CHF 3 , C 2 F 6 , C 2 F 4 , or C 4 F 8 .
  • the pressure of the atmosphere 5 in the enclosure 1 is similar to that in step a) and the passivation gas flow rate lies in the range 50 sccm to 300 sccm.
  • the plasma of passivation gas causes a protective polymer film 2 f to be formed over the entire inside surface of the first segment 2 b 1 of the cavity, i.e. both over its side wall 2 e and its bottom 2 g .
  • the duration between the start instant t 2 and the end instant t 3 of step b) is selected so as to cause the thickness of the protective film to be satisfactory, for example of the order of a few nanometers (nm) to a few tens of nm.
  • a plasma of cleaning or depassivation gas is generated, which gas is selected so as to provide cleaning of the polymer that is more effective than that which is provided by the etching gas, and serves to remove polymer from the bottom zone 2 g of the cavities 2 b in selective manner.
  • a cleaning gas containing-oxygen e.g. a cleaning gas containing at least one of the following gases: O 2 , SO 2 , CO, CO 2 , NO, NO 2 , N 2 O.
  • the substrate 2 is preferably simultaneously biased by the bias source 4 so as to attack the ions of oxygen to the substrate 2 .
  • a plasma of gas containing oxygen atoms benefits not only from the oxidizing effect of the ions, but also from the oxidizing effect of atoms which are neutral particles with an isotropic trajectory. It is found that the cleaning step makes it possible also to remove polymer film from the vertical sides of the cavity in the vicinity of the bottom of the cavity, thus ensuring that the patterns do not taper and making it possible to reach higher aspect ratios.
  • the substrate 2 is biased with a voltage close to that used during the attack step, typically in the range 20 V to 120 V, and advantageously in the range 20 V to 80 V, so as to attract the plasma ions.
  • the pressure of the atmosphere 5 surrounding the substrate 2 lies in the range 0.5 Pa to 10 Pa, and preferably lies in the range 2 Pa to 5 Pa.
  • the flow rate of the cleaning gas lies in the range 10 sccm to 100 sccm, and the duration of step c) is selected to be just sufficient to ensure effective cleaning of the bottom zones 2 g of the cavities 2 b.
  • the depassivation step by the action of the plasma of oxygen O 2 serves to remove effectively and quickly the polymer film from the bottom 2 g of the first segment 2 b 1 of a cavity.
  • step d an attack step is performed again similar to step a), by the action of the plasma of the etching gas SF 6 , thereby making a second segment 2 b 2 of the cavity 2 b .
  • step d an attack step is performed again similar to step a), by the action of the plasma of the etching gas SF 6 , thereby making a second segment 2 b 2 of the cavity 2 b .
  • step d there follows a pulse step of passivation, and a step of depassivation, and so on.
  • the duration of the pulse steps c) for selective depassivation can be determined as a function of the duration of the preceding passivation step b). The thicker the polymer film, the longer the time required for the selective depassivation pulse step.
  • the duration of the selective depassivation pulse step may be selected to increase from one depassivation step to another during the process of etching a single substrate 2 .
  • the initial etching steps enable a cavity to be made having a side wall that is substantially vertical up to an aspect ratio of about 20 without there being any need to use lengthy cleaning steps in order to conserve a constant section for the cavity.
  • the advantage of the depassivation step is then merely that of increasing the speed of the method. However, thereafter, it becomes essential to use the depassivation step in order to guarantee that an aspect ratio in excess of 20 or 30 can be achieved.
  • depassivation steps of duration that is progressively longer with increasing aspect ratio, or indeed depassivation steps in increasing numbers, for example rising from one passivation step for three attack and passivation steps, to one depassivation step for two attack and passivation steps, and passing finally to one depassivation step for one attack and passivation step.
  • the bias voltage applied to the substrate 2 it is possible to provide for the bias voltage applied to the substrate 2 to increases progressively from one depassivation step to another during the process of etching a substrate 2 .
  • the method of the invention makes it possible simultaneously to obtain aspect ratios that are considerably greater than those obtained with prior art methods, while guaranteeing good selectivity with respect to photoresist masks, while also increasing the overall speed of etching.
  • FIG. 7 is a photograph of a section of a silicon substrate after an operation of partial etching using a method of the present invention.
  • the substrate 2 whose surface 2 a is covered by a mask 2 c .
  • the cavities 2 b that are being etched present side walls that are substantially vertical, such that their bottoms 2 g remain of sufficient cross-section to make additional etching possible for increasing the depth of the cavities 2 b , thereby increasing their aspect ratio.

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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US10/500,654 2002-01-03 2002-12-31 Method and device for anisotropic etching of high aspect ratio Abandoned US20050103749A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0200032A FR2834382B1 (fr) 2002-01-03 2002-01-03 Procede et dispositif de gravure anisotrope du silicium a haut facteur d'aspect
FR02/00032 2002-01-03
PCT/FR2002/004588 WO2003060975A1 (fr) 2002-01-03 2002-12-31 Procede et dispositif de gravure anisotrope du silicium a haut facteur d'aspect

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US (1) US20050103749A1 (ja)
EP (1) EP1464078A1 (ja)
JP (1) JP4576122B2 (ja)
FR (1) FR2834382B1 (ja)
WO (1) WO2003060975A1 (ja)

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WO2008007962A1 (en) * 2006-07-12 2008-01-17 Technische Universiteit Eindhoven Method and device for etching a substrate by means of a plasma
EP1933375A2 (en) * 2006-12-13 2008-06-18 Applied Materials, Inc. Methods for Recess Etching
US20090162790A1 (en) * 2007-12-21 2009-06-25 Lam Research Corporation Photoresist double patterning
US20090221148A1 (en) * 2008-02-29 2009-09-03 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and computer-readable storage medium
US20090242512A1 (en) * 2008-03-27 2009-10-01 Dalsa Semiconductor Inc. Deep reactive ion etching
US20090272717A1 (en) * 2008-03-21 2009-11-05 Applied Materials, Inc. Method and apparatus of a substrate etching system and process
US20100041237A1 (en) * 2006-09-30 2010-02-18 Sang-Yu Lee Method for forming a fine pattern using isotropic etching
US20100159707A1 (en) * 2004-04-30 2010-06-24 Lam Research Corporation Gas distribution system having fast gas switching capabilities
US20100197138A1 (en) * 2009-01-31 2010-08-05 Applied Materials, Inc. Method and apparatus for etching
US9305810B2 (en) 2011-06-30 2016-04-05 Applied Materials, Inc. Method and apparatus for fast gas exchange, fast gas switching, and programmable gas delivery

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FR2880469B1 (fr) * 2005-01-03 2007-04-27 Cit Alcatel Dispositif de fabrication d'un masque par gravure par plasma d'un substrat semiconducteur
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JP5305734B2 (ja) * 2008-05-19 2013-10-02 ラピスセミコンダクタ株式会社 ドライエッチング方法
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DE102014216195A1 (de) * 2014-08-14 2016-02-18 Robert Bosch Gmbh Vorrichtung zum anisotropen Ätzen eines Substrats und Verfahren zum Betreiben einer Vorrichtung zum anisotropen Ätzen eines Substrats
JP6456131B2 (ja) * 2014-12-18 2019-01-23 キヤノン株式会社 基板の加工方法及び液体吐出ヘッドの製造方法
JP6609535B2 (ja) * 2016-09-21 2019-11-20 株式会社日立ハイテクノロジーズ プラズマ処理方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501893A (en) * 1992-12-05 1996-03-26 Robert Bosch Gmbh Method of anisotropically etching silicon
US6136214A (en) * 1996-04-26 2000-10-24 Hitachi, Ltd. Plasma processing method and apparatus
US6277756B1 (en) * 1999-02-12 2001-08-21 Denso Corporation Method for manufacturing semiconductor device
US20020134749A1 (en) * 2001-01-26 2002-09-26 Chromux Technologies. Inc. Method of making a vertical, mirror quality surface in silicon and mirror made by the method
US20020144974A1 (en) * 1998-06-12 2002-10-10 Franz Laermer Method of anisotropic etching of silicon
US6846746B2 (en) * 2002-05-01 2005-01-25 Applied Materials, Inc. Method of smoothing a trench sidewall after a deep trench silicon etch process

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612767B2 (ja) * 1984-01-25 1994-02-16 株式会社日立製作所 溝およびそのエッチング方法
JP2502536B2 (ja) * 1986-08-08 1996-05-29 松下電器産業株式会社 パタ―ン形成方法
JPH0817796A (ja) * 1994-06-28 1996-01-19 Hitachi Ltd ドライエッチング装置とその方法および半導体装置
ATE251341T1 (de) * 1996-08-01 2003-10-15 Surface Technology Systems Plc Verfahren zur ätzung von substraten
JPH11195641A (ja) * 1998-01-05 1999-07-21 Matsushita Electric Ind Co Ltd プラズマ処理方法
WO1999049506A1 (en) * 1998-03-20 1999-09-30 Surface Technology Systems Limited Method and apparatus for manufacturing a micromechanical device
KR100639841B1 (ko) * 1998-07-23 2006-10-27 서페이스 테크놀로지 시스템스 피엘씨 이방성 에칭 장치 및 방법
JP4680333B2 (ja) * 1998-12-28 2011-05-11 東京エレクトロンＡｔ株式会社 プラズマ処理方法、エッチング方法、プラズマ処理装置及びエッチング装置
DE19919469A1 (de) * 1999-04-29 2000-11-02 Bosch Gmbh Robert Verfahren zum Plasmaätzen von Silizium

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501893A (en) * 1992-12-05 1996-03-26 Robert Bosch Gmbh Method of anisotropically etching silicon
US6136214A (en) * 1996-04-26 2000-10-24 Hitachi, Ltd. Plasma processing method and apparatus
US20020144974A1 (en) * 1998-06-12 2002-10-10 Franz Laermer Method of anisotropic etching of silicon
US6277756B1 (en) * 1999-02-12 2001-08-21 Denso Corporation Method for manufacturing semiconductor device
US20020134749A1 (en) * 2001-01-26 2002-09-26 Chromux Technologies. Inc. Method of making a vertical, mirror quality surface in silicon and mirror made by the method
US6846746B2 (en) * 2002-05-01 2005-01-25 Applied Materials, Inc. Method of smoothing a trench sidewall after a deep trench silicon etch process

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100159707A1 (en) * 2004-04-30 2010-06-24 Lam Research Corporation Gas distribution system having fast gas switching capabilities
US8673785B2 (en) * 2004-04-30 2014-03-18 Lam Research Corporation Gas distribution system having fast gas switching capabilities
WO2008007962A1 (en) * 2006-07-12 2008-01-17 Technische Universiteit Eindhoven Method and device for etching a substrate by means of a plasma
US9209108B2 (en) 2006-09-30 2015-12-08 Lg Innotek Co., Ltd. Method for forming a fine pattern using isotropic etching
US20100041237A1 (en) * 2006-09-30 2010-02-18 Sang-Yu Lee Method for forming a fine pattern using isotropic etching
US8486838B2 (en) * 2006-09-30 2013-07-16 Lg Innotek Co., Ltd. Method for forming a fine pattern using isotropic etching
EP1933375A2 (en) * 2006-12-13 2008-06-18 Applied Materials, Inc. Methods for Recess Etching
US20080146034A1 (en) * 2006-12-13 2008-06-19 Applied Materials, Inc. Method for recess etching
EP1933375A3 (en) * 2006-12-13 2009-04-29 Applied Materials, Inc. Methods for Recess Etching
US8282847B2 (en) * 2007-12-21 2012-10-09 Lam Research Corporation Photoresist double patterning
US20090162790A1 (en) * 2007-12-21 2009-06-25 Lam Research Corporation Photoresist double patterning
US8911587B2 (en) 2007-12-21 2014-12-16 Lam Research Corporation Photoresist double patterning apparatus
US20090221148A1 (en) * 2008-02-29 2009-09-03 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and computer-readable storage medium
US20090272717A1 (en) * 2008-03-21 2009-11-05 Applied Materials, Inc. Method and apparatus of a substrate etching system and process
EP2105952A3 (en) * 2008-03-27 2010-10-20 Dalsa Semiconductor Inc. Deep reactive ion etching
US20090242512A1 (en) * 2008-03-27 2009-10-01 Dalsa Semiconductor Inc. Deep reactive ion etching
US20120208300A1 (en) * 2009-01-31 2012-08-16 Applied Materials, Inc. Etch processing chamber
CN102768933A (zh) * 2009-01-31 2012-11-07 应用材料公司 用于蚀刻的方法
US20100197138A1 (en) * 2009-01-31 2010-08-05 Applied Materials, Inc. Method and apparatus for etching
US8937017B2 (en) * 2009-01-31 2015-01-20 Applied Materials, Inc. Method and apparatus for etching
US9305810B2 (en) 2011-06-30 2016-04-05 Applied Materials, Inc. Method and apparatus for fast gas exchange, fast gas switching, and programmable gas delivery

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