US20030034809A1 - Variable-frequency pulse generator - Google Patents

Variable-frequency pulse generator Download PDF

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Publication number
US20030034809A1
US20030034809A1 US10/203,405 US20340502A US2003034809A1 US 20030034809 A1 US20030034809 A1 US 20030034809A1 US 20340502 A US20340502 A US 20340502A US 2003034809 A1 US2003034809 A1 US 2003034809A1
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value
mhz
unit
reference value
output
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Yasuhiro Nakashima
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKASHIMA, YASUHIRO
Publication of US20030034809A1 publication Critical patent/US20030034809A1/en
Priority to US10/790,198 priority Critical patent/US6822492B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Definitions

  • the present invention relates to a variable-frequency pulse generator capable of generating a pulse of the desired frequency.
  • FIG. 12 shows a configuration of a variable-frequency pulse generator disclosed in the above publication.
  • the reference symbol 100 denotes a conventional variable-frequency pulse generation circuit
  • 101 denotes a bit inverter which inverts a first reference value D 1
  • 102 denotes a data selector which selects either one of the output of the inverter 101 and a pulse number set value Ps
  • 103 denotes a digital adder which adds the output ⁇ 1 of a first data holding circuit described later and the output of the data selector 102
  • 104 denotes the first data holding circuit which latches the output ⁇ 2 of the digital adder 103 at the timing T 2 of a reference clock fb.
  • the reference symbol 105 denotes a first data comparator which compares the output ⁇ 1 of the first data holding circuit 104 and the first reference value D 1
  • 106 denotes a second data comparator which compares the output ⁇ 1 of the first data holding circuit 104 and a second reference value D 2 .
  • the reference symbol 107 denotes a pulse generation circuit which judges the output level (High or Low) based on the two comparison results
  • 108 denotes a second data holding circuit which latches the output fd of the pulse generation circuit 107 at the timing T 3 of the reference clock fb and outputs a pulse train fout
  • 109 denotes an overflow prevention circuit which outputs the overflow prevention signal fob synchronous with the reference clock fb based on the comparison result of the first data comparator 105 .
  • the control clock frequency fc is [fb/4].
  • the first reference value D 1 is [fc ⁇ n]
  • the second reference value D 2 is [(fc/2) ⁇ n].
  • the pulse number set value per n seconds Ps is [Vp ⁇ n], and the value thereof can be set for 1 unit in the range of [0 ⁇ Ps ⁇ (fc/2) ⁇ n ⁇ ].
  • n denotes the maximum cycle of the output pulse
  • Vp denotes a speed set value.
  • the inverter 101 outputs a bit inversion value of the reference value D 1 in the 26-bit notation.
  • the data selector 102 When the S terminal is 0 ( ⁇ 1 ⁇ D 1 ), the data selector 102 outputs the pulse number set value Ps (26-bit notation) of a terminal A to a terminal Y, and when the S terminal is 1 ( ⁇ 1 >D 1 ), the data selector 102 outputs the bit inversion value of the reference value D 1 of a terminal B to the terminal Y.
  • the first data holding circuit 104 latches the addition result ⁇ 2 at the timing T 2 of the reference clock fb and the overflow prevention signal fob, and out puts data ⁇ 1 (26-bit notation).
  • the first data comparator 105 compares the output ⁇ 1 of the first data holding circuit 104 and the first reference value D 1 , and when ⁇ 1 >D 1 , outputs 1 as the overflow signal.
  • the second data comparator 106 compares the output ⁇ 1 of the first data holding circuit 104 and the second reference value D 2 .
  • the second data holding circuit 108 latches the judgment result fd at the timing T 3 of the reference clock fb, and outputs a pulse train fout.
  • the overflow prevention circuit 109 receives the overflow signal output from the first data comparator 105 at the timing T 4 of the reference clock fb, and outputs an overflow prevention signal fob.
  • FIG. 13 is a timing chart which shows the operation of the conventional variable-frequency pulse generator.
  • the speed change timing ⁇ t changes at a period synchronous with the timing T 1 of the reference clock fb and the speed change timing, and acceleration and deceleration speed is latched at the timing T 1 of the reference clock fb. This operation is executed by the part other than the configuration shown in FIG. 12.
  • the first data holding circuit 104 latches the output ⁇ 2 of the digital adder 103 at the timing T 2 of the reference clock fb.
  • the second data holding circuit 108 then latches the output fd of the pulse generation circuit 107 at the timing T 3 of the reference clock fb, and outputs the pulse train fout.
  • the variable-frequency pulse generator has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit (corresponding to an inverter 11 in the embodiment described later) which inverts a first reference value regulated by the reference clock, a selection unit (corresponding to a data selector 12 ) which selects the first reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit (corresponding to a first data holding circuit 14 ) which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of an overflow prevention signal, an addition unit (corresponding to a digital adder 13 ) which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit (corresponding to a first data comparator 15 ) which compares the value obtained by
  • the variable-frequency pulse generator according to the next invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an addition unit (corresponding to a digital adder 21 ) which adds a predetermined value, which changes depending on a set speed, and data latched at a predetermined timing of the second cycle of the reference clock, a subtraction unit (corresponding to a digital subtracter 22 ) which subtracts a first reference value regulated by the reference clock from the value obtained by the addition unit as a result of addition, a first comparison unit (corresponding to a first data comparator 25 ) which compares the value obtained by the addition unit as a result of addition and the first reference value, and when a condition “addition result ⁇ first reference value” is satisfied, judges that an overflow has occurred, a second comparison unit (corresponding to a second data comparator 26 ) which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value,
  • the variable-frequency pulse generator has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit which inverts a reference value regulated by the reference clock, a selection unit which selects the reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of an overflow prevention signal, an addition unit which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit which compares the value obtained by the addition unit as a result of addition and the reference value, a judgment unit (corresponding to a pulse generation circuit 17 c ) which judges whether a condition “the overflow frequency is an even number” and “0 ⁇ addition result ⁇ reference value” is satisfied
  • the variable-frequency pulse generator has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit which inverts a first reference value regulated by the reference clock, a selection unit which selects the first reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of the overflow prevention signal, an addition unit which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit which compares the value obtained by the addition unit as a result of addition and the first reference value, a second comparison unit which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value, a judgment unit which judges whether a
  • FIG. 1 shows the configuration of a first embodiment of a variable-frequency pulse generator according to the present invention
  • FIG. 2 is a timing chart which shows the operation of the variable-frequency pulse generator in the first embodiment
  • FIG. 3 shows the output result of each section, when the variable-frequency pulse generator in the first embodiment is operated
  • FIG. 4 shows the output waveform of the variable-frequency pulse generator in the first embodiment
  • FIG. 5 shows the configuration of a second embodiment of the variable-frequency pulse generator according to the present invention
  • FIG. 6 is a timing chart which shows the operation of the variable-frequency pulse generator in the second embodiment
  • FIG. 7 shows the output result of each section, when the variable-frequency pulse generator in the second embodiment is operated
  • FIG. 8 shows the configuration of a third embodiment of the variable-frequency pulse generator according to the present invention.
  • FIG. 9 shows the output result of each section, when the variable-frequency pulse generator in the third embodiment is operated.
  • FIG. 10 shows the configuration of a fourth embodiment of the variable-frequency pulse generator according to the present invention.
  • FIG. 11 shows the output result of each section, when the variable-frequency pulse generator in the fourth embodiment is operated.
  • FIG. 12 shows the configuration of a conventional variable-frequency pulse generator
  • FIG. 13 is a timing chart which shows the operation of the conventional variable-frequency pulse generator.
  • variable-frequency pulse generator According to this invention will be explained in detail below with reference to the accompanying drawings. However, this invention is not limited by these embodiments.
  • FIG. 1 shows the configuration of a first embodiment of the variable-frequency pulse generator according to the present invention.
  • the reference symbol 1 a denotes a variable-frequency pulse generation circuit in the first embodiment
  • 11 denotes a bit inverter which inverts a first reference value D 1
  • 12 denotes a data selector which selects either one of the output of the inverter 11 and a pulse number set value Ps
  • 13 denotes a digital adder which adds the output ⁇ 1 of a first data holding circuit 14 described later and the output of the data selector 12
  • 14 denotes a first data holding circuit which latches the output ⁇ 2 of the digital adder 13 at the timing T 2 of a reference clock fb.
  • the reference symbol 15 denotes a first data comparator which compares the output ⁇ 2 of the digital adder 13 and the first reference value D 1
  • 16 denotes a second data comparator which compares the output ⁇ 2 of the digital adder 13 and a second reference value D 2 .
  • the reference symbol 17 denotes a pulse generation circuit which judges the output level (High or Low) based on the two comparison results
  • 18 denotes a second data holding circuit which latches the output fd of the pulse generation circuit 17 at the timing T 2 of the reference clock fb and outputs a pulse train fout
  • 19 denotes a third data comparator which compares the output ⁇ 1 of the first data holding circuit 14 and the first reference value D 1
  • 20 denotes an overflow prevention circuit which outputs an overflow prevention signal fob based on the comparison result of the third data comparator 19 .
  • the control clock frequency fc is [fb/2 ]
  • the first reference value D 1 is [fc ⁇ n]
  • the second reference value D 2 is [(fc/2) ⁇ n].
  • the pulse number set value per n seconds Ps is [Vp ⁇ n], and the value there of can be set per one unit in the range of [0 ⁇ Ps ⁇ (fc/2) ⁇ n ⁇ ].
  • n denotes the maximum cycle of the output pulse
  • Vp denotes a speed set value.
  • the pulse number set value per n seconds (hereinafter referred to as a “pulse number set value”) Ps becomes 0 ⁇ Ps ⁇ 16 MHz. Therefore, the speed set value Vp becomes 0 ⁇ Vp ⁇ 8 MHz.
  • the inverter 11 outputs a bit inversion value of the reference value D 1 in the 26-bit notation.
  • the data selector 12 When the S terminal is 0 ( ⁇ 1 ⁇ D 1 ), the data selector 12 outputs the pulse number set value Ps (26-bit notation) of a terminal A to a terminal Y, and when the S terminal is 1 ( ⁇ 1 ⁇ D 1 ), the data selector 12 outputs the bit inversion value of the reference value D 1 of a terminal B to the terminal Y.
  • the first data holding circuit 14 latches the addition result ⁇ 2 at the timing T 2 of the reference clock fb and the overflow prevention signal fob, and outputs data ⁇ 1 (26-bit notation).
  • the first data comparator 15 compares the output ⁇ 2 of the digital adder 13 and the first reference value D 1 .
  • the second data comparator 16 compares the output ⁇ 2 of the digital adder 13 and the second reference value D 2 .
  • the second data holding circuit 18 latches the judgment result fd at the timing T 2 of the reference clock fb, and outputs a pulse train fout.
  • the third data comparator 19 compares the output ⁇ 1 of the first data holding circuit 14 and the first reference value D 1 , and when ⁇ 1 ⁇ D 1 , outputs 0, and when ⁇ 1 ⁇ D 1 , outputs 1.
  • the overflow prevention circuit 20 receives the output of the third data comparator 19 at the timing T 1 of the reference clock fb, and outputs an overflow prevention signal fob.
  • FIG. 2 is a timing chart which shows the operation of the variable-frequency pulse generator in the first embodiment.
  • the speed change timing ⁇ t changes at a period synchronous with the timing T 1 of the reference clock fb and the speed change timing, and acceleration and deceleration speed is latched at the timing T 1 of the reference clock fb. This operation is executed by the part other than the configuration shown in FIG. 1.
  • the first data holding circuit 14 latches the output ⁇ 2 of the digital adder 103 at the timing T 2 of the reference clock fb.
  • the second data holding circuit 18 then latches the output fd of the pulse generation circuit 17 , and outputs the pulse train fout.
  • the above processing is repetitively executed at timings T 1 and T 2 of the reference clock fb.
  • FIG. 3 shows the output result of each section, when the variable-frequency pulse generator in the first embodiment is operated.
  • the reference clock fb is 32 MHz
  • the maximum cycle n of the output pulse is 2 seconds
  • the pulse number set value Ps is 8 ⁇ 16 MHz (that is, the speed set value Vp is set to 4 ⁇ 8 MHz). Therefore, the control clock frequency fc becomes 16 MHz, the first reference value D 1 becomes 32 M, and the second reference value D 2 becomes 16 M.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 1 ( ⁇ 1 >D 1 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the over flow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • FIG. 4 shows the output waveform of the variable-frequency pulse generator in the first embodiment.
  • the output pulse fout becomes also 4 MHz, and it is seen that the pulse is output as per the speed set value Vp.
  • the output pulse fout becomes also 8 MHz, and it is also seen that the pulse is output as per the speed set value Vp.
  • the output pulse changes corresponding to the change in the speed set value.
  • one cycle of the output control of the pulse train fout is changed from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock, by comparing the output ⁇ 2 of the digital adder 13 before being held by the first data holding circuit 14 , and the first reference value D 1 and the second reference value D 2 , respectively, by the first data comparator 15 and the second data comparator 16 .
  • the latch timing of the over flow signal is also changed from T 4 to T 1 of the reference clock fb, by comparing the output ⁇ 1 of the first data holding circuit 14 and the first reference value D 1 by the third data comparator 19 .
  • FIG. 5 shows the configuration of a second embodiment of the variable-frequency pulse generator according to the present invention.
  • the reference symbol 1 b denotes a variable-frequency pulse generation circuit in the second embodiment
  • 21 denotes a digital adder which adds the output ⁇ 1 of a first data holding circuit 24 described later and the pulse number set value Ps
  • 22 denotes a digital subtracter which subtracts a first reference value D 1 from the output ⁇ 2 of the digital adder 21 .
  • the reference symbol 23 denotes a data selector which selects either one of the output of the output ⁇ 2 of the digital adder 21 and the output ⁇ 3 of the digital subtracter 22
  • 24 denotes a first data holding circuit which latches the output of the data selector 23 at the timing T 2 of the reference clock fb
  • 25 denotes a first data comparator which compares the output ⁇ 2 of the digital adder 21 and the first reference value D 1
  • 26 denotes a second data comparator which compares the output ⁇ 2 of the digital adder 21 and the second reference value D 2 .
  • the reference symbol 27 denotes a pulse generation circuit which judges the output level (High or Low) based on the two comparison results
  • 28 denotes a second data holding circuit which latches the output fd of the pulse generation circuit 27 at the timing T 2 of the reference clock fb and outputs a pulse train fout.
  • the control clock frequency fc is [fb/2 ].
  • the first reference value D 1 is [fc ⁇ n]
  • the second reference value D 2 is [(fc/2) ⁇ n].
  • the pulse number set value per n seconds Ps is [Vp ⁇ n], and the value thereof can be set per one unit in the range of [0 ⁇ Ps ⁇ (fc/2) ⁇ n ⁇ ].
  • n denotes the maximum cycle of the output pulse
  • Vp denotes a speed set value.
  • the pulse number set value per n seconds (hereinafter referred to as a “pulse number set value”) Ps becomes 0 ⁇ Ps ⁇ 16 MHz. Therefore, the speed set value Vp becomes 0 ⁇ Vp ⁇ 8 MHz.
  • the digital adder 21 adds the pulse number set value Ps (26-bit notation) and the output ⁇ 1 of the first data holding circuit 24 (26-bit notation), and outputs the addition result ⁇ 2 (26-bit notation) However, 0 ⁇ 2 ⁇ ((fc/2) ⁇ n+fc ⁇ n)
  • the digital subtracter 22 subtracts the first reference value D 1 from the output ⁇ 2 of the digital adder 21 , and outputs the subtraction result ⁇ 3 (26-bit notation) However, ⁇ (fc ⁇ n) ⁇ 3 ⁇ ((fc/2) ⁇ n).
  • the data selector 23 When the S terminal is 1 ⁇ ( ⁇ 2 ⁇ D 1 ), the data selector 23 outputs the data ⁇ 2 of the terminal B to the terminal Y, and when the S terminal is 0 ( ⁇ 2 ⁇ D 1 ), the data selector 23 outputs the data ⁇ 3 of the terminal A to the terminal Y.
  • the first data holding circuit 24 latches the output of the data selector 23 at the timing T 2 of the reference clock fb, and outputs data ⁇ 1 (26-bit notation) However, 0 ⁇ 1 ⁇ (fc ⁇ n).
  • the first data comparator 25 compares the output ⁇ 2 of the digital adder 21 and the first reference value D 1 .
  • the second data comparator 26 compares the output ⁇ 2 of the digital adder 13 and the second reference value D 2 .
  • the second data holding circuit 28 latches the judgment result fd at the timing T 2 of the reference clock fb, and outputs a pulse train fout.
  • FIG. 6 is a timing chart which shows the operation of the variable-frequency pulse generator in the second embodiment.
  • the speed change timing ⁇ t changes at a period synchronous with the timing T 1 of the reference clock fb and the speed change timing, and acceleration and deceleration speed is latched at the timing T 1 of the reference clock fb. This operation is executed by the part other than the configuration shown in FIG. 5.
  • the first data holding circuit 24 latches the output of the data selector 23 at the timing T 2 of the reference clock fb.
  • the second data holding circuit 28 then latches the output fd of the pulse generation circuit 27 , and outputs the pulse train fout.
  • FIG. 7 shows the output result of each section, when the variable-frequency pulse generator in the second embodiment is operated.
  • the reference clock fb is 32 MHz
  • the maximum cycle n of the output pulse is 2 seconds
  • the pulse number set value Ps is 8 ⁇ 16 MHz (that is, the speed set value Vp is set to 4 ⁇ 8 MHz). Therefore, the control clock frequency fc becomes 16 MHz, the first reference value D 1 becomes 32 M, and the second reference value D 2 becomes 16 M.
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 3 .
  • the output Pin of the data selector 23 becomes ⁇ 3 .
  • the output Pin of the data selector 23 becomes ⁇ 2 .
  • the output Pin of the data selector 23 becomes ⁇ 3 .
  • one cycle of the output control of the pulse train fout is changed from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock, by comparing the output ⁇ 2 of the digital adder 21 before being held by the first data holding circuit 24 , and the first reference value D 1 and the second reference value D 2 , respectively, by the first data comparator 25 and the second data comparator 26 .
  • the digital subtracter 22 further subtracts the first reference value D 1 from the output ⁇ 2 of the digital adder 21 , and when the comparison result by the first data comparator 25 satisfies ⁇ 2 ⁇ D 1 , the data selector 23 selects and outputs ⁇ 3 , being the subtraction result, to thereby prevent the overflow of the digital adder 21 .
  • the control cycle can be reduced, and the noise, power consumption and heat generation can be reduced, compared to the conventional art.
  • FIG. 8 shows the configuration of a third embodiment of the variable-frequency pulse generator according to the present invention.
  • the same configuration as that of the first embodiment described above is denoted by the same reference symbol, and the explanation thereof is omitted. Only the operation different from that of the first embodiment will be explained herein.
  • the reference symbol 1 c is a variable-frequency pulse generation circuit in the third embodiment
  • 17 c is a pulse generation circuit which judges the output level (High or Low) based on the comparison result of the second data comparator 16 .
  • the control clock frequency fc is [fb/2 ]
  • the second reference value D 2 is [(fc/2) ⁇ n].
  • the reference clock frequency fb is 32 MHz
  • the maximum cycle n of the output pulse is 2 seconds.
  • the inverter 11 outputs a bit inversion value of the reference value D 2 in the 25-bit notation.
  • the data selector 12 When the S terminal is 0 ( ⁇ 1 ⁇ D 1 ), the data selector 12 outputs the pulse number set value Ps (25-bit notation) of the terminal A to the terminal Y, and when the S terminal is 1 ( ⁇ 1 ⁇ D 2 ), the data selector 12 outputs the bit inversion value of the reference value D 2 of the terminal B to the terminal Y.
  • the first data holding circuit 14 latches the addition result ⁇ 2 at the timing T 2 of the reference clock fb and the overflow prevention signal fob, and outputs data ⁇ 1 (25-bit notation)
  • the second data comparator 16 compares the output ⁇ 2 of the digital adder 13 and the second reference value D 2 .
  • the second data holding circuit 18 latches the judgment result fd at the timing T 2 of the reference clock fb, and outputs a pulse train fout.
  • the third data comparator 19 compares the output ⁇ 1 of the first data holding circuit 14 and the second reference value D 2 , and when ⁇ 1 ⁇ D 2 , outputs 0, and when ⁇ 1 ⁇ D 2 , outputs 1.
  • the overflow prevention circuit 20 receives the output of the third data comparator 19 at the timing T 1 of the reference clock fb, and outputs an overflow prevention signal fob.
  • the latch timing of the variable-frequency pulse generator in the third embodiment is the same as that shown in FIG. 2 explained above, and hence the explanation thereof is omitted.
  • FIG. 9 shows the output result of each section, when the variable-frequency pulse generator in the third embodiment is operated. It is assumed that the reference clock fb is 32 MHz, the maximum cycle n of the output pulse is 2 seconds, and the pulse number set value Ps is 8 ⁇ 16 MHz (that is, the speed set value Vp is set to 4 ⁇ 8 MHz). Therefore, the control clock frequency fc becomes 16 MHz, and the second reference value D 2 becomes 16 M.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 1 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 1 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 0 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • the third data comparator 19 outputs 1 ( ⁇ 1 ⁇ D 2 ) as the overflow signal.
  • one cycle of the output control of the pulse train fout is changed from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock, by comparing the output ⁇ 2 of the digital adder 13 before being held by the first data holding circuit 14 , and the second reference value D 2 , respectively, by the second data comparator 16 .
  • the latch timing of the overflow signal is also changed from T 4 to T 1 of the reference clock fb, by comparing the output ⁇ 1 of the first data holding circuit 14 and the second reference value D 2 by the third data comparator 19 .
  • the third embodiment it is judged whether the overflow frequency is an even number of times or an odd number of times, and the pulses are generated based on the judgment result and the comparison result by the second data comparator 16 . Thereby, the number of gates can be reduced than that in the first embodiment.
  • FIG. 10 shows the configuration of a fourth embodiment of the variable-frequency pulse generator according to the present invention.
  • the same configuration as that of the first embodiment described above is denoted by the same reference symbol, and the explanation thereof is omitted. Only the operation different from that of the first embodiment will be explained herein.
  • the reference symbol 1 d is a variable-frequency pulse generation circuit in the third embodiment
  • 17 d is a pulse generation circuit which judges the output level (High or Low) based on the comparison result of the two data comparators
  • 19 d is a third data comparator which compares the output ⁇ 1 of the first data holding circuit 14 and the first reference value D 1 .
  • the reference clock frequency fb is 32 MHz
  • the maximum cycle n of the output pulse is 2 seconds.
  • variable-frequency pulse generator in the fourth embodiment will be explained.
  • the data selector 12 When the S terminal is 0 ( ⁇ 1 ⁇ D 1 ), the data selector 12 outputs the pulse number set value Ps (26-bit notation) of the terminal A to the terminal Y, and when the S terminal is 1 ( ⁇ 1 >D 1 ), the data selector 12 outputs the bit inversion value of the reference value D 1 of the terminal B to the terminal Y.
  • the third data comparator 19 d compares the output ⁇ 1 of the first data holding circuit 14 and the first reference value D 1 , and when ⁇ 1 ⁇ D 1 , outputs 0, and when ⁇ 1 >D 1 , outputs 1.
  • the latch timing of the variable-frequency pulse generator in the fourth embodiment is the same as that shown in FIG. 2 explained above, and hence the explanation thereof is omitted.
  • FIG. 11 shows the output result of each section, when the variable-frequency pulse generator in the fourth embodiment is operated. It is assumed herein that the reference clock fb is 32 MHz, the maximum cycle n of the output pulse is 2 seconds, and the pulse number set value Ps is 8 ⁇ 16 MHz (that is, the speed set value Vp is set to 4 ⁇ 8 MHz). Therefore, the control clock frequency fc becomes 16 MHz, and the first reference value D 1 becomes 32 MHz, and the second reference value D 2 becomes 16 MHz.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 0 ( ⁇ 1 ⁇ D 1 ) as the overflow signal.
  • the third data comparator 19 d outputs 1 ( ⁇ 1 >D 1 ) as the overflow signal.
  • one cycle of the output control of the pulse train fout is changed from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock, by comparing the output ⁇ 2 of the digital adder 13 before being held by the first data holding circuit 14 , the first reference value D 1 and the second reference value D 2 , respectively, by the first data comparator 15 and the second data comparator 16 .
  • the latch timing of the over flow signal is also changed from T 4 to T 1 of the reference clock fb.
  • the output of the addition unit before being held by the data holding unit, the first reference value and the second reference value are compared, respectively, by the first comparison unit and the second comparison unit, to thereby change one cycle of the output control of the pulse train from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock. Further, by comparing the output of the data holding unit and the first reference value by the third comparison unit, the latch timing of the overflow signal is changed from the fourth cycle (T 4 ) to the first cycle (T 1 ). Thereby, the control cycle can be reduced, and hence there is the effect that the noise, power consumption and heat generation can be reduced, compared to the conventional art.
  • the output of the addition unit before being held by the data holding unit, the first reference value and the second reference value are compared, respectively, by the first comparison unit and the second comparison unit, to thereby change one cycle of the output control of the pulse train from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock.
  • the selection unit prevents the overflow of the addition unit by selecting/outputting the subtraction result.
  • the output of the addition unit before being held by the data holding unit, the first reference value and the second reference value are compared, respectively, by the first comparison unit and the second comparison unit, to thereby change one cycle of the output control of the pulse train from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock. Further, by comparing the output of the data holding unit and the first reference value by the third comparison unit, the latch timing of the overflow signal is changed from the fourth cycle (T 4 ) to the first cycle (T 1 ). Thereby, the control cycle can be reduced, and hence there is the effect that the noise, power consumption and heat generation can be reduced, compared to the conventional art.
  • variable-frequency pulse generator is useful for a variable-frequency pulse generator which generates a pulse train of a desired frequency, and particularly useful for all apparatus which uses a variable-frequency pulse generator in which the noise, power consumption and heat generation within the apparatus considerably increase due to speed-up of the reference block.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Inverter Devices (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
US10/203,405 2001-01-17 2001-12-17 Variable-frequency pulse generator Abandoned US20030034809A1 (en)

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JP2001-009523 2001-01-17

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110161719A1 (en) * 2009-12-31 2011-06-30 Industrial Technology Research Institute Processing devices
US20120166856A1 (en) * 2010-12-28 2012-06-28 Stmicroelectronics Pvt. Ltd. Signal synchronizing systems and methods
US9643227B2 (en) 2014-05-29 2017-05-09 M.E.P. Macchine Elettonriche Piegatrici Spa Drawing unit and corresponding method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432065A (en) * 1979-12-21 1984-02-14 Siemens Aktiengesellschaft Method and apparatus for generating a pulse train with variable frequency
US5870238A (en) * 1995-12-15 1999-02-09 Samsung Electronics Co., Ltd. Switching offset value as need to improve sector pulse generation for a hard disk drive

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JPS60187123A (ja) * 1984-03-07 1985-09-24 Fuji Electric Co Ltd 可変周波数パルス発生装置
JPH077904B2 (ja) 1987-09-14 1995-01-30 三菱電機株式会社 パルス発生回路
JPH09261015A (ja) * 1996-03-19 1997-10-03 Japan Radio Co Ltd 周波数可変のパルス波形発生回路
JPH1073812A (ja) * 1996-09-02 1998-03-17 Dainippon Printing Co Ltd ホログラムカラーフィルターを用いた液晶表示装置
JP3551002B2 (ja) * 1998-01-30 2004-08-04 三菱電機株式会社 可変周波数パルス発生装置
JP3237622B2 (ja) 1998-08-27 2001-12-10 日本電気株式会社 携帯端末装置のストラップ構造
JP2000278048A (ja) * 1999-03-24 2000-10-06 Nippon Telegr & Teleph Corp <Ntt> 周波数シンセサイザ

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432065A (en) * 1979-12-21 1984-02-14 Siemens Aktiengesellschaft Method and apparatus for generating a pulse train with variable frequency
US5870238A (en) * 1995-12-15 1999-02-09 Samsung Electronics Co., Ltd. Switching offset value as need to improve sector pulse generation for a hard disk drive

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110161719A1 (en) * 2009-12-31 2011-06-30 Industrial Technology Research Institute Processing devices
US8499188B2 (en) * 2009-12-31 2013-07-30 Industrial Technology Research Institute Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal
US20120166856A1 (en) * 2010-12-28 2012-06-28 Stmicroelectronics Pvt. Ltd. Signal synchronizing systems and methods
US9225321B2 (en) * 2010-12-28 2015-12-29 Stmicroelectronics International N.V. Signal synchronizing systems and methods
US9643227B2 (en) 2014-05-29 2017-05-09 M.E.P. Macchine Elettonriche Piegatrici Spa Drawing unit and corresponding method

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JP3660595B2 (ja) 2005-06-15
US20040164774A1 (en) 2004-08-26
DE10195741B3 (de) 2013-06-13
DE10195741T1 (de) 2003-11-06
JP2002217690A (ja) 2002-08-02
KR20020086648A (ko) 2002-11-18
US6822492B2 (en) 2004-11-23
WO2002058238A1 (fr) 2002-07-25
KR100493607B1 (ko) 2005-06-10

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