US20020180011A1 - Lead frame, semiconductor device using the same and method of producing the semiconductor device - Google Patents

Lead frame, semiconductor device using the same and method of producing the semiconductor device Download PDF

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Publication number
US20020180011A1
US20020180011A1 US10/156,812 US15681202A US2002180011A1 US 20020180011 A1 US20020180011 A1 US 20020180011A1 US 15681202 A US15681202 A US 15681202A US 2002180011 A1 US2002180011 A1 US 2002180011A1
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United States
Prior art keywords
lead frame
portions
semiconductor device
pair
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/156,812
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English (en)
Inventor
Takekazu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TANAKA, TAKEKAZU
Publication of US20020180011A1 publication Critical patent/US20020180011A1/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Priority to US10/936,795 priority Critical patent/US7189599B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/4805—Shape
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    • H01L2224/491—Disposition
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    • Y10S438/00—Semiconductor device manufacturing: process
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Definitions

  • a method of producing a semiconductor device for causing the surface of a lead frame to partly appear on the bottom of the semiconductor device begins with a step of mounting a semiconductor chip to an island portion included in the lead frame. Electrodes formed on the surface of the semiconductor chip and an electrode portion are connected by bonding wires. Part of the top and part of the bottom of the lead frame, which include the island portion, semiconductor chip, electrode portion and bonding wire, are sealed with seal resin. Subsequently, the entire surface of the seal resin beneath the lead frame is ground in parallel to the bottom of the lead frame. Finally, part of the bottom of the lead frame is caused to appear on the bottom of the seal resin.
  • the lead frame 1 positioned on the resin sheet 6 is sealed by the seal resin 3 together with the semiconductor chip 2 .
  • the resin sheet 6 prevents the seal resin 3 from leaking to the bottoms of the external electrodes 4 .
  • the resin sheet 6 is peeled off the package.
  • the bottom of the packages is plated except for the portions where the external electrodes 4 protrude downward. This is followed by dicing the seal resin 3 and lead frame 1 to thereby complete the semiconductor device 5 .
  • the resin sheet 6 protects the external electrodes 4 during the production of the semiconductor device 5 , as stated above. More specifically, when the lead frame 1 loaded with the semiconductor chip 2 is sealed with the seal resin 3 , the resin sheet 6 prevents the resin 3 from leaking to thereby insure the plating step. However, the resin sheet 6 is expensive and increases the production cost of the semiconductor device 5 .
  • the lead frame includes a pair of base portions 11 and two island portions 13 extending over both of the two base portions 11 .
  • the lead frame 1 is formed of metal.
  • Electrode portions 12 are formed on the base portions 11 . More specifically, the electrode portions 12 and island portions 13 should preferably be formed on the tops of the base portions 11 integrally with the base portions 11 .
  • FIGS. 11C and 11D indicate, the procedure described above provides the portions where only the seal resin 3 is present with margins, compared the portions where the external electrodes 4 are present. It is therefore possible to provide the package with any desired size on the basis of, e.g., the full-cut dicing positions. If the full-cut dicing width of the seal resin 3 is smaller than the half-cut dicing width of the lead frame 1 , then part of the lead frame 1 can appear on the side of the resulting semiconductor device; if the former width is the same as the latter width, then part of the lead frame 1 can appear on the side of the semiconductor device.
  • the base portions each consist of a portion on which the electrode portion are formed, a portion on which an island portion is formed, and a portion connecting them together. Such connecting portions insure a positional relation between the bottoms of the electrode portions and those of the island portions.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US10/156,812 2001-05-30 2002-05-30 Lead frame, semiconductor device using the same and method of producing the semiconductor device Abandoned US20020180011A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/936,795 US7189599B2 (en) 2001-05-30 2004-09-09 Lead frame, semiconductor device using the same and method of producing the semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-163268 2001-05-30
JP2001163268A JP4611569B2 (ja) 2001-05-30 2001-05-30 リードフレーム及び半導体装置の製造方法

Related Child Applications (1)

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US10/936,795 Division US7189599B2 (en) 2001-05-30 2004-09-09 Lead frame, semiconductor device using the same and method of producing the semiconductor device

Publications (1)

Publication Number Publication Date
US20020180011A1 true US20020180011A1 (en) 2002-12-05

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US10/156,812 Abandoned US20020180011A1 (en) 2001-05-30 2002-05-30 Lead frame, semiconductor device using the same and method of producing the semiconductor device
US10/936,795 Expired - Fee Related US7189599B2 (en) 2001-05-30 2004-09-09 Lead frame, semiconductor device using the same and method of producing the semiconductor device

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US (2) US20020180011A1 (ko)
JP (1) JP4611569B2 (ko)
KR (1) KR100491657B1 (ko)
TW (1) TW543173B (ko)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050032271A1 (en) * 2001-05-30 2005-02-10 Nec Electronics Corporation Lead frame, semiconductor device using the same and method of producing the semiconductor device
US20070134845A1 (en) * 2002-07-02 2007-06-14 Nec Electronics Corporation Method of forming molded resin semiconductor device
US20070298544A1 (en) * 2006-06-21 2007-12-27 Oman Todd P Manufacturing method for a leadless multi-chip electronic module
US20130228930A1 (en) * 2012-03-02 2013-09-05 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
CN104465589A (zh) * 2013-09-12 2015-03-25 株式会社东芝 半导体装置及其制造方法
US11562947B2 (en) * 2020-07-06 2023-01-24 Panjit International Inc. Semiconductor package having a conductive pad with an anchor flange

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030093774A (ko) * 2002-06-05 2003-12-11 광전자 주식회사 리드프레임, 상기 리드프레임을 이용한 칩 스케일 반도체패키지 및 그 제조방법
US7507603B1 (en) * 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US8034402B2 (en) * 2007-07-27 2011-10-11 Ngk Insulators, Ltd. Method for producing ceramic compact and ceramic part

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163069A (en) * 1997-10-09 2000-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having pads for connecting a semiconducting element to a mother board
US6528879B2 (en) * 2000-09-20 2003-03-04 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US20030160339A1 (en) * 2002-02-27 2003-08-28 Nec Electronics Corporation Electronic component and fabrication method thereof

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KR20020091797A (ko) 2002-12-06
KR100491657B1 (ko) 2005-05-27

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