US20010043121A1 - Semiconductor circuit with a stabilized gain slope - Google Patents

Semiconductor circuit with a stabilized gain slope Download PDF

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Publication number
US20010043121A1
US20010043121A1 US09/195,620 US19562098D US2001043121A1 US 20010043121 A1 US20010043121 A1 US 20010043121A1 US 19562098 D US19562098 D US 19562098D US 2001043121 A1 US2001043121 A1 US 2001043121A1
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Prior art keywords
circuit
capacitor
constituted
resonant circuit
semiconductor circuit
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Granted
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US09/195,620
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US6313706B1 (en
Inventor
Yuji Kakuta
Yoshiaki Fukasawa
Yuichi Taguchi
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Renesas Electronics Corp
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NEC Corp
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Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUKASAWA, YOSHIAKI, KAKUTA, YUJI, TAGUCHI, YUICHI
Publication of US20010043121A1 publication Critical patent/US20010043121A1/en
Assigned to NEC COMPOUND SEMICONDUCTOR DEVICES, LTD. reassignment NEC COMPOUND SEMICONDUCTOR DEVICES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF ADDRESS Assignors: RENESAS ELECTRONICS CORPORATION
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/191—Tuned amplifiers

Definitions

  • the present invention relates to a semiconductor circuit, and particularly to a semiconductor circuit used in CATV (CAble TeleVision) hybrid IC (HIC).
  • CATV CAble TeleVision
  • HIC hybrid IC
  • HIC hybrid IC
  • a plurality of stages of amplifiers are connected in series via coaxial cable, and a desired gain slope must be established across the entire employed frequency band to correct for characteristic lost in the coaxial cable.
  • Gain slope is such that gain increases with higher frequencies within the bandwidth.
  • FIG. 1 and FIG. 2 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open application No. 85810/83.
  • a parallel resonant circuit is formed by inductor L 101 , which is provided in a bias feedback circuit, and capacitor C 102 , which is provided between the base and emitter of transistor Tr 101 .
  • damping resistor R 106 connected in a series with capacitor C 102 between the base and emitter of transistor Tr 101 is provided to control Q in the resonant circuit.
  • the resonance frequency is altered by changing the element constants of inductor L 101 and capacitor C 102 , thereby regulating the peaking frequency.
  • FIG. 3 and FIG. 4 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.
  • a serial resonant circuit is formed by capacitor C 112 and inductor L 111 in an interstage circuit provided between two amplifier circuits, and in the circuit shown in FIG. 4, FET(Field Effect Transistor) Tr 113 is provided such that inductor L 111 is connected in parallel between the source and drain, and a parallel resonant circuit is formed by inductor L 111 and the capacitance between the source and drain of FET Tr 113 .
  • alteration of resonance frequency is realized by changing the gate bias to vary the capacitance between the source and drain of FET Tr 113 , thereby regulating peaking frequency.
  • resonance frequency is altered by changing the element constants of inductor L 101 and capacitor C 102 to regulate the peaking frequency, but the impedance on the input side and output side change according to the amount of peaking because inductor L 101 and capacitor C 102 are provided in the feedback circuit.
  • the resulting circuit therefore has the three factors of input and output impedance and gain slope, and design and adjustment consequently require considerable time and trouble.
  • capacitor C 111 and inductor L 111 between active elements must also be changed to alter the resonance frequency, and mismatching between elements having gain tends to cause problems in characteristics such as oscillation and instability.
  • the object of the present invention is to provide a semiconductor circuit that can realize a stable gain slope without increasing the circuit scale or necessitating extra time for correcting impedance.
  • a resonant circuit is provided outside a feedback loop for effecting peaking at a particular frequency and for realizing a gain slope having a desired inclination, for example, an inclination of 1 dB or more.
  • a desired inclination for example, an inclination of 1 dB or more.
  • the invention does not entail enlargement of circuit scale because additional active elements are not necessary.
  • FIG. 1 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open No. 85810/83.
  • FIG. 2 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open No. 85810/83.
  • FIG. 3 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.
  • FIG. 4 is a circuit diagram showing the configuration of a circuit for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.
  • FIG. 5 is a circuit diagram showing a semiconductor circuit according to the first embodiment of the present invention.
  • FIG. 6 shows one example of the configuration of chip inductance that including a capacitance component.
  • FIG. 7 is an equivalent circuit diagram of the chip inductance shown in FIG. 6.
  • FIG. 8 shows the gain characteristic with respect to frequency for a case in which a resonant circuit is not applied in the circuit shown in FIG. 5.
  • FIG. 9 shows the gain characteristic with respect to frequency in the circuit shown in FIG. 5.
  • FIG. 10 is a circuit diagram showing a semiconductor circuit according to the second embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing a semiconductor circuit according to the third embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing a semiconductor circuit according to the fourth embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing a semiconductor circuit according to the fifth embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a semiconductor circuit according to the first embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.
  • this embodiment is made up of FET Q 1 having its gate terminal connected to the input terminal and its source terminal connected to ground; resistor R 1 and capacitor C 1 connected in a series between the drain terminal and gate terminal of FET Q 1 ; and capacitor C 2 and inductor L 1 connected in parallel between the output terminal and the drain terminal of FET Q 1 ; wherein a feedback loop is formed by FET Q 1 , resistor R 1 , and capacitor C 1 . This feedback loop is provided for maintaining the band and impedance.
  • this embodiment can reduce the time and trouble required in designing and adjusting as compared with the circuits shown in FIG. 1 and FIG. 2 in which impedance changes on both the input side and output side.
  • This invention can also dispense with the need for variable bias for altering the gate bias of the FET shown in FIG. 3 and FIG. 4, because the resonance frequency is modified by simply altering the constants of elements. As a result, a slope can be imposed on gain without increasing circuit scale. In addition, oscillation resulting from mismatching of impedance does not occur because the alteration of element constants does not take place in interstage elements.
  • inductor L 1 and capacitor C 2 are connected in parallel in this embodiment, peaking can be similarly effected if these elements are connected in a series.
  • the resonant circuit composed of inductor L 1 and capacitor C 2 can also be constituted only by chip inductance that includes a capacitance component.
  • FIG. 6 shows an example of the configuration of chip inductance including a capacitance component
  • FIG. 7 is an equivalent circuit diagram of the chip inductance shown in FIG. 6.
  • the chip inductance of this example includes internal conductors that constitute the L component that are linked in a number of layers in a helical spring form in a ceramic unit with the portions that constitute the C component interposed between the conductors.
  • a resonant circuit including an L component and C component is thus formed as shown in FIG. 7.
  • FIG. 8 shows the gain characteristic with respect to frequency for a case in which a resonant circuit is not applied in the circuit shown in FIG. 5, and
  • FIG. 9 shows the gain characteristic with response to frequency in the circuit shown in FIG. 5.
  • the circuit shown in FIG. 5 realizes a gain slope having a desired inclination of, for example, 1 dB or more in a desired frequency band.
  • FIG. 10 is a circuit diagram showing a semiconductor circuit according to the second embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.
  • this embodiment is made up of: FET Q 1 having its gate terminal connected to the input terminal and its source terminal connected to ground; resistor R 1 and capacitor C 1 connected in a series between the drain terminal and gate terminal of FET Q 1 ; FET Q 2 having its gate terminal connected to the drain terminal of FET Q 1 and its source terminal connected to ground; resistor R 2 and capacitor C 3 connected in a series between the drain terminal and gate terminal of FET Q 2 ; and capacitor C 2 and inductor L 1 connected in parallel between the output terminal and the drain terminal of FET Q 2 ; wherein a first feedback loop is formed by FET Q 1 , resistor R 1 , and capacitor C 1 ; and a second feedback loop is formed by FET Q 2 , resistor R 2 , and capacitor C 3 .
  • the circuit generating resonance is provided outside the feedback loops, and as a result, only the output side impedance changes and the input side impedance does not change, as in the circuit described in the first embodiment. This construction allows a reduction of the time and trouble necessary for designing and adjusting the circuit.
  • FIG. 11 is a circuit diagram showing a semiconductor circuit according to the third embodiment of the present invention. This circuit is only the alternating-current portion of the semiconductor circuit of this invention.
  • the resonant circuit constituted by inductor L 1 and capacitor C 2 in this embodiment is provided outside the feedback loop constituted by FET Q 1 , resistor R 1 , and capacitor C 1 .
  • the feedback loop constituted by FET Q 1 , resistor R 1 , and capacitor C 1 As a result, only the output side impedance changes and the input side impedance undergoes no change, whereby the time and trouble required for design and adjustment can be reduced.
  • the feedback loop is constituted by FET Q 1 , resistor R 1 , and capacitor C 1 in this embodiment, the same effect can be obtained if the feedback is formed using FET Q 2 if the resonant circuit is provided outside the feedback loop.
  • FIG. 12 is a circuit diagram showing a semiconductor circuit according to the fourth embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing the semiconductor circuit according to the fifth embodiment of the present invention.
  • inputted signals in this embodiment are distributed into two differing signals, the two distributed signals are each amplified by amplifier circuit 12 and 13 , and the signals amplified by amplifiers 12 and 13 are then synthesized and outputted.
  • Transformer T 1 grounded by way of capacitors C 34 and C 35 is provided as a distributing means that distributes signals inputted by way of input terminal 1 into two signals of different phase
  • transformer T 2 that is grounded by way of capacitor C 37 is provided as a synthesizing means for synthesizing the two signals amplified by amplifiers 12 and 13 .
  • Amplifier circuit 12 is made up of: FETs Q 11 -Q 13 connected in multiple stages; thermistor Rt 11 and resistor R 13 connected together in parallel and provided as the gate resistance of FET Q 11 , the second FET; inductor L 13 provided between the gate terminal of FET Q 11 and a connection point between thermistor Rt 11 and resistor R 13 ; resistor R 11 , capacitor C 11 , and thermistor Rt 12 connected in a series between the gate terminal, i.e., the input of amplifier circuit 12 , and the drain terminal of FET Q 12 ; resistor R 12 and capacitor C 12 connected in a series between the drain terminal of FET Q 12 and a prescribed potential; capacitor C 13 connected between the drain terminal of FET Q 12 and the other connection point between thermistor Rt 11 and resistor R 13 ; inductor L 11 and resistor R 17 connected in a series between the drain terminal of FET Q 12 and the source terminal of FET Q 11 ; capacitor C 15 connected between the connection
  • Amplifier circuit 13 is made up of: FETs Q 21 -Q 23 connected in multiple stages; thermistor Rt 21 and resistor R 23 connected together in parallel and provided as the gate resistance of FET Q 21 , the second FET; inductor L 23 provided between the gate terminal of FET Q 21 and a connection point between thermistor Rt 21 and resistor R 23 ; resistor R 21 , capacitor C 21 , and thermistor Rt 22 connected in a series between the gate terminal, i.e., the input of amplifier circuit 13 , and the drain terminal of FET Q 22 ; resistor R 22 and capacitor C 22 connected in a series between the drain terminal of FET Q 22 and a prescribed potential; capacitor C 23 connected between the drain terminal of FET Q 22 and the other connection point between thermistor Rt 21 and resistor R 23 ; inductor L 21 and resistor R 27 connected in a series between the drain terminal of FET Q 22 and the source terminal of FET Q 21 ; capacitor C 25 connected between the connection
  • transformer T 1 On the input side of transformer T 1 are provided: capacitor C 33 and inductor L 31 connected in a series between transformer T 1 and input terminal 1 , capacitor C 31 and resistor R 31 connected in a series between the connection point between capacitor 33 and inductor L 31 and the prescribed potential, and capacitor C 32 connected between the connection point between capacitor 33 and inductor L 31 and the prescribed potential; and on the output side of transformer T 2 are provided: inductor L 32 and capacitor C 39 connected in a series between transformer T 2 and output terminal 2 , and capacitor C 38 connected between the connection point between inductor L 32 and capacitor C 39 and the prescribed potential.
  • resistor R 41 connected between the source terminal of FET Q 11 and the source terminal of FET Q 21
  • resistors R 39 and R 40 connected in a series between the gate terminal of FET Q 11 and the gate terminal of FET Q 21
  • resistors R 33 and R 34 connected in a series between the connection point between resistor R 39 and resistor R 40 and transformer T 1
  • resistor R 32 and thermistors Rt 31 and Rt 32 connected in a series between the connection point between resistor R 33 and transformer T 1 and the prescribed potential
  • resistor R 35 connected between the prescribed potential and the connection point between resistor R 34 and the connection point between resistors R 39 and R 40
  • resistor R 37 connected between the source terminal of FET Q 12 and the source terminal of FET Q 22
  • resistor R 36 connected between the source terminal of FET Q 12 and the prescribed potential
  • resistor R 38 connected between the source terminal of FET Q 22 and the prescribed potential
  • resistors R 42 and R 43 connected between transformer
  • Thermistors Rt 11 , Rt 21 , and Rt 31 are thermally sensitive resistance elements in which resistance changes with a negative temperature characteristic according to the ambient temperature
  • thermistors Rt 12 , Rt 13 , Rt 22 , Rt 23 , and Rt 32 are thermally sensitive resistance elements in which resistance changes with a positive temperature characteristic according to the ambient temperature.
  • impedance changes because the constants of elements that constitute the circuit are changed, but only the output side impedance changes and the input side impedance undergoes no change. Because the resonant circuit constituted by inductor L 12 and capacitor C 16 is provided outside the feedback loop that uses FETs Q 11 -Q 13 in amplifier circuit 12 and the resonant circuit constituted by inductor L 22 and capacitor C 26 is provided outside the feedback loop that uses FETs Q 21 -Q 23 in amplifier circuit 13 .
  • the embodiment therefore enables a reduction of time and trouble in design and adjustment.
  • modification of the resonant frequency by altering the element constants obviates the need for variable bias for altering the gate bias of the FET, whereby a slope can be set to gain without increasing the scale of the circuit. Further, oscillation due to mismatching of impedance does not occur because alteration of the element constants does not take place in interstage elements.
  • thermistors Rt 11 and Rt 21 having a negative temperature characteristic are provided as the gate resistance of FETs Q 11 and Q 21 , respectively.
  • amplifier circuit 12 fluctuations in gain characteristic with respect to ambient temperature in the gain slope that is generated in the resonant circuit constituted by inductor L 12 and capacitor C 16 are thus canceled out by fluctuations in the value of Q with respect to ambient temperature in the circuit constituted by capacitor C 13 , thermistor Rt 11 , and inductor L 13 , and the inclination of the gain slope outputted from amplifier circuit 12 is therefore uniform despite variations in the ambient temperature.
  • thermistors Rt 31 and Rt 32 are connected in a series between prescribed potential and the connection point between resistor R 33 and transformer T 1 .
  • the current in the vicinity of a prescribed temperature is therefore at a minimum, and the circuit current increases as the ambient temperature falls from the prescribed temperature and also increases as the ambient temperature rises from the prescribed temperature, thereby enabling prevention of deterioration of distortion characteristic due to change in temperature.
  • resistor R 43 having a resistance of 10-100 ⁇ is provided between resistor R 42 and the connection point between resistor R 16 and resistor R 26 , and capacitor C 40 is provided between the prescribed potential and the connection point between resistor R 42 and resistor R 43 , the circuit constants of these components being set according to termination conditions.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
US09/195,620 1997-11-27 1998-11-19 Semiconductor circuit with a stabilized gain slope Granted US20010043121A1 (en)

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JP326442/1997 1997-11-27
JP32644297 1997-11-27

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US09/195,620 Expired - Lifetime US6313706B1 (en) 1997-11-27 1998-11-19 Semiconductor circuit with a stabilized gain slope
US09/195,620 Granted US20010043121A1 (en) 1997-11-27 1998-11-19 Semiconductor circuit with a stabilized gain slope
US09/933,808 Expired - Fee Related US6388527B1 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope
US09/933,809 Expired - Fee Related US6501335B2 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope
US09/933,751 Expired - Fee Related US6476679B2 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope

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US09/933,808 Expired - Fee Related US6388527B1 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope
US09/933,809 Expired - Fee Related US6501335B2 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope
US09/933,751 Expired - Fee Related US6476679B2 (en) 1997-11-27 2001-08-22 Semiconductor circuit with a stabilized gain slope

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US (5) US6313706B1 (de)
EP (1) EP0920122A3 (de)
KR (1) KR100350756B1 (de)
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US20030002140A1 (en) * 1996-05-28 2003-01-02 Fujitsu Limited Multi-wavelength light amplifier
US20100272445A1 (en) * 1998-03-19 2010-10-28 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers

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JP2001118731A (ja) * 1999-10-19 2001-04-27 Murata Mfg Co Ltd チップ型複合電子部品およびその製造方法
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US6995613B2 (en) * 2003-07-30 2006-02-07 Tropian, Inc. Power distribution and biasing in RF switch-mode power amplifiers
KR100659555B1 (ko) * 2003-09-30 2006-12-19 이종석 증폭회로의 입출력신호 보호회로
DE10361714B4 (de) * 2003-12-30 2009-06-10 Infineon Technologies Ag Halbleiterbauelement
WO2006121650A2 (en) * 2005-04-29 2006-11-16 The Regents Of The University Of California Power amplifier with an output matching network
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US8970308B2 (en) * 2013-02-08 2015-03-03 Infineon Technologies Ag Input match network with RF bypass path
CN104377959B (zh) * 2013-08-16 2017-04-26 台达电子企业管理（上海）有限公司 功率转换器与稳定电压增益的方法
US11005433B2 (en) * 2018-02-12 2021-05-11 Georgia Tech Research Corporation Continuous-mode harmonically tuned power amplifier output networks and systems including same
CN110932670B (zh) * 2018-09-19 2023-06-20 雅特力科技(重庆)有限公司 振荡器电路以及相关的振荡器装置
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US20030002140A1 (en) * 1996-05-28 2003-01-02 Fujitsu Limited Multi-wavelength light amplifier
US20070165299A1 (en) * 1996-05-28 2007-07-19 Fujitsu Limited Multi-wavelength light amplifier
US7474459B2 (en) 1996-05-28 2009-01-06 Fujitsu Limited Multi-wavelength light amplifier
US20090225403A1 (en) * 1996-05-28 2009-09-10 Yasushi Sugaya Multi-wavelength light amplifier
US8004752B2 (en) 1996-05-28 2011-08-23 Fujitsu Limited Multi-wavelength light amplifier
US8320040B2 (en) 1996-05-28 2012-11-27 Fujitsu Limited Multi-wavelength light amplifier
US8699126B2 (en) 1996-05-28 2014-04-15 Fujitsu Limited Multi-wavelength light amplifier
US20100272445A1 (en) * 1998-03-19 2010-10-28 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers
US7924499B2 (en) 1998-03-19 2011-04-12 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers
US7969648B2 (en) 1998-03-19 2011-06-28 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers
US20110164309A1 (en) * 1998-03-19 2011-07-07 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers
US8547629B2 (en) 1998-03-19 2013-10-01 Fujitsu Limited Gain and signal level adjustments of cascaded optical amplifiers

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US6313706B1 (en) 2001-11-06
CN1219023A (zh) 1999-06-09
US6476679B2 (en) 2002-11-05
EP0920122A2 (de) 1999-06-02
US20020005761A1 (en) 2002-01-17
US20010052821A1 (en) 2001-12-20
EP0920122A3 (de) 2001-10-24
US6501335B2 (en) 2002-12-31
KR19990045609A (ko) 1999-06-25
CN1085439C (zh) 2002-05-22
US6388527B1 (en) 2002-05-14
KR100350756B1 (ko) 2002-11-18

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