TWI787172B - 用於半導體結構的支撐件 - Google Patents

用於半導體結構的支撐件 Download PDF

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Publication number
TWI787172B
TWI787172B TW106106332A TW106106332A TWI787172B TW I787172 B TWI787172 B TW I787172B TW 106106332 A TW106106332 A TW 106106332A TW 106106332 A TW106106332 A TW 106106332A TW I787172 B TWI787172 B TW I787172B
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TW
Taiwan
Prior art keywords
layer
support
carbon
semiconductor structure
base substrate
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TW106106332A
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English (en)
Chinese (zh)
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TW201742108A (zh
Inventor
克里斯多福 斐格
奧列格 科諾強克
卡山姆 阿拉薩德
加布里埃爾 費洛
維若尼克 蘇利耶
克里斯朵 維堤蘇
塔古依 伊高揚
Original Assignee
法商索泰克公司
里昂克羅德 貝爾那大學
法國國家科學研究中心
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Application filed by 法商索泰克公司, 里昂克羅德 貝爾那大學, 法國國家科學研究中心 filed Critical 法商索泰克公司
Publication of TW201742108A publication Critical patent/TW201742108A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3206—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3208—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H10P14/3252—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
  • Silicon Compounds (AREA)
  • Element Separation (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
TW106106332A 2016-02-26 2017-02-24 用於半導體結構的支撐件 TWI787172B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1651642 2016-02-26
FR1651642A FR3048306B1 (fr) 2016-02-26 2016-02-26 Support pour une structure semi-conductrice

Publications (2)

Publication Number Publication Date
TW201742108A TW201742108A (zh) 2017-12-01
TWI787172B true TWI787172B (zh) 2022-12-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW106106332A TWI787172B (zh) 2016-02-26 2017-02-24 用於半導體結構的支撐件

Country Status (9)

Country Link
US (1) US11251265B2 (https=)
EP (1) EP3420583B1 (https=)
JP (1) JP6981629B2 (https=)
KR (1) KR102687932B1 (https=)
CN (1) CN109155276B (https=)
FR (1) FR3048306B1 (https=)
SG (2) SG10201913216XA (https=)
TW (1) TWI787172B (https=)
WO (1) WO2017144821A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6619874B2 (ja) * 2016-04-05 2019-12-11 株式会社サイコックス 多結晶ＳｉＣ基板およびその製造方法
FR3068506B1 (fr) * 2017-06-30 2020-02-21 Soitec Procede pour preparer un support pour une structure semi-conductrice
US20210183691A1 (en) * 2018-07-05 2021-06-17 Soitec Substrate for an integrated radiofrequency device, and process for manufacturing same
FR3091011B1 (fr) * 2018-12-21 2022-08-05 Soitec Silicon On Insulator Substrat de type semi-conducteur sur isolant pour des applications radiofréquences
FR3104318B1 (fr) 2019-12-05 2023-03-03 Soitec Silicon On Insulator Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite
FR3110283B1 (fr) 2020-05-18 2022-04-15 Soitec Silicon On Insulator Procédé de fabrication d’un substrat semi-conducteur sur isolant pour applications radiofréquences
JP2021190660A (ja) * 2020-06-04 2021-12-13 株式会社Sumco 貼り合わせウェーハ用の支持基板
CN111979524B (zh) * 2020-08-19 2021-12-14 福建省晋华集成电路有限公司 一种多晶硅层形成方法、多晶硅层以及半导体结构
FR3116151A1 (fr) 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile
FR3117668B1 (fr) 2020-12-16 2022-12-23 Commissariat Energie Atomique Structure amelioree de substrat rf et procede de realisation
FR3134239B1 (fr) * 2022-03-30 2025-02-14 Soitec Silicon On Insulator Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
US20240030222A1 (en) * 2022-07-20 2024-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Trapping layer for a radio frequency die and methods of formation
JP2026511208A (ja) 2022-11-29 2026-04-10 ソイテック 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法
WO2024115410A1 (fr) 2022-11-29 2024-06-06 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes.
EP4627621A1 (fr) 2022-11-29 2025-10-08 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
FR3146020B1 (fr) 2023-02-20 2025-07-18 Soitec Silicon On Insulator Support comprenant une couche de piégeage de charges, substrat composite comprenant un tel support et procédé de fabrication associés

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US20130084689A1 (en) * 2010-12-24 2013-04-04 Io Semiconductor, Inc. Trap Rich Layer Formation Techniques for Semiconductor Devices
US20150115480A1 (en) * 2013-10-31 2015-04-30 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity soi wafers with charge trapping layers based on terminated si deposition

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JP2907128B2 (ja) * 1996-07-01 1999-06-21 日本電気株式会社 電界効果型トランジスタ及びその製造方法
US20070032040A1 (en) * 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
KR101436313B1 (ko) * 2007-07-04 2014-09-01 신에쯔 한도타이 가부시키가이샤 다층 실리콘 웨이퍼의 제작법
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
FR2973158B1 (fr) 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
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FR2999801B1 (fr) * 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
JP5978986B2 (ja) 2012-12-26 2016-08-24 信越半導体株式会社 高周波半導体装置及び高周波半導体装置の製造方法
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US20130084689A1 (en) * 2010-12-24 2013-04-04 Io Semiconductor, Inc. Trap Rich Layer Formation Techniques for Semiconductor Devices
US20150115480A1 (en) * 2013-10-31 2015-04-30 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity soi wafers with charge trapping layers based on terminated si deposition

Also Published As

Publication number Publication date
CN109155276B (zh) 2023-01-17
EP3420583B1 (fr) 2021-08-04
JP2019512870A (ja) 2019-05-16
KR20190013696A (ko) 2019-02-11
JP6981629B2 (ja) 2021-12-15
FR3048306B1 (fr) 2018-03-16
TW201742108A (zh) 2017-12-01
KR102687932B1 (ko) 2024-07-25
EP3420583A1 (fr) 2019-01-02
WO2017144821A1 (fr) 2017-08-31
SG10201913216XA (en) 2020-02-27
US11251265B2 (en) 2022-02-15
US20190058031A1 (en) 2019-02-21
CN109155276A (zh) 2019-01-04
SG11201807197PA (en) 2018-09-27
FR3048306A1 (fr) 2017-09-01

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