TWI782310B - Logic circuit, processing unit, electronic component, and electronic device - Google Patents

Abstract

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Description

Logic circuit, processing device, electronic component and electronic device

One embodiment of the present invention disclosed in this specification, drawings, and claims (hereinafter referred to as this specification, etc.) relates to a semiconductor device (for example, a sequential circuit, a hold circuit, a memory circuit, a logic circuit, etc.) , its driving method, its manufacturing method, and the like. One embodiment of the present invention is not limited to the illustrated technical field. For example, one embodiment of the present invention relates to a memory device, a processing device, an imaging device, a display device, a light emitting device, a power storage device, a driving method or a manufacturing method thereof.

In order to reduce the power consumption of semiconductor devices, circuits that do not need to work are stopped by using power gating or clock gating. A flip-flop (FF) is one of sequential circuits (memory circuits holding states) included in semiconductor devices in many cases. Therefore, by reducing the power consumption of the FF, the power consumption of the semiconductor device incorporating the FF can be reduced. In general FF, if the power is turned off, the state (data) held will be lost.

A hold circuit is proposed in which data can be held even when power is turned off by utilizing the extremely small off-state current characteristic of a transistor (hereinafter, sometimes referred to as an OS transistor) whose semiconductor region is formed of an oxide semiconductor. For example, Patent Documents 1 to 3 describe that by incorporating a holding circuit using an OS transistor in the FF, power gating of the FF can be performed. For example, Non-Patent Document 1 describes that power gating of a processor is performed by providing a holding circuit including OS transistors for FF and SRAM.

[Patent Document 1] Japanese Patent Application Publication No. 2012-257192 [Patent Document 2] Japanese Patent Application Publication No. 2013-9297 [Patent Document 3] Japanese Patent Application Publication No. 2013-175708

[Non-Patent Document 1] H.Tamura et al., "Embedded SRAM and Cortex-M0 Core with Backup Circuits Using a 60-nm Crystalline Oxide Semiconductor for Power Gating," IEEE COOL Chips XVII, Apr.2014.

One of the objects of one embodiment of the present invention is to provide a novel semiconductor device or a novel driving method of the semiconductor device. In addition, as one of the objects of one embodiment of the present invention, power gating, data retention without power supply, reduction of power consumption, miniaturization, and ease of design can be mentioned.

The description of multiple purposes does not interfere with the existence of each other's purposes. An embodiment of the present invention does not need to achieve all of the above objects. Objects other than the objects listed above are naturally understood from the description in this specification and the like, and may be objects of one embodiment of the present invention.

One embodiment of the present invention is a logic circuit, including: a first circuit; and a second circuit, wherein the first circuit includes a first input terminal to an nth input terminal and a first output terminal (n is an integer greater than 2) , the second circuit includes an n+1th input terminal, a first node, a first capacitor, and a first transistor to a third transistor, and the first circuit has a function of selecting any one of the first input terminal to the nth input terminal and from The function of the first output terminal outputting the same logic data as that of the selected input terminal, the capacitor is electrically connected to the first node, and the first transistor has the function of controlling the conduction between the n+1th input terminal and the first input terminal State function, the second transistor has the function of controlling the conduction state between the first output terminal and the first node, the third transistor has the function of controlling the conduction state between the first node and the first input terminal, the first A gate of the transistor is electrically connected to a gate of the second transistor, and the second transistor and the third transistor include a semiconductor region formed using an oxide semiconductor layer.

In the above aspect, the first capacitor and the first to third transistors may be stacked on the region where the first circuit is formed. In the above mode, the first transistor may also include a semiconductor region formed using an oxide semiconductor layer. In this case, the oxide semiconductor layers of the first to third transistors preferably include c-axis-aligned crystals.

In addition, in the logic circuit according to the above method, the first circuit includes a selection circuit and a first logic circuit, the first logic circuit includes an n+2th input terminal and a first output terminal, and the first logic circuit has The output terminal outputs the same logic data as the n+2th input terminal, the selection circuit includes a second output terminal, and the selection circuit has the function of electrically connecting any one of the first input terminal to the nth input terminal to the second output terminal function, and the second output terminal is electrically connected to the n+2th input terminal.

According to one embodiment of the present invention, a novel semiconductor device or a novel method of operating a semiconductor device can be provided. In addition, according to an embodiment of the present invention, it is possible to realize: power gating; data retention without power supply; power consumption reduction; miniaturization; and easy design.

The description of multiple effects does not prevent the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all the above-mentioned effects. In one embodiment of the present invention, objects, effects, and novel features other than those described above can be naturally understood from the description and drawings in this specification.

In this specification and the like, a semiconductor device refers to a device using semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, etc.), a device including the circuit, and the like. In addition, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit and a wafer provided with an integrated circuit are examples of semiconductor devices. In addition, a memory device, a display device, a light emitting device, a lighting device, an electronic device, and the like are semiconductor devices themselves, or sometimes include a semiconductor device.

For example, in this specification and the like, when it is clearly described as "X and Y are connected", the following cases are disclosed in this specification and the like: the case where X and Y are electrically connected; the case where X and Y are functionally connected; and The case where X is directly connected to Y. Therefore, it is not limited to a predetermined connection relationship such as the connection relationship shown in the drawings or the text, and a connection relationship other than the connection relationship shown in the drawings or the text is also described in the drawings or the text. Both X and Y are objects (eg, devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

A transistor includes three terminals of a gate, a source, and a drain. The gate is a node that serves as a control node that controls the conduction state of the transistor. Of the two input-output nodes functioning as a source or a drain, one terminal is used as a source and the other terminal is used as a drain depending on the type of transistor or the potential level supplied to each terminal. Therefore, in this specification and the like, "source" and "drain" may be interchanged with each other. In addition, in this specification etc., two terminals other than a gate may be referred to as a 1st terminal and a 2nd terminal.

A node may be called a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. according to the circuit structure or device structure. In addition, a terminal, wiring, etc. may be called instead a node.

Voltage mostly refers to the potential difference between a certain potential and a reference potential such as ground potential (GND) or source potential. Therefore, the voltage can be renamed as the potential. Potential is relative. Therefore, even if it is described as "ground potential", it does not necessarily mean 0V.

In this specification and the like, "film" and "layer" may be interchanged with each other depending on the situation or situation. For example, "conductive layer" may be replaced with "conductive film" in some cases. Sometimes "insulating film" can be replaced with "insulating layer".

In this specification, etc., ordinal numerals such as "first", "second", and "third" are sometimes attached in order to avoid confusion of constituent elements. limited and added.

In this specification and the like, for example, the clock signal CLK is sometimes omitted and described as "signal CLK", "CLK", and the like. The same applies to other components (for example, signals, voltages, potentials, circuits, elements, electrodes, wiring, etc.).

In the drawings, sizes, layer thicknesses, or regions are sometimes exaggerated for easy understanding. Therefore, the present invention is not necessarily limited to this scale. In addition, in the drawings, ideal examples are schematically shown, and are not limited to shapes, numerical values, and the like shown in the drawings. For example, it may include signal, voltage or current deviation caused by noise or timing deviation.

In this specification, for the sake of convenience, words and phrases such as "upper" and "lower" may be used to describe the positional relationship of components with reference to the drawings. In addition, the positional relationship of the constituent elements changes appropriately according to the direction in which each constituent element is described. Therefore, it is not limited to the words and sentences described in this specification, and the words and sentences may be appropriately replaced according to circumstances.

The positional relationship of each circuit block in the block diagram described in the drawings is specified for the convenience of explanation. Even if the block diagram shows that different circuit blocks have different functions, sometimes the actual circuit blocks are also set as one circuit block. Different functions are implemented in the block. In addition, the function of each circuit block is specified for convenience of explanation, and even if the case where processing is performed by one circuit block is shown, this process may be performed by a plurality of circuit blocks in an actual circuit block.

Embodiments of the present invention are shown below. Note that the embodiments described in this specification can be combined as appropriate. In addition, when a plurality of structural examples (including working examples, manufacturing method examples) are shown in one embodiment, the structural examples may be combined appropriately. In addition, the present invention can be implemented in many different ways, and those skilled in the art can easily understand the fact that the ways and details can be changed into various forms without departing from the spirit and scope. form. Therefore, the present invention should not be construed as being limited only to the contents described in the following embodiments.

Embodiment 1 ＜＜Structure Example of Logic Circuit＞＞ FIG. 1A shows a structural example of a logic circuit. The logic circuit 100 shown in FIG. 1A is a semiconductor device capable of holding data (state). Depending on the circuit structure, etc., it can also be called a sequential circuit. The logic circuit 100 is a semiconductor device capable of clock gating and power gating. The logic circuit 100 includes a circuit 10 and a circuit RC1. Circuit RC1 is a hold circuit having a function capable of holding data. The circuit RC1 has a function of reading and holding the state (data) of the circuit 10 . In addition, the circuit RC1 has a function of reading the held data to the circuit 10 .

<Circuit 10> The circuit 10 includes terminals D1 to Dn (n is an integer greater than or equal to 2), a terminal Q, a terminal QB, and a terminal EN. Terminals D1 to Dn are data input terminals. Terminal Q and terminal QB are data output terminals. The terminal EN is a terminal to which the control signal E0 is input. The circuit 10 may be a logic circuit. The circuit 10 may have a function of selecting any one of the terminals D1 to Dn according to the logic of the terminal EN and outputting data of the same logic as the data input to the selected terminal from the terminal Q. The terminal QB is a terminal for outputting data inverting the logic of the terminal Q. In the example of FIG. 1A , the circuit 10 may not include the terminal QB.

FIG. 1B shows a structural example of the circuit 10 . The circuit 10 shown in FIG. 1B includes a selection circuit 20 and a circuit 30 . The terminal T1 of the selection circuit 20 is electrically connected to the terminal T2 of the circuit 30 . The terminal T1 is an output terminal of the selection circuit 20 , and the terminal T2 is an input terminal of the circuit 30 .

The signal E0 is a control signal of the selection circuit 20 . The selection circuit 20 has a function of selecting any one of the terminals D1 to Dn according to the signal E0 and electrically connecting it to the terminal T1.

The circuit 30 may be a logic circuit. The circuit 30 may have a calculation function, that is, a function of outputting from the terminal Q data having the same logic as the data input to the terminal T2. For example, the circuit 30 may be a sequential circuit for updating internal states according to control signals such as the clock signal CLK. For example, the circuit 30 may be a latch, a flip-flop, a shift register, a counting circuit, a frequency division circuit, and the like.

<Circuit RC1> The circuit RC1 includes a node FN, a terminal D0, a terminal T0, a switch SW1, a switch SW2, a switch SW3, and a capacitor C1. Terminal D0 and terminal T0 are input terminals.

The node FN is a node that can be in an electrically floating state, and is used as a data (state) holding unit of the circuit RC1 . One terminal of the capacitor C1 is electrically connected to the node FN, and the other terminal is electrically connected to the terminal T0. The capacitor C1 may be used as a storage capacitor maintaining the voltage of the node FN. A signal or a fixed voltage can be input to terminal T0. For example, a low power supply voltage of the circuit 10 may be input to the terminal T0.

The switch SW1 controls the conduction state between the terminal D0 and the terminal D1, and the switch SW2 controls the conduction state between the terminal Q and the node FN. The on/off of the switches SW1 and SW2 is controlled according to the signal E2. The switch SW3 controls the conduction state between the node FN and the terminal D1. The on/off of the switch SW3 is controlled according to the signal E3.

(regular work) When the circuit 10 processes the input data, the switch SW3 is turned off. Turn on the switch SW1 as needed. When the data processed by the circuit 10 does not include the data of the terminal D1, it is sufficient to turn off the switch SW1. When the data processed by the circuit 10 includes the data of the terminal D1, the switch SW1 can be turned on. The state of the switch SW2 can be on or off. In the example of FIG. 1A , the switch SW2 is also turned on in linkage with the switch SW1 according to the signal E2. By making the control signals of the switch SW1 and the switch SW2 different, the switch SW2 can also be turned off. By making the control signals of the switch SW1 and the switch SW2 the same, the number of wires and the number of elements can be reduced, thereby reducing power consumption.

(backup job) In order to back up the state of the circuit 10 , if necessary, the input of signals such as CLK to the circuit 10 is stopped so as not to change the logic (state) of the terminal Q. Next, the switch SW2 is turned on and the switch SW3 is turned off. Since the node FN is electrically connected to the terminal Q, the logic of the node FN is the same as that of the terminal Q. If the logic of the terminal Q is "1", the node FN is also "1", and if the logic of the terminal Q is "0", the node FN is also "0". By closing the switches SW2 and SW3 and making the node FN in the electrically floating state, the backup is terminated, and the circuit RC1 is in the data holding state.

By ending the backup, the power supply to the circuit 10 can be stopped. That is to say, by providing the circuit RC1 , clock gating and power gating of the circuit 10 can be performed.

(Return to work) In order to restore the state of the circuit 10, power is supplied to the circuit 10, and the circuit 10 is brought into a state capable of outputting the data of the terminal D1 from the terminal Q according to the signal E0. Since the terminal D1 is electrically connected to the node FN, the logic level of the terminal D1 is the same as that of the node FN. Therefore, the circuit 10 can output from the terminal Q data of the same logic as the data held in the node FN. That is, the state of the logic circuit 100 is restored.

Make switch SW3 close. By restarting the supply of the signal CLK as needed, the logic circuit 100 is in a state capable of normal operation. When it is necessary to make the logic of the terminal Q the same as the logic of the node FN during the data hold period before restarting the supply of the signal CLK, supply a control signal such as the signal CLK before turning off the switch SW3 to make the circuit 10 perform normal operation, and The data of terminal D1 can be written into terminal Q.

The circuit RC1 may have a retention characteristic capable of retaining data when power gating the circuit 10 . In order to hold data in the circuit RC1 for a long time, it is preferable to suppress as much as possible a change in the potential of the node FN in the electrically floating state (in particular, a drop in potential). As one of the solutions, there may be a method of configuring the switches SW2 and SW3 using transistors whose drain current (off-state current) in a non-conducting state is very small.

In order to reduce the off-state current of the transistor, for example, a semiconductor region may be formed using a semiconductor with a large energy gap. The energy gap of the semiconductor is preferably 2.5 eV or more, 2.7 eV or more, or 3 eV or more. An oxide semiconductor is mentioned as said semiconductor. For example, the switches SW2 , SW3 may be transistors (OS transistors) including semiconductor regions formed using an oxide semiconductor. At a source-drain voltage of 10V and room temperature (about 25°C), the leakage current of an OS transistor normalized by channel width can be below 10×10 ^{− 21} A/μm (10zA/μm). The leakage current of the OS transistors used in switches SW2 and SW3 is preferably below 1×10 ^{− 18} A, below 1×10 ^{− 21} A or below 1×10 ^{− 24} A at room temperature (about 25°C). Alternatively, the leakage current is preferably 1×10 ^{− 15} A or less, 1×10 ^{− 18} A or less, or 1×10 ^{− 21} A or less at 85°C.

The oxide semiconductor has a large energy gap, electrons are not easily excited, and the effective mass of holes is large. Therefore, an OS transistor may be less prone to avalanche breakdown or the like than a general transistor using silicon or the like. The OS transistor has a high drain withstand voltage by suppressing hot carrier degradation due to sudden collapse, etc., and thus can be driven at a high drain voltage. Therefore, by applying the OS transistor to the circuit RC1 , it is possible to increase the working margin of the driving conditions such as the potential level of the signal and the input timing. For example, driving may be performed to increase the voltage of the node FN in the data hold state.

The oxide semiconductor of the OS transistor is preferably an oxide containing at least one or more elements selected from In, Ga, Sn, and Zn. As the oxide, there are In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al- Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In oxide, Sn oxide, Zn oxide, etc. In addition, an oxide semiconductor obtained by adding an element or compound other than the constituent elements of the oxide to the above-mentioned oxide, such as SiO ₂ , may also be used.

In OS transistors, even if the gate insulating layer is thickened, that is, its equivalent oxide thickness is about 11nm, and the channel length is shortened, that is, about 50nm, it can also have very good off-state current characteristics. and subcritical properties. Thus, since the OS transistor can use a gate insulating layer thicker than that of a general Si transistor constituting a logic circuit, the leakage current through the gate insulating layer can be reduced, and the leakage caused by the gate insulating layer can also be suppressed. Uneven electrical properties due to uneven thickness. Details of the OS transistor will be described in Embodiment Mode 4. FIG.

There is no particular limitation on the transistors constituting the switch SW1 and the circuit 10, and general transistors suitable for standard cells can be used, for example, transistors whose semiconductor regions are formed using group 14 elements (Si, Ge, C) can be used. A typical example of the transistor of the circuit 10 is a transistor (Si transistor) whose semiconductor region is formed using silicon. In addition, in order to improve the mobility of the Si transistor, etc., it is also possible to use a bend transistor in which Ge is added to a semiconductor region containing Si.

The switch SW1 may be configured using an OS transistor similarly to the switch SW2 and the switch SW3, or may be configured using a CMOS circuit such as an analog switch. By using an OS transistor as the switch SW1, the additional area of the logic circuit 100 when the circuit RC1 is added can be made zero as described below. In addition, by stacking the n-type OS transistor on the p-type Si transistor when the switch SW1 is an analog switch (a switch in which an n-type transistor and a p-type transistor are connected in parallel), it is possible to use only the Si transistor. Compared with the case where an analog switch is configured, the area of the logic circuit 100 is suppressed from increasing. In addition, the analog switch may also be referred to as a transfer gate.

In the logic circuit 100, there is no need to change the circuit configuration of the circuit 10 due to setting the circuit RC1. For example, in the case of the configuration example shown in FIG. The general circuit of the device. A general sequential circuit such as a latch circuit or a flip-flop circuit can be applied as the circuit 30 . Since the circuit RC1 can be laminated on the circuit 10, the circuit RC1 can be provided without changing the design and layout of the circuit 10.

As described above, by employing the holding circuit of this embodiment, the logic circuit can be provided with a backup function without changing the circuit structure and layout of the logic circuit. In addition, by employing the holding circuit, it is possible to provide a logic circuit with a backup function without substantially degrading the performance during normal operation. In addition, since the holding circuit is stacked on the region where the logic circuit is formed, the additional area when the holding circuit is added can be reduced to zero.

＜Modification example of hold circuit＞ Logic circuit 101 shown in FIG. 2A includes circuit RC2 instead of circuit RC1. The circuit RC2 is a circuit in which an inverter 42 is added to the circuit RC1. The input terminal of the inverter 42 is electrically connected to the terminal QB, and the output terminal is electrically connected to the switch SW2. Circuit RC2 holds data for inverting the logic of terminal QB. Therefore, the circuit RC2 can hold data of the same logic as that of the terminal Q and write the held data to the terminal D1. It is preferable to supply power when only the inverter 42 is performing a backup operation.

Logic circuit 102 shown in FIG. 2B includes circuit RC3 instead of circuit RC1 . Circuit RC3 is a circuit in which inverters 43 and 44 are added to circuit RC1. The input terminal of the inverter 43 is electrically connected to the switches SW1 and SW3, and the output terminal is electrically connected to the terminal D1. The input terminal of the inverter 44 is electrically connected to the terminal D0, and the output terminal is electrically connected to the switch SW1. The switch SW2 controls the conduction state between the terminal QB and the node FN. By backup operation, the circuit RC3 maintains the same logical data as the terminal QB. The data written to the terminal D1 by the recovery operation is the data inverting the logic of the node FN by the inverter 43 . That is, data of the same logic as that of the terminal Q can be written into the terminal D1.

The circuit 10 shown in FIGS. 2A and 2B may also not include the terminal Q. As shown in FIG.

＜Modification example of logic circuit＞ The logic circuit 103 shown in FIG. 3 is a modified example of the logic circuit 101 . The circuit 10 is changed into a circuit 15 with one input. Circuit 15 is a logic circuit. The circuit 15 may have an arithmetic function capable of outputting data of the same logic as that of the terminal D1. Control signals such as CLK may also be input to the circuit 15 as needed. In addition, the circuit 15 may also include a terminal QB. The circuit 15 may be, for example, a buffer circuit.

Circuit RC4 is a modified example of circuit RC1. The switches SW1 to SW3 are controlled by signals E1 to E3 different from each other. Accordingly, only the switch SW1 can be turned on during the normal operation of the logic circuit 103, and can be turned off during the backup operation.

Embodiment 2 ＜＜Structure example of scanning flip-flop＞＞ A more specific example of the circuit configuration and driving method of the logic circuit 100 will be described. Here, an example in which the logic circuit 100 is a scanning flip-flop is shown. The scanning flip-flop (SFF) 110 shown in FIG. 4 includes a scanning flip-flop (SFF) 11 and a circuit RC11 . The SFF 11 includes a selection circuit (SEL) 21 and a flip-flop (FF) 31 . The circuit RC11 is a holding circuit having a function of holding data. SFF 110 may be called a scanning FF with a backup function. SFF110 can be set in the power domain (power domain) for power gating.

<Structure example of SFF11> FIG. 5 shows an example of the circuit configuration of SFF11. SFF11 shown in FIG. 5 includes SEL21, FF31 and terminals VH, VL, D, Q, QB, SD, SE, CK, and RT.

Terminal VH is a power supply terminal for high power supply voltage VDD, and terminal VL is a power supply terminal for low power supply voltage VSS. VDD and VSS are supplied to the inverter of SEL21, the inverter of FF31, and a NAND circuit (hereinafter referred to as “NAND”). VDD is input to the terminal VH through the power switch.

Terminals D and SD are data input terminals. Terminal D is electrically connected to an output terminal of a logic circuit (for example, a combinational circuit), and data DIN is input to terminal D. Restoration data or scan test data SCNIN is input to the terminal SD through the circuit RC11 (see FIG. 4 ). Terminal Q is a data output terminal. The terminal Q is electrically connected to the terminal SD_IN of other SFF 110 and the data input terminal of the logic circuit. The terminal QB outputs data that inverts the logic of the terminal Q. Terminal QB is electrically connected to data input terminals of other logic circuits. Set the terminal QB as needed, that's it.

Terminals SE, CK, and RT are input terminals for control signals. The scan enable signal SEsig is input to the terminal SE. SE is electrically connected to SEL21. The clock signal CLK is input to the terminal CK. The terminal CK is electrically connected to the circuit 31a. A reset signal RSTsig is input to the terminal RT. Terminal RT is electrically connected to NAND of FF31.

(SEL21) SEL21 selects any one of terminal D and terminal SD according to the voltage (logic) of terminal SE, and electrically connects it to the input terminal of FF31. When performing a scan test, the signal SE is set to a high level voltage (“H”), and the terminal SD is electrically connected to the input terminal of the FF31. When the SFF11 is used as a flip-flop for normal operation, the terminal SE is set to a low level voltage ("L"), and the terminal D is electrically connected to the input terminal of the FF31.

(FF31) FF31 includes two latches 32M, 33S and a circuit 31a. The latch 32M is a master latch, and the latch 32S is a slave latch, and the latch 32M and the latch 32S are electrically connected in series. The circuit 31a is a clock signal input circuit and includes terminals CK1 and CKB1. The terminal CK1 is a terminal for outputting a non-inverted clock signal of the signal CLK. The terminal CKB1 is a terminal for outputting an inverted clock signal of the signal CLK. Both terminals CK1 and CKB1 are electrically connected to the analog switch of FF31.

<Structure Example 1 of Hold Circuit> The circuit RC11 shown in FIG. 4 includes terminals SD_IN, RE, BK, PL, a node FN11, transistors M1 to M3, and a capacitor C11. The circuit RC11 is a circuit in which the switches SW1 to SW3 of the circuit RC1 are composed of transistors M1 to M3, respectively. Note that in the following description, the terminal VH is sometimes referred to as VH. The same applies to other terminals. In addition, the node FN11 is sometimes referred to as FN11.

SD_IN is the input terminal of scan test data SCNIN. BK and RE are input terminals for control signals. Input the signal (backup signal BKsig) to control the backup work to BK. BK is electrically connected to the gates of transistors M1 and M2. A signal (resume signal REsig) for controlling resumption of operation is input to RE. RE is electrically connected to the gate of transistor M3.

One of the two terminals of the capacitor C11 is electrically connected to FN11, and the other is electrically connected to PL. Input VSS to PL. Transistors M1 to M3 are n-type, here OS transistors. Transistor M1 is a path transistor for electrically connecting SD_IN and SD. Transistor M2 is a path transistor used to electrically connect Q and FN11. Transistor M3 is a path transistor used to electrically connect FN11 and SD.

By using the OS transistors as the transistors M2 and M3, it is possible to suppress the voltage drop of the FN11 even in the state where the FN11 holds the data of "1". Therefore, the circuit RC11 can be used as a non-volatile memory circuit for backing up the SFF11. In addition, power gating can be performed on the semiconductor device on which the SFF 110 is mounted, thereby reducing the power consumption of the semiconductor device.

Note that sometimes during the data retention period of the circuit RC11, a voltage to completely turn off the transistors M2 and M3 is always applied to the gate. Alternatively, when the transistors M2 and M3 are provided with a back gate, the back gate may always be supplied with a voltage that keeps the transistors M2 and M3 in a normally-off state. In this case, although a voltage is supplied to the circuit RC11 during the hold period, current hardly flows, and thus the circuit RC11 consumes little power. Since the circuit RC11 consumes almost no power even if a fixed voltage is supplied to the circuit RC11 during the hold period, it can be said that the circuit RC11 is a nonvolatile circuit.

＜<Working example of scanning flip-flops＞＞ 6 and 7 are timing charts showing an example of the operation of the SFF 110 . FIG. 6 shows an example of the operation of the SFF 110 when the semiconductor device incorporating the SFF 110 transitions from the active mode to the sleep mode, and FIG. 7 shows an example of the operation of the SFF 110 when the semiconductor device incorporating the SFF 110 transitions from the sleep mode to the active mode. 6 and 7 show changes in the voltage (logic) of the terminals VH, CK, Q, SE, SD, BK, RE and the node FN11. In FIG. 6 and FIG. 7, the maximum value of the voltage is VDD, and the minimum value is VSS. t1 to t10 represent time.

＜Activity Mode (Normal Work Mode)＞ In active mode, the SFF110 performs normal work. The SFF 110 is used as a flip-flop that temporarily holds output data from a logic circuit. Here, the output data of the logic circuit is input to the terminal D. During normal operation, with RE and BK at "L", transistors M1 to M3 are off. SE is "L", and terminal D is connected to the input terminal of FF31 through SEL21. RT is "H". The signal CLK is input to CK. When CK is "H", the voltage (logic) of Q changes in conjunction with this.

<Scan mode> In scan mode, multiple SFFs 110 are electrically connected in series to form a scanner chain. In circuit RC11, transistors M1, M2 are turned on, and transistor M3 is turned off. Since SE is "H", SD is electrically connected to the input terminal of FF31 through SEL21. That is, in the scan mode, the output data of the Q of the SFF11 is input to the SD of the SFF11 of the next stage.

(scan test) In order to perform a scan test, in scan mode, scan test data SCNIN is input to SD_IN of the SFF 110 of the first stage of the scanner chain. The drifting of the scanner chain is performed by inputting CLK, and the scanning test data SCNIN is written into the SFF110 of the scanner chain. Next, the SFF 110 is operated normally, and the output data of the logic circuit is held in the SFF 110 . Set to scan mode again to do the drift work of the scanner chain. Based on the data output from the Q output of the final stage SFF110, it is possible to determine whether the logic circuit and the SFF110 are faulty or not.

(backup sequence) A backup sequence is performed by transitioning from active mode to sleep mode. In the backup sequence, clock gating (clock stop), data backup and power gating (power off) are performed. Set to sleep mode by stopping the supply of clock.

In the example of FIG. 6, at t1, the clock gating of SFF11 and the backup operation of circuit RC11 are started. Specifically, at t1, CK is set to "L" and BK is set to "H". The period when BK is "H" is the backup working period. By setting BK to "H", FN11 is electrically connected to Q through transistor M2. Therefore, if Q is "0", FN11 remains "L", and if Q is "1", the voltage of FN11 rises to "H". That is, the logic of FN11 can be made the same as that of Q while BK is "H". The period during which BK is "H" is determined so that the voltage of FN11 rises to a logic level of "1". By setting BK to "L" at t2 and turning off the transistors M1 and M2, FN11 is in the electric floating state, and the circuit RC11 is in the data holding state.

At t3, the power is turned off, and RT is set to "L". The voltage of VH gradually drops from VDD to VSS. It is also possible to stop the power supply at t2. In addition, it is sufficient to cut off the power supply as needed. Depending on the configuration of the power domain of the semiconductor device incorporating the SFF 110 , the time spent in the sleep mode, etc., the power required to return from the sleep mode to the active mode may be greater than the power that can be reduced by shutting off the power supply. In this case, since the effect of power gating cannot be obtained, it is preferable to stop only the supply of the clock in the sleep mode without shutting off the power.

(resume sequence) In the recovery sequence from the sleep mode to the active mode, the power is turned on, the data is restored, and the clock is supplied. The active mode is set by starting the supply of the clock.

At t4, the power is turned on. The voltage of VH gradually rises from VSS to VDD. Start to resume operation after VH becomes VDD. At t5, SE and RE are set to "H". Also, set RT to "H". Perform recovery work with RE in "H" state. Transistor M3 is turned on, and FN11 is connected to SD. If FN11 is "L", then SD remains "L". If FN11 is "H", the voltage of SD rises to "H". At t6, SE is set to "H". SD is electrically connected to the input terminal of FF31 through SE and SEL21. That is, by setting RE to "H", the data held in FN11 is written to SD.

In addition, at t5, RE may be set to "H" together with SE. As shown in FIG. 7, when FN11 is "H", it is preferable to set SE to "H" after the voltage of SD rises to a logic level of "1". By employing the above-described driving method, it is possible to prevent a through current from flowing through the SFF 11 .

Since the data of FN11 is written into SD by capacitance distribution, when FN11 is connected to SD while FN11 is in the "H" state, the voltage of FN11 drops due to the parasitic capacitance of SD. Therefore, it may be necessary to make the capacitance of C11 sufficiently larger than the parasitic capacitance of SD. The capacitance of C11 may be determined in consideration of the characteristics of the logic circuit to which SD data is input, and the like. For example, when the threshold voltage of the logic circuit is VDD/2, the capacitance of C11 needs to be equal to or greater than the parasitic capacitance of SD.

After making the logic of SD the same as FN11, set CK to "H" for a fixed period (t7 to t8). In the example of FIG. 7, CLK of one clock is input to CK. By setting CK to "H" at t7, the data of the latch 32M is written into the latch 32S. At t7, if SD is "0", Q is "0", and if SD is "1", Q is "1". That is, the data of FN11 is written in Q, and SFF110 returns to the state before the supply of CLK was stopped (it entered the sleep mode). At t9, SE and RE are set to "L", and the recovery operation ends. D is electrically connected to the input terminal of FF31 through SEL21. In the circuit RC11, the transistor M3 is turned off, and the node FN11 becomes a floating state.

After SE and RE are set to "L", CLK input is restarted at t10 when a fixed period (for example, one clock period) elapses, and the SFF 110 is placed in an active mode. SFF110 for routine work.

As mentioned above, the SFF 110 can perform data backup and restoration at high speed, for example, within a few clocks (2 to 5 clocks), the backup and restoration can be performed. Since the write operation of the circuit RC11 is to charge or discharge the FN11 by switching the transistors M1 to M3, and the read operation is to charge or discharge the SD by switching the transistors M1 to M3. So these jobs require as little energy as a DRAM cell. Since there is no need to supply power to the circuit RC1 in order to hold data, the standby power of the SFF 110 can be reduced. Likewise, since there is no need to supply power to the circuit RC11 during normal operation, the dynamic power of the SFF 110 is substantially not increased when the circuit RC11 is set. Although the parasitic capacitance of the transistor M1 is added to the terminal Q when the circuit RC11 is set, since the parasitic capacitance of the transistor M1 is smaller than the parasitic capacitance of the logic circuit connected to the terminal Q, it has no effect on the normal operation of the SFF110. In essence, the circuit RC11 The setting does not degrade the performance of SFF110 in active mode.

Next, taking the scan FF as an example, other circuit configuration examples of the holding circuit will be described.

<Structure Example 2 of Hold Circuit> SFF112 shown in FIG. 8 includes circuits RC12 and SFF11. The circuit RC12 is a modified example of the circuit RC11 ( FIG. 4 ), and includes a capacitor C12 for capacitive coupling between the node FN11 and the terminal RE. In the above-described circuit configuration, by setting the voltage of RE at the time of resume operation to VDD (“H”), the voltage of the node FN11 can be increased. Therefore, the period during which the circuit RC12 can hold the voltage of "H" is longer than that of the circuit RC11. However, at this time, even when the node FN11 maintains the voltage of "L", the voltage of the node FN11 rises. Therefore, at this time, the capacitance of the capacitor C12 is set so that the voltage of the SD becomes a logic level of "0" when the voltage of "L" of the node FN11 is written into the SD. Thus, the capacitance of the capacitor C12 is smaller than that of C11.

<Structure examples 3 and 4 of the holding circuit> SFF113 shown in FIG. 9 includes circuits RC13 and SFF11. SFF114 shown in FIG. 10 includes circuits RC14 and SFF11.

In the circuit RC12 shown in FIG. 8, depending on the capacitance ratio of the capacitors C12 and C11, when the voltage of the node FN11 is written to SD at "H", the voltage of SD may exceed the logic level of "1". In this case, the circuit RC13 or the circuit RC14 may be used as a holding circuit. The circuit RC13 is a circuit in which a buffer 45 (hereinafter referred to as BUF45 ) is added to the circuit RC12 . The input terminal of BUF45 is electrically connected to the drain (or source) of transistor M3, and the output terminal of BUF45 is electrically connected to SD. The transistor of the BUF 45 is preferably a high withstand voltage transistor capable of withstanding a gate voltage exceeding VDD.

The circuit RC14 shown in FIG. 10 is a modified example of the circuit RC13. As shown in FIG. 10, the connection position of the capacitor C12 is different from that of the circuit RC13. One terminal of the capacitor C12 is electrically connected to the drain (or source) of the transistor M3, and the other terminal is electrically connected to the input terminal of the BUF45. Set BUF45 in circuit RC14 as needed.

<Structure examples 5 and 6 of the holding circuit> SFF115 shown in FIG. 11 includes circuits RC15 and SFF11. SFF116 shown in FIG. 12 includes circuits RC16 and SFF11. The circuit RC15 and the circuit RC16 are modified examples of the circuit RC11, including transistors M1 to M3 provided with back gates.

In circuit RC15, the back gates of transistors M1 to M3 are electrically connected to terminal OBG. Signal or fixed potential can be input to OBG. Alternatively, a capacitor can also be connected to the OBG. It is also possible to maintain the voltage of the back gates of the transistors M1 to M3 by charging the capacitor. According to the voltages of the back gates of the transistors M1 to M3 , for example, the threshold voltages of the transistors M1 to M3 can be adjusted.

In the circuit RC16, the back gates are electrically connected to the gates of the transistors M1 to M3. By adopting the above device structure, the on-state current characteristics of the transistors M1 to M3 can be improved.

Although the back gates are provided in the transistors M1 to M3 in the circuit RC15, some transistors may not include the back gates. In addition, when the back gate is provided in the transistor M1, the back gate may be connected to the terminal OBG, or may be electrically connected to the gate of the transistor M1. The same applies to the transistors M2 and M3. The same applies to circuit RC16.

＜＜Structure Example of Processing Equipment＞＞ An example of a semiconductor device including a scan FF will be described. The semiconductor device shown in FIG. 13 includes a processing unit (PU) 200 and a power supply circuit 210 . PU 200 is a circuit having a function of executing instructions. PU200 includes a plurality of functional circuits integrated on one chip. The PU 200 includes a processor core 201 , a power management unit (PMU) 202 , a power switch (PSW) 203 and a clock control circuit 204 . FIG. 13 shows an example in which the power supply circuit 210 and the PU 200 are provided on different chips. The terminal 220 is a terminal for a power supply, and the power supply voltage VDD is input to the terminal 220 from the power supply circuit 210 . Terminals 221 and 222 are signal input terminals. The terminal 221 is input with the main clock signal MCLK. The signal INT is input to the terminal 222 . Signal INT is an interrupt signal requesting interrupt processing. Signal INT is input to processor core 201 and PMU 202 .

＜Processor Core＞ The processor core 201 is a circuit having a function of processing instructions, and may also be called an arithmetic processing circuit or a processor (processing device). The processor core 201 includes a logic circuit 240 , an SFF (Scan FF) 250 and the like, which constitute various functional circuits. For example, logic circuit 240 may be a combinational circuit. For example, SFF250 is included in the scratchpad. SFF250 includes SFF50 and circuit RC50. SFF50 only needs to have the function of scanning FF, and can be composed of scanning FF prepared in a general circuit library. Circuit RC50 is a holding circuit for backing up SFF50, and circuits RC11 to RC14 are applicable. The terminal Q of the SFF 250 is electrically connected to the input terminal of the logic circuit 240 , and to constitute a scanner chain, the terminal Q of the SFF 250 is electrically connected to the terminal SD_IN of another SFF 250 . By setting the SFF250, the clock gating and power gating of the processor core 201 can be performed, thereby reducing the power consumption of the PU200.

FIG. 14 is an example of the configuration of the processor core 201 . The processor core 201 shown in FIG. 14 includes a control device 231 , a program counter 232 , a pipeline register 233 , a pipeline register 234 , a register file 235 , an ALU (arithmetic logic unit) 236 and a data bus 237 . The data transmission between the processor core 201 and peripheral circuits such as the PMU 202 or the cache memory is performed through the data bus 237 .

The control device 231 comprehensively controls the work of the program counter 232, the pipeline register 233, the pipeline register 234, the register file 235, the ALU 236, and the data bus 237, and controls the programs included in the input application software and the like. Instructions are decoded and executed. ALU236 has the function of performing various arithmetic processing such as four arithmetic operations and logical operations. The program counter 232 has a register for storing the address of the instruction to be executed next.

The pipeline register 233 is a register with the function of temporarily storing instruction data. The register file 235 has a plurality of registers including general-purpose registers, and can store data read from the main memory or data obtained from the operation processing results of the ALU 236 . The pipeline register 234 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 236 or data obtained from the results of the arithmetic processing of the ALU 236 .

＜Power Management＞ PMU202 has the functions of controlling power gating, clock gating, etc. Specifically, PMU 202 has a function capable of controlling processor core 201 , PSW 203 , and clock control circuit 204 . The PMU 202 has a function of outputting control signals such as BKsig, REsig, and SEsig to the processor core 201 .

PMU 202 includes circuitry 205 . The circuit 205 has a function of measuring time. The PMU 202 has a function of power management based on the time data obtained by the circuit 205 . For example, by using a timer circuit as the circuit 205 , the timer interrupt request signal can also be generated in the PMU 202 . The circuit 205 can be provided as needed.

PSW 203 has a function of controlling the supply of VDD to PU 200 according to the control signal of PMU 202 . In the example of FIG. 13, the processor core 201 may also have multiple power domains. At this time, the power supply to multiple power domains can be independently controlled by PSW203. Processor core 201 may also have power domains that are not power gating. At this time, VDD may be supplied to the power domain without passing through PSW203.

The clock control circuit 204 has a function of receiving a signal MCLK to generate a gated clock signal and outputting it. The clock control circuit 204 has a function of stopping the supply of the clock signal to the processor core 201 according to the control signal of the PMU 202 . The power supply circuit 210 may also have a function of changing the potential level of VDD according to a control signal of the PMU 202 .

Signal SLP is output from processor core 201 to PMU 202 . The signal SLP is a trigger signal used to transfer the processor core 201 to the sleep mode. A backup sequence of SFF 250 is executed in processor core 201 according to signal SLP. The backup sequence of SFF250 can be executed similarly to the backup sequence of SFF110 shown in FIG. 6 . The PMU 202 outputs a control signal for transitioning from the active mode to the sleep mode to the functional circuit of the control object when receiving the signal SLP. The PMU 202 controls the clock control circuit 204 to stop supplying the clock signal to the processor core 201 . Also, PMU 202 controls PSW 203 to stop power supply to processor core 201 .

A process for restoring the processor core 201 from the sleep mode to the active mode is performed by the input signal INT. A recovery sequence of SFF 250 is executed in processor core 201 according to signal INT. The recovery sequence of SFF 250 can be executed in the same manner as the recovery sequence of SFF 110 shown in FIG. 7 . The PMU 202 outputs a control signal for transitioning from the sleep mode to the active mode to the functional circuit of the control object when receiving the signal INT. PMU 202 controls PSW 203 to start supplying power to processor core 201 again. In addition, the PMU 202 controls the clock control circuit 204 to start supplying the clock signal to the processor core 201 again.

The backup sequence can also be executed triggered by the signal INT or the interrupt request signal of the PMU 202 . In addition, the recovery sequence may be executed when an interrupt request signal from PMU 202 is used as a trigger.

<<Device Structure of SFF250>> FIG. 15 shows the device structure of SFF250. In FIG. 15, circuit RC50 has the same circuit configuration as circuit RC11 (FIG. 4). Transistors M1 to M3 are OS transistors. SFF250 may have a three-dimensional device structure in which circuit RC50 is laminated on SFF50. W ₁ , W _k , W _{k + 1} , and W _h are the first wiring layer, the kth wiring layer, the k+1th wiring layer, and the hth wiring layer, respectively. K is an integer of 1 or more, and h is an integer of k+2 or more. The terminals D, SD, Q, SE, and CK of the SFF50 are provided on the wiring layer _Wk , and the terminal SD_IN of the circuit RC50 is provided on the wiring layer _Wh .

Transistors of SFF 50 are provided in the FET layer 260 . The transistors of the FET layer 260 can be fabricated by a common CMOS process. The transistors of the FET layer 260 are electrically connected by conductors of the wiring layers W ₁ to W _k . The SFF50 is electrically connected to the circuit _RC50 through the conductors of the wiring layers _{Wk + 1} to Wh.

Since the number of elements of the circuit RC50 is much smaller than that of the SFF50, it is not necessary to change the circuit structure and layout of the SFF50 in order to laminate the circuit RC50. That is to say, the circuit RC50 is a backup circuit with very high versatility. In addition, since the circuit RC50 can be provided in the region where the SFF 50 is formed, the additional area of the SFF 250 is zero even if the circuit RC50 is mounted.

＜＜Integrated circuit of assembly circuit RC50＞＞ Therefore, in the processor core 201 shown in FIG. 13 , the circuit RC50 does not affect the configuration of the SFF 50 , so that the SFF 50 can be configured to efficiently perform scan testing. That is, by using the circuit RC50 as a backup circuit, it is possible to easily design an integrated circuit with a backup function, and to ensure ease of testability.

In the processor core 201 , like the SFF 50 , other standard cells such as NAND circuits are provided in the FET layer 260 and the wiring layers W ₁ to W _k . Since the conductors for connecting the circuit RC50 and the terminals SD and Q are formed in the wiring layers W1 to _Wk , the wiring _of other standard cells needs to be arranged bypassing these conductors, and thus the area of the processor core 201 may increase. The SFF250 is one of the standard units installed in the processor core 201 in many cases, and the additional area of the SFF250 caused by the installation of the circuit RC50 is zero. Therefore, an increase in the area of the processor core 201 is caused by a change in the layout of wiring between other standard cells, so that the additional area of the processor core 201 can be suppressed to less than several percent. This fact was confirmed by designing a processor core equipped with circuit RC50. In addition, the reduction in power consumption of the processor core in which the circuit RC50 is mounted was confirmed by calculation.

<Area and Power of Processor Core> A processor core equipped with a scanning FF including circuit RC50 is designed. This processor core is called "OS-FF installed processor", and the scan FF including the circuit RC50 is called OS-FF. For comparison, a CPU core with scan FF without circuit RC50 was designed and installed. This processor core is referred to as "Si-FF installed processor".

The designed processor core is a RISC processor core. The circuit configuration of the OS-FF mounted processor is the same as that of the Si-FF mounted processor except for the presence or absence of the circuit RC50. Circuits other than circuit RC50 are made of Si transistors. The processor core is designed with the design rule that the channel length of Si transistor is 60nm and the channel length of OS transistor is 60nm. The Si-FF mounted processor has an area of 275 μm × 272 μm, and the OS-FF mounted processor has an area of 275 μm × 272 μm. The area occupied by the scan FF is approximately half of the logic circuit of the processor core. Even if the circuit RC50 is provided in each scan FF on which a processor is installed in the OS-FF, the additional area is suppressed to 3%.

In terms of calculation, when the power supply voltage is 1.2V, the dynamic power of the Si-FF installed processor is 19μA/MHz, and the dynamic power of the OS-FF installed processor is also 19μA/MHz. The installation of the circuit RC50 does not increase the dynamic power. In addition, the standby power of the OS-FF mounted processor when power gating is estimated to be 0.03 μA.

The performance of the designed OS-FF is confirmed by calculation. When the channel length of the OS transistor is 65nm and the critical voltage is 1.6V, the retention time of OS-FF at room temperature exceeds 30 days. That is, it was confirmed that the OS-FF has sufficient retention performance as a non-volatile memory circuit during the sleep period of the processor on which the OS-FF is installed.

In terms of calculation, the backup time and recovery time of OS-FF when the working frequency is 50MHz are both 2 clocks. The additional time for the power gating operation of the OS-FF mounted processor was sufficiently short, and it was confirmed that the OS-FF did not substantially degrade the performance of the processor.

Through the calculation, the effect of power gating to reduce the power consumption of OS-FF mounted processors was confirmed. Power consumption is estimated separately under the operating conditions of 1 msec during active and 1 msec, 1 sec, 100 sec during sleep. The supply voltage is 1.2V. Power consumption under operating condition 1 (1msec during active, 1msec during sleep) is 570μW. Power consumption under operating condition 2 (1msec during active, 1sec during sleep) is 1.2μW. The power consumption under operating condition 3 (1msec during active period and 100sec during sleep period) is 0.05μW. It was confirmed that the power consumption of the OS-FF mounted processor can be efficiently reduced by performing power gating during sleep.

Since the scan FF of this embodiment has a hold circuit, for example, the following excellent effects are exhibited. In this scan FF, the additional area when the hold circuit is provided may be zero. When the hold circuit is provided, there is almost no power consumption at the time of normal operation, and performance of normal operation can be hardly degraded. Low power consumption and high-speed backup and restoration are possible. Data can be retained without supplying power. Since the scanning FF of the circuit library is directly used to design the scanning FF, the designability of the scanning FF is high. Therefore, even if the integrated circuit installed with the scanning FF constitutes a scanning chain with the scanning FF, its testability will not be damaged.

In this way, the scan FF is very suitable for normally-off computing. Even if this scanning FF is mounted, an increase in dynamic power and a decrease in performance of the integrated circuit can hardly occur. Therefore, the integrated circuit equipped with the scanning FF can effectively reduce power consumption by performing power gating while maintaining performance.

Although it is described here that the sequential circuit scans the FF, other sequential circuits can also obtain the above effects.

Embodiment 3 In this embodiment, an electronic component and an electronic device including the electronic component will be described as an example of a semiconductor device.

＜Example of manufacturing method of electronic components＞ FIG. 16A is a flowchart showing an example of a manufacturing method of an electronic component. Electronic components are also called semiconductor packages or packages for ICs. The electronic component has a plurality of different specifications and names depending on the direction in which the terminal is taken out or the shape of the terminal. In this embodiment, an example thereof will be described.

Through the assembly process (post-process), and by combining a plurality of detachable components on the printed circuit board, a semiconductor device composed of transistors is completed. The post-processing can be completed by performing each process shown in FIG. 16A. Specifically, after the element substrate obtained by the previous process is completed (step S1 ), the back surface of the substrate is ground (step S2 ). By reducing the thickness of the substrate in this step, it is possible to reduce the warpage of the substrate that occurred in the previous process, and realize the miniaturization of components.

A dicing process of grinding the backside of the substrate and dividing the substrate into a plurality of wafers is performed. And, a die bonding process (step S3 ) is performed in which each of the diced die is picked up, mounted and bonded to a lead frame. As the bonding method of the die and the lead frame in the die bonding process, an appropriate method can be selected according to the product. For example, resin or adhesive tape can be used for bonding. The bonding of the die and the lead frame in the die bonding process can be performed by mounting the die on an interposer. In a wire bonding process, the leads of the lead frame are electrically connected to the electrodes on the chip through thin metal wires (step S4 ). Silver wires or gold wires can be used as the thin metal wires. In addition, ball bonding or wedge bonding may be used for wire bonding.

A molding process of sealing the wire-bonded wafer with epoxy resin or the like is performed (step S5 ). By performing the molding process, the interior of the electronic component is filled with resin, which can protect the circuit part and metal thin wires installed inside the electronic component from mechanical external force, and can also reduce the deterioration of characteristics caused by moisture or dust. Next, electroplating is performed on the lead wires of the lead frame. Then, the lead wires are cut and formed (step S6 ). This plating process prevents the leads from being rusted, and when the leads are subsequently mounted on a printed circuit board, soldering can be performed more reliably. Next, printing processing (marking) is performed on the surface of the package (step S7). And the electronic component is completed (step S9 ) by the inspection step (step S8 ). By assembling the semiconductor device of the above-described embodiment, it is possible to provide a small electronic component with low power consumption.

Figure 16B shows a schematic perspective view of the completed electronic component. In FIG. 16B , a schematic perspective view of a QFP (Quad Flat Package: Quad Flat Package) is shown as an example of an electronic component. As shown in FIG. 16B , an electronic component 7000 includes a lead 7001 and a circuit portion 7003 . In the circuit unit 7003 , for example, the scan FF (SFF) of Embodiment 2 or other logic circuits are manufactured. The electronic component 7000 is mounted on, for example, a printed circuit board 7002 . By combining a plurality of such electronic components 7000 and electrically connecting them to each other on a printed circuit board 7002, the electronic components 7000 can be mounted on an electronic device. The completed circuit board 7004 is placed inside an electronic device or the like. For example, the electronic component 7000 can be used as a random memory for storing data or a processing unit such as a CPU, MCU (Micro Control Unit), FPGA, or wireless IC for performing various processes. By installing the electronic component 7000, the power consumption of the electronic device can be reduced. Alternatively, it is easy to miniaturize the electronic device.

Therefore, the electronic component 7000 can be used for electronic components (IC chips) of electronic devices in various fields such as digital signal processing, software-defined radio devices (software-defined radio devices), avionics (such as communication equipment, navigation systems, automatic driving systems ( autopilot systems), flight management systems and other aviation-related electronic devices), ASIC prototyping, medical image processing, speech recognition, ciphers, bioinformatics, simulators for mechanical devices, and radio waves in radio astronomy binoculars etc. As such an electronic device, a display device, a personal computer (PC) or an image reproduction device equipped with a storage medium (reproduction storage medium such as a digital audio-visual disc (DVD), a Blu-ray Disc (Blu-ray Disc), a flash memory , HDD, etc., and devices with a display unit for displaying images). In addition, examples of electronic devices that can use the electronic components according to one embodiment of the present invention include mobile phones, portable game machines, portable information terminals, e-book reader terminals, imaging devices (video cameras, digital cameras, etc.), wearable display devices (head-mounted, goggle type, glasses type, armband type, bracelet type, necklace type, etc.), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), Photocopiers, fax machines, printers, multi-function printers, automatic teller machines (ATMs) and vending machines, etc. Specific examples of these electronic devices are shown in FIGS. 17A to 17F .

The portable game machine 900 shown in FIG. 17A includes a casing 901, a casing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like.

The portable information terminal 910 shown in FIG. 17B includes a casing 911 , a casing 912 , a display portion 913 , a display portion 914 , a connection portion 915 , and operation keys 916 . The display portion 913 is provided in the casing 911 , and the display portion 914 is provided in the casing 912 . Moreover, the shell 911 and the shell 912 are connected by the connecting portion 915 , and the angle formed by the shell 911 and the shell 912 can be changed by the connecting portion 915 . Accordingly, the image displayed on the display unit 913 can also be switched according to the angle between the housing 911 and the housing 912 formed by the connecting portion 915 . In addition, a display device provided with a touch panel may be used as the display unit 913 and/or the display unit 914 .

A laptop personal computer 920 shown in FIG. 17C includes a casing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

The electric refrigerator-freezer 930 shown in FIG. 17D includes a casing 931 , a refrigerator door 932 , a freezer door 933 and the like.

A video camera 940 shown in FIG. 17E includes a casing 941, a casing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided in the housing 941 , and the display unit 943 is provided in the housing 942 . Also, the case 941 and the case 942 are connected by the connection part 946 , and the angle between the case 941 and the case 942 can be changed by the connection part 946 . The direction of the video displayed on the display unit 943 may be changed according to the angle formed by the housing 941 and the housing 942 , and the display/non-display of the video may be switched.

A car 950 shown in FIG. 17F includes a body 951, wheels 952, an instrument panel 953, lights 954, and the like.

Embodiment 4 In this embodiment mode, an oxide semiconductor, an OS transistor, and the like will be described.

＜＜Structure example 1 of OS transistor＞＞ 18A to 18D show an example of the structure of the OS transistor. FIG. 18A is a plan view showing an example of the structure of an OS transistor. FIG. 18B is a cross-sectional view between y1-y2, FIG. 18C is a cross-sectional view between x1-x2, and FIG. 18D is a cross-sectional view between x3-x4. Here, the direction of the line y1-y2 may be referred to as the channel length direction, and the direction of the line x1-x2 may be referred to as the channel width direction. That is, FIG. 18B is a diagram showing the cross-sectional structure of the OS transistor in the channel length direction, and FIGS. 18C and 18D are diagrams showing the cross-sectional structure of the OS transistor in the channel width direction. Note that some constituent elements are omitted in FIG. 18A in order to clearly show the device configuration.

The OS transistor 501 is formed on the insulating surface. Here, an OS transistor 501 is formed on an insulating layer 511 . The insulating layer 511 is formed on the surface of the substrate 510 . OS transistor 501 is covered with insulating layer 514 and insulating layer 515 . Note that the insulating layers 514 and 515 can also be regarded as constituent elements of the OS transistor 501 . The OS transistor 501 includes an insulating layer 512 , an insulating layer 513 , oxide semiconductor (OS) layers 521 to 523 , a conductive layer 530 , a conductive layer 541 and a conductive layer 542 . The insulating layer 513 includes a region serving as a gate insulating layer. The conductive layer 530 is used as a gate electrode. Here, the OS layer 521 , the OS layer 522 , and the OS layer 523 are collectively referred to as the OS layer 520 .

As shown in FIGS. 18B and 18C , the OS layer 520 includes a portion in which an OS layer 521 , an OS layer 522 , and an OS layer 523 are sequentially stacked. The insulating layer 513 covers this laminated portion. The conductive layer 531 overlaps the laminated portion via the insulating layer 513 . The conductive layer 541 and the conductive layer 542 are disposed on the stack formed by the OS layer 521 and the OS layer 523 , and are in contact with the top surface of the stack and the side surfaces in the channel length direction. In the example of FIGS. 18A to 18D , the conductive layers 541 and 542 are also in contact with the insulating layer 512 . The OS layer 523 is formed to cover the OS layers 521 and 522 and the conductive layers 541 and 542 . The bottom surface of the OS layer 523 is in contact with the top surface of the OS layer 522 .

In the OS layer 520 , a conductive layer 530 is formed so as to surround the laminated portion of the OS layers 521 to 523 in the channel width direction via the insulating layer 513 (see FIG. 18C ). Therefore, a gate electric field in the vertical direction and a gate electric field in the lateral direction are applied to the lamination portion. In the OS transistor 501 , the gate electric field refers to an electric field formed by a voltage applied to the conductive layer 530 (gate electrode layer). By utilizing the gate electric field, it is possible to electrically surround the entire lamination portion of the OS layers 521 to 523 , and thus a channel may be formed in the entire portion (in a block) of the OS layer 522 . Therefore, the OS transistor 501 can have a high on-state current.

In this specification, this kind of transistor structure that can be electrically surrounded by a gate electric field is called a "surrounded channel (s-channel)" structure. The OS transistor 501 has an s-channel structure. In the s-channel structure, a large current can flow between the source and the drain of the transistor, so the drain current (on-state current) in the on-state can be increased.

By making the OS transistor 501 have an s-channel structure, a gate electric field can also be applied to the side surface of the OS layer 522, thereby facilitating control of the channel formation region. A structure in which the conductive layer 530 extends below the OS layer 522 and faces the side surface of the OS layer 521 is preferable because controllability is further improved. As a result, the subthreshold swing value (S value) of the OS transistor 501 can be reduced, whereby the short channel effect can be suppressed. Therefore, this structure is suitable for miniaturization.

By adopting a three-dimensional device structure as the OS transistor 501, the channel length can be made below 100 nm. By miniaturizing the OS transistor, the circuit area can be reduced. The channel length of the OS transistor is preferably less than 65nm, more preferably less than 30nm or less than 20nm. It is sufficient that the channel length is at least 10 nm.

The conductor used as the gate of the transistor is called the gate electrode, the conductor used as the source of the transistor is called the source electrode, and the conductor used as the drain of the transistor is called the gate electrode. For the drain electrode, the region used as the source of the transistor is called the source region, and the region used as the drain of the transistor is called the drain region. In this specification, the gate electrode may be referred to as a gate, the drain electrode or a drain region may be referred to as a drain, and the source electrode or a source region may be referred to as a source.

For example, the channel length refers to the region where the semiconductor (or the part in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap or the source and The distance between the sink and pole. In addition, in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor is sometimes not limited to one value. Therefore, in this specification, the channel length is any value, maximum value, minimum value or average value in the area where the channel is formed.

For example, the channel width refers to the area where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or the area where the source and drain are opposite in the area where the channel is formed length. In addition, in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor is sometimes not limited to one value. Therefore, in this specification, the channel width is any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

In addition, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width) . For example, in a transistor with a three-dimensional structure, sometimes the effective channel width is greater than the apparent channel width shown in the top view of the transistor, and its influence cannot be ignored. For example, in a transistor having a microscopic and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In this case, the effective channel width obtained when the channel is actually formed is larger than the apparent channel width shown in the plan view.

In a transistor with a three-dimensional structure, it is sometimes difficult to estimate the effective channel width through actual measurement. For example, in order to estimate the effective channel width from the design value, the shape of the semiconductor needs to be known in advance as an assumption. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

Therefore, in this specification, the length of the part where the source electrode and the drain electrode are opposite in the area where the semiconductor and the gate electrode overlap in the top view of the transistor, that is, the apparent channel width is sometimes referred to as "surrounding channel width". (SCW: Surrounded Channel Width)". In addition, in this specification, when simply expressing "channel width", it may mean the surrounding channel width or the apparent channel width. Alternatively, in this specification, when simply expressing "channel width", the effective channel width may be indicated. Note that the values of channel length, channel width, effective channel width, apparent channel width, surrounding channel width, etc. can be determined by analyzing cross-sectional TEM images and the like.

In addition, when calculating the field effect mobility of the transistor, the current value per channel width, etc., calculations around the channel width are sometimes used. In this case, the value sometimes differs from the value when calculated using the effective channel width.

＜Substrate＞ The substrate 510 is not limited to a simple supporting material, and may also be a substrate on which other devices such as transistors are formed. At this time, any one of the conductive layer 530 , the conductive layer 541 and the conductive layer 542 of the OS transistor 501 may also be electrically connected to the above-mentioned other devices.

<Insulating Base Layer> The insulating layer 511 has a function of preventing impurities from diffusing from the substrate 510 . The insulating layer 512 preferably has a function of supplying oxygen to the OS layer 520 . Therefore, the insulating layer 512 preferably contains oxygen, and more preferably contains more oxygen than the stoichiometric ratio. For example, the insulating layer 512 releases oxygen molecules when the surface temperature of the film is 100° C. to 700° C. or 100° C. to 500° C. by thermal desorption spectroscopy (TDS: Thermal Desorption Spectroscopy). A film having an amount of 1.0×10 ¹⁸ [molecule/cm ³ ] or more. When the substrate 510 is a substrate on which other devices are formed, it is preferable to planarize the insulating layer 511 by using CMP (Chemical Mechanical Polishing) method or the like to make the surface flat.

Aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconia, lanthanum oxide, neodymium oxide, hafnium oxide can be used for the insulating layers 511 and 512 And insulating materials such as tantalum oxide, silicon nitride, aluminum oxynitride or their mixed materials.

＜Gate electrode＞ Conductive layer 530 is preferably copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni ), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt) and other metals, including Alloys of the above metals or compounds containing them as main components are formed.

The conductive layer 530 may have a single-layer structure or a stacked structure of two or more layers. Examples include a single-layer structure of an aluminum film containing silicon, a two-layer structure of laminating a titanium film on an aluminum film, a two-layer structure of laminating a titanium film on a titanium nitride film, and laminating a tungsten film on a titanium nitride film. A two-layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are sequentially laminated, a single-layer structure of a Cu-Mn alloy film, A two-layer structure in which a Cu film is stacked on a Cu-Mn alloy film, a three-layer structure in which a Cu-Mn alloy film, a Cu film, and a Cu-Mn alloy film are sequentially stacked, and the like. In particular, the Cu—Mn alloy film is preferable because it has low electrical resistance and forms manganese oxide at the interface with the insulating film containing oxygen to prevent diffusion of Cu.

The conductive layer 530 may also use indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, Light-transmitting conductive materials such as indium tin oxide added with silicon oxide. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

＜Gate insulating layer＞ The insulating layer 513 is formed using an insulating film having a single-layer structure or a stacked-layer structure. The insulating layer 513 can be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconia, lanthanum oxide, neodymium oxide, hafnium oxide and More than one insulating film in tantalum. The insulating layer 513 may also be a laminate of the above materials. In addition, the insulating layer 513 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities. The insulating layer 511 can also be formed in the same manner as the insulating layer 513 . The insulating layer 511 includes, for example, oxygen, nitrogen, silicon, hafnium and the like. Specifically, hafnium oxide and silicon oxide or hafnium oxide and silicon oxynitride are preferably included.

The relative permittivity of hafnium oxide is higher than that of silicon oxide or silicon oxynitride. Therefore, compared with the case where silicon oxide is used, the thickness of the insulating layer 513 can be increased, so that leakage current caused by tunneling current can be reduced. That is, a transistor with a small off-state current can be realized. Furthermore, the relative permittivity of hafnium oxide having a crystalline structure is higher than that of hafnium oxide having an amorphous structure. Therefore, in order to form a transistor with a small off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic crystal structure, a cubic crystal structure, and the like. Note that one embodiment of the present invention is not limited thereto.

<Source electrode, drain electrode, back gate electrode> The conductive layer 541 and the conductive layer 542 can also be formed in the same manner as the conductive layer 530 . The Cu—Mn alloy film has low electrical resistance, and by providing the Cu—Mn alloy film in contact with the oxide semiconductor film, manganese oxide can be formed at the interface with the oxide semiconductor film to prevent Cu from diffusing. Therefore, it is preferable to use a Cu—Mn alloy layer for the conductive layer 541 and the conductive layer 542 . A conductive layer 531 ( FIG. 20A ), which will be described later, can also be formed in the same manner as the conductive layer 530 .

＜Protective insulating film＞ The insulating layer 514 preferably has the function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals and the like. By providing the insulating layer 514 , oxygen can be prevented from diffusing from the OS layer 520 to the outside and hydrogen, water, and the like can be suppressed from entering the OS layer 520 from the outside. As the insulating layer 514, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, and the like. In addition, instead of the nitride insulating film having a blocking effect against oxygen, hydrogen, water, alkali metal, alkaline earth metal, etc., an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. As the oxide insulating film having a barrier effect against oxygen, hydrogen, water, etc., there are aluminum oxide film, aluminum oxynitride film, gallium oxide film, gallium oxynitride film, yttrium oxide film, yttrium oxynitride film, hafnium oxide film, etc. film, hafnium oxynitride film, etc.

The aluminum oxide film has a high barrier effect against the transmission of impurities such as hydrogen and moisture, and oxygen, so the aluminum oxide film is suitable for the insulating layer 514 . Therefore, the aluminum oxide film is suitably used as a protective film in the process of manufacturing the transistor and after manufacturing the transistor, which has the effect of preventing impurities such as hydrogen and moisture from being mixed into the OS layer 520 that cause changes in the electrical characteristics of the transistor; Oxygen, a main component of layer 520, is released from the oxide semiconductor; unnecessary release of oxygen from insulating layer 512 is prevented. Oxygen contained in the aluminum oxide film can also be diffused into the oxide semiconductor.

＜Interlayer insulation film＞ An insulating layer 515 is preferably formed on the insulating layer 514 . The insulating layer 515 may be formed using insulating films of a single-layer structure or a stacked-layer structure. As the insulating film, materials including magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. more than one insulating film.

<Oxide semiconductor layer> Typical semiconductor materials for the OS layers 521 to 523 are In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Ga, Y, Sn, Zr, La, Ce, or Nd, etc.). The element M is, for example, an element having a high bond energy with oxygen, the element M is, for example, an element having a higher bond energy with oxygen than indium, or the element M has a function of increasing the energy gap of an oxide semiconductor, for example. The OS layers 521 to 523 are not limited to oxide layers containing indium. The OS layers 521 to 523 can also be formed using, for example, Zn—Sn oxide, Ga—Sn oxide, Zn—Mg oxide, or the like. The OS layer 522 is preferably formed using In-M-Zn oxide. Both the OS layer 521 and the OS layer 523 can be formed using Ga oxide.

The OS layer 522 is not limited to an oxide semiconductor containing indium. The OS layer 522 may be, for example, an oxide semiconductor (for example, zinc tin oxide or gallium tin oxide) that does not contain indium but contains at least one of zinc, gallium, and tin.

The OS layer 522 can be formed using, for example, an oxide with a large energy gap. The energy gap of the OS layer 522 is, for example, not less than 2.5 eV and not more than 4.2 eV, preferably not less than 2.8 eV and not more than 3.8 eV, more preferably not less than 3 eV and not more than 3.5 eV.

The OS layer 522 is preferably, for example, a CAAC-OS film described later. Since an oxide semiconductor may be easily crystallized when Zn is contained, it is preferable that the OS layer 522 contains Zn.

When an interface level is formed at the interface between the OS layer 522 and the OS layer 521 , a channel region is also formed in a region near the interface, so the threshold voltage of the OS transistor 501 changes. Therefore, the OS layer 521 preferably contains at least one of the metal elements constituting the OS layer 522 as a constituent element. Therefore, it is difficult to form an interface energy level at the interface between the OS layer 522 and the OS layer 523 , and the deviation of the electrical characteristics such as the threshold voltage of the OS transistor 501 can be reduced.

The OS layer 523 preferably includes at least one of the metal elements constituting the OS layer 522 as a constituent element. Therefore, the interface scattering between the OS layer 522 and the OS layer 523 is not easy to occur, and the carrier migration is not easily hindered, so the field effect mobility of the OS transistor 501 can be improved.

The OS layer 521 , the OS layer 522 and the OS layer 523 preferably include at least indium. In addition, when the OS layer 521 is an In-M-Zn oxide, when the sum of In and M is 100atomic%, it is preferable that: In is lower than 50atomic%, and M is higher than 50atomic%, more preferably : In is lower than 25atomic%, M is higher than 75atomic%. In addition, when the OS layer 522 is an In-M-Zn oxide, when the sum of In and M is 100atomic%, it is preferable that: In is higher than 25atomic%, and M is lower than 75atomic%, more preferably : In is higher than 34atomic%, M is lower than 66atomic%. In addition, when the OS layer 523 is an In-M-Zn oxide, when the sum of In and M is 100atomic%, it is preferable that: In is lower than 50atomic%, and M is higher than 50atomic%, more preferably : In is lower than 25atomic%, M is higher than 75atomic%. In addition, the same kind of oxide as that of the OS layer 521 may be used for the OS layer 523 . Alternatively, the OS layer 521 and/or the OS layer 523 may not contain indium. For example, the OS layer 521 and/or the OS layer 523 may also be formed using a gallium oxide film.

Preferably, among the OS layers 521 to 523, the OS layer 522 has the highest carrier mobility. Thus, a channel may be formed in the OS layer 522 away from the insulating layer 511 .

For example, oxides containing In such as In—M—Zn oxides can increase carrier mobility by increasing the content of In. In In-M-Zn oxides, the s orbitals of heavy metals are mainly conducive to carrier conduction. By increasing the indium content to increase the overlap of the s orbitals, the mobility of oxides with more indium content is higher than that of indium. Oxides with less content are high. Therefore, by using an oxide having a high indium content for the oxide semiconductor film, carrier mobility can be improved.

When an oxide semiconductor film is formed by sputtering, since it is affected by heating or space heating of the substrate surface on which the oxide semiconductor film is formed, the composition of the target used as a source and the composition of the film may be different. different. For example, when an In-Ga-Zn oxide target is used, since zinc oxide sublimates more easily than indium oxide, gallium oxide, etc., a difference in composition between the source and the In-Ga-Zn oxide tends to occur. Specifically, the Zn content of the formed In-Ga-Zn oxide is less than that of the source. Therefore, it is preferable to select the source in consideration of the change in composition in advance. In addition, the difference in the composition of the source and the film is also affected by the pressure, the gas used for film formation, and the like in addition to the temperature.

When the OS layer 522 is In-M-Zn oxide formed by sputtering, the number of atoms of the metal element used to form the In-M-Zn oxide target is preferably In:M:Zn=1 :1:1, 3:1:2 or 4:2:4.1. For example, the atomic number ratio of metal elements contained in a semiconductor film formed using a target of In:M:Zn=4:2:4.1 is approximately In:M:Zn=4:2:3.

When the OS layer 521 and the OS layer 523 are In-M-Zn oxides formed by sputtering, the atomic number ratio of the metal elements used to form the In-M-Zn oxide target is In:M: Zn=1:3:2 or 1:3:4.

When the oxide semiconductor film is formed by sputtering, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be suitably used. As the sputtering gas, a rare gas (typically argon), an oxygen gas, and a mixed gas of a rare gas and an oxygen gas are suitably used. Furthermore, when a mixed gas of a rare gas and an oxygen gas is used, it is preferable to increase the ratio of the oxygen gas to the rare gas. In addition, the target material may be appropriately selected according to the composition of the oxide semiconductor to be formed.

In order to obtain an oxide semiconductor of high-purity nature or substantially high-purity nature, it is necessary not only to evacuate the processing chamber to a high vacuum, but also to highly purify the sputtering gas. As the oxygen gas or argon gas used for the sputtering gas, a high-purity gas having a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, further preferably -120°C or lower is used, This prevents moisture and the like from being mixed into the oxide semiconductor as much as possible.

＜Band structure＞ Next, the functions and effects of the OS layer 520 composed of a stack of the OS layer 521 , the OS layer 522 , and the OS layer 523 will be described with reference to the energy band diagram shown in FIG. 19B . FIG. 19A is an enlarged view of the channel region of the OS transistor 501, which is a partially enlarged view of FIG. 18B. FIG. 19B shows the energy band structure of a portion (the channel formation region of the OS transistor 501 ) between the dotted lines z1 - z2 in FIG. 19A . In the following, the OS transistor 501 is taken as an example for description, but the same applies to the OS transistors 502 to 506 .

In FIG. 19B , Ec512 , Ec521 , Ec522 , Ec523 , and Ec513 represent the conduction band bottom energies of insulating layer 512 , OS layer 521 , OS layer 522 , OS layer 523 , and insulating layer 513 , respectively.

Here, the energy difference between the vacuum level and the conduction band bottom (also called electron affinity) is the value obtained by subtracting the energy gap from the energy difference between the vacuum level and the valence band top (also called free potential). In addition, the energy gap can be measured with a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON). In addition, the energy difference between the vacuum level and the valence band top can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) device (VersaProbe manufactured by PHI Corporation).

Since the insulating layer 512 and the insulating layer 513 are insulators, Ec512 and Ec513 are closer to the vacuum energy level (lower electron affinity) than Ec521 , Ec522 and Ec523 .

The OS layer 522 is an oxide layer having higher electron affinity than the OS layer 521 and the OS layer 523 . For example, as the OS layer 522, an oxide having an electron affinity greater than that of the OS layer 521 and the OS layer 523 by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV is used. . Note that electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

When a voltage is applied to the gate (conductive layer 530 ) of the OS transistor 501 , a channel is formed in the OS layer 522 having the highest electron affinity among the OS layers 521 , 522 , and 523 .

InGaO has low electron affinity and high oxygen barrier property. Therefore, the OS layer 523 preferably includes InGaO. The ratio of gallium atoms [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more.

In addition, Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is preferably closer to the vacuum level than Ec522 by not less than 0.05 eV, not less than 0.07 eV, not less than 0.1 eV, or not less than 0.15 eV and not more than 2 eV, not more than 1 eV, not more than 0.5 eV, or not more than 0.4 eV.

In addition, Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is preferably closer to the vacuum level than Ec522 by not less than 0.05 eV, not less than 0.07 eV, not less than 0.1 eV, or not less than 0.15 eV and not more than 2 eV, not more than 1 eV, not more than 0.5 eV, or not more than 0.4 eV.

A mixed region of the OS layer 521 and the OS layer 522 may exist between the OS layer 521 and the OS layer 522 . In addition, there may be a mixed area between the OS layer 523 and the OS layer 522 between the OS layer 523 and the OS layer 522 . Since the interface state density in the mixed region is low, in the energy band structure of the stack of OS layers 521 to 523 (OS layer 520 ), the energy near each interface changes continuously (also referred to as continuous junction).

In the OS layer 520 having the above energy band structure, electrons mainly migrate in the OS layer 522 . Therefore, even if there are energy levels at the interface between the OS layer 521 and the insulating layer 512 or the interface between the OS layer 523 and the insulating layer 513, these interface energy levels are not easy to hinder electron migration in the OS layer 520, so that the OS transistor 501 can be increased. on-state current.

In addition, as shown in FIG. 19B, although trap levels Et 502 caused by impurities or defects may be formed near the interface between the OS layer 521 and the insulating layer 512 and near the interface between the OS layer 523 and the insulating layer 513, the OS layer 521 And the existence of the OS layer 523 can make the OS layer 522 away from the trap energy level Et502. In the OS transistor 501 , the top surface and side surfaces of the OS layer 522 are in contact with the OS layer 523 in the channel width direction, and the bottom surface of the OS layer 522 is in contact with the OS layer 521 (see FIG. 18C ). In this way, by adopting a structure in which the OS layer 522 is covered by the OS layer 521 and the OS layer 523 , the influence of the trap level Et502 can be further reduced.

Note that when the energy difference between Ec521 or Ec523 and Ec522 is small, electrons in the OS layer 522 may cross the energy difference and reach a trap level. When electrons are captured by the trap energy level, fixed negative charges are generated at the interface of the insulating film, causing the threshold voltage of the transistor to drift to the positive direction. Therefore, by setting the energy difference between Ec521 and Ec522 and the energy difference between Ec523 and Ec522 to be 0.1 eV or more, preferably 0.15 eV or more, the variation of the threshold voltage of the OS transistor 501 is suppressed, so that the OS transistor can be 501 is preferable because of its good electrical characteristics.

The more factors that hinder electron migration are reduced, the more the on-state current of the transistor can be increased. For example, it is assumed that electrons migrate efficiently when there are no factors that hinder electron migration. For example, when the physical unevenness in the channel region is large, electron migration is hindered. Or, for example, the hindrance of electron migration also occurs when the density of defect states in the channel region is high.

In order to increase the on-state current of the OS transistor 501, for example, the root mean square (RMS: Root-Mean -Square) roughness is lower than 1 nm, preferably lower than 0.6 nm, more preferably lower than 0.5 nm, further preferably lower than 0.4 nm. In addition, the average surface roughness (also referred to as Ra) in the range of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, further preferably less than 0.4 nm. The maximum height difference (also referred to as P-V) within the range of 1 μm×1 μm is lower than 10 nm, preferably lower than 9 nm, more preferably lower than 8 nm, further preferably lower than 7 nm.

For example, when the OS layer 522 has oxygen vacancies (also referred to as “V _O ”), a donor level may be formed because hydrogen enters the oxygen vacancy sites. Hereinafter, the state where hydrogen enters the oxygen-deficient site is sometimes referred to as "V _O H". Since V _O H scatters electrons, it causes a decrease in the on-state current of the transistor. In addition, oxygen-deficient sites will be more stable with oxygen ingress than hydrogen ingress. Therefore, by reducing oxygen vacancies in the OS layer 522, it is sometimes possible to increase the on-state current of the transistor. For example, in a certain depth of the OS layer 522 or in a certain region of the OS layer 522, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is 2×10 ²⁰ atoms/cm ³ or less, Preferably it is 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, still more preferably 5×10 ¹⁸ atoms/cm ³ or less.

In order to reduce oxygen vacancies in the OS layer 522 , for example, a method of moving excess oxygen contained in the insulating layer 512 to the OS layer 522 through the OS layer 521 is employed. In this case, the OS layer 521 is preferably an oxygen-permeable layer (a layer that allows oxygen to pass through).

When the OS transistor 501 has an s-channel structure, a channel may be formed in the entire portion of the OS layer 522 . The OS layer 522 may have a thickness of not less than 10 nm and not more than 100 nm, or not less than 10 nm and not more than 30 nm.

In addition, in order to increase the on-state current of the transistor, the thickness of the OS layer 523 may be reduced. For example, the OS layer 523 may have a region with a thickness of less than 10 nm, preferably less than 5 nm, more preferably less than 3 nm. On the other hand, the OS layer 523 has a function of blocking intrusion of elements other than oxygen (hydrogen, silicon, etc.) constituting an adjacent insulator into the OS layer 522 . Therefore, the OS layer 523 preferably has a certain thickness. For example, the OS layer 523 may have a region with a thickness of not less than 0.3 nm, preferably not less than 1 nm, more preferably not less than 2 nm. In addition, in order to suppress outward diffusion of oxygen released from the insulating layer 512 and the like, the OS layer 523 preferably has a property of blocking oxygen.

In addition, in order to improve reliability, it is preferable to make the OS layer 521 thick and make the OS layer 523 thin. For example, the OS layer 521 may have a thickness of, for example, not less than 10 nm, preferably not less than 20 nm, more preferably not less than 40 nm, and further preferably not less than 60 nm. By forming the OS layer 521 thick, the distance from the interface of the adjacent insulator and the OS layer 521 to the OS layer 522 where the channel is formed can be increased. Note that the OS layer 521 may have a thickness of, for example, 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less, because the productivity of the semiconductor device may decrease.

In order to impart stable electrical characteristics to an OS transistor whose channel is formed in an oxide semiconductor, it is effective to make the oxide semiconductor essentially or substantially essentially by reducing the impurity concentration in the oxide semiconductor. Here, "essentially" means that the carrier density of the oxide semiconductor is lower than 1×10 ¹⁷ /cm ³ , preferably lower than 1×10 ¹⁵ /cm ³ , more preferably lower than 1×10 ¹³ /cm ³ .

In addition, for oxide semiconductors, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are impurities. For example, hydrogen and nitrogen cause the formation of donor energy levels, which increases the carrier density. In addition, silicon causes the formation of impurity levels in the oxide semiconductor. This impurity level becomes a trap, which may degrade the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the OS layer 521 , the OS layer 522 , and the OS layer 523 or at each interface.

In order to make the oxide semiconductor essential or substantially essential, for example, the silicon concentration measured by SIMS analysis in a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor is lower than 1×10 ¹⁹ atoms/cm ³ , preferably lower than 5×10 ¹⁸ atoms/cm ³ , more preferably lower than 1×10 ¹⁸ atoms/cm ³ . In addition, for example, the hydrogen concentration in a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 5×10 ¹⁸ atoms/cm ³ or less. In addition, for example, the nitrogen concentration in a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor is lower than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor may decrease. In order to prevent the crystallinity of the oxide semiconductor from being lowered, for example, the concentration of silicon contained in a certain depth of the oxide semiconductor or a certain region of the oxide semiconductor is lower than 1×10 ¹⁹ atoms/cm ³ , preferably lower than 5×10 ¹⁸ atoms/cm ³ , preferably less than 1×10 ¹⁸ atoms/cm ³ . In addition, for example, the concentration of carbon contained in a certain depth of the oxide semiconductor or a certain region of the oxide semiconductor is lower than 1×10 ¹⁹ atoms/cm ³ , preferably lower than 5×10 ¹⁸ atoms/cm ³ , more preferably lower than Parts of 1×10 ¹⁸ atoms/cm ³ are sufficient.

In addition, the off-state current of the transistor using the above-mentioned highly purified oxide semiconductor in the channel formation region is extremely small. For example, the off-state current normalized by the channel width of the transistor when the source-drain voltage is about 0.1V, 5V or 10V can be reduced to several yA/μm to several zA/μm.

18A to 18D show an example in which the OS layer 520 has a three-layer structure, but are not limited thereto. For example, the OS layer 520 may also have a two-layer structure without the OS layer 521 or the OS layer 523 . Alternatively, any one of the oxide semiconductor layers shown as the OS layer 521, the OS layer 522, and the OS layer 523 may be provided above or below the OS layer 521 or above or below the OS layer 523. Four layers of structure. Alternatively, one or more oxide semiconductor layers shown as OS layers 521 to 523 are provided at two or more positions between arbitrary layers of the OS layer 520, above the OS layer 520, and below the OS layer 520. Layer n-layer structure (n is an integer greater than 5).

＜＜Structure example 2 of OS transistor＞＞ The OS transistor 502 shown in FIG. 20A is a modified example of the OS transistor 501 . The OS transistor 502 also has an s-channel structure like the OS transistor 501 . The differences between the OS transistor 502 and the OS transistor 501 are the conductive layer 541 and the shape of the conductive layer 542 and the conductive layer 531 disposed on the insulating layer 511 of the OS transistor 502 .

The conductive layer 531 is used as a back gate electrode. A constant potential, the same potential or signal as that of the conductive layer 530 , or a different potential or signal from the conductive layer 530 may be supplied to the conductive layer 531 . The conductive layer 541 and the conductive layer 542 are used as source electrodes or drain electrodes, respectively.

The conductive layer 541 and the conductive layer 542 of the OS transistor 502 are formed by a hard mask used to form a stack of the OS layer 521 and the OS layer 522 . Therefore, the conductive layer 541 and the conductive layer 542 do not have regions in contact with the side surfaces of the OS layer 521 and the OS layer 522 . For example, the OS layers 521 and 522 and the conductive layers 541 and 542 can be formed through the following processes. Two oxide semiconductor films constituting the OS layers 521 and 522 are formed. A single-layer or stacked conductive film is formed on the oxide semiconductor film. A hard mask is formed by etching the conductive film. A stack of the OS layer 521 and the OS layer 522 is formed by etching the two-layer oxide semiconductor film using this hard mask. Next, the conductive layer 541 and the conductive layer 542 are formed by etching the hard mask.

The conductive layer 531 may be used as a back gate electrode of the OS transistor 502 . The conductive layer 531 may also be provided in the OS transistor 501 shown in FIGS. 20A to 20C or the OS transistors 503 to 506 ( FIGS. 18A to 21B ) described later.

＜＜Structure examples 3 and 4 of OS transistors＞＞ The OS transistor 503 shown in FIG. 20B is a modified example of the OS transistor 501 , and the OS transistor 504 shown in FIG. 20C is a modified example of the OS transistor 502 . In the OS transistor 503 and the OS transistor 504 , the OS layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, the ends of the OS layer 523 and the insulating layer 513 are substantially aligned with the ends of the conductive layer 530 .

＜＜Structure examples 5 and 6 of OS transistors＞＞ The OS transistor 505 shown in FIG. 21A is a modified example of the OS transistor 501 , and the OS transistor 506 shown in FIG. 21B is a modified example of the OS transistor 502 . Both OS transistor 505 and OS transistor 506 include layer 551 between OS layer 523 and conductive layer 541 , and layer 552 between OS layer 523 and conductive layer 542 .

The layers 551 and 552 can be formed using, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor. The layers 551 and 552 can be formed using an n-type oxide semiconductor layer, or can be formed using a conductor layer whose resistance is higher than that of the conductive layers 541 and 542 . For example, as the layers 551 and 552, a layer containing indium, tin, and oxygen, a layer containing indium and zinc, a layer containing indium, tungsten, and zinc, a layer containing tin and zinc, a layer containing zinc and gallium, a layer containing A layer containing zinc and aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron, a layer containing tin and antimony, a layer containing tin and fluorine, a layer containing titanium and niobium, and the like. The layers listed above may also contain one or more of hydrogen, carbon, nitrogen, silicon, germanium, and argon.

The layers 551 and 552 may also have a property of transmitting visible light. In addition, the layers 551 and 552 may also have a property of not transmitting visible rays, ultraviolet rays, infrared rays, or X-rays by reflecting or absorbing them. When having such a property, it may be possible to suppress fluctuations in the electrical characteristics of the transistor caused by stray light.

As the layers 551 and 552 , it is preferable to use a layer that does not form a Schottky barrier with the OS layer 522 . Accordingly, the conduction characteristics of the OS transistors 505 and 506 can be improved.

The resistance of the layers 551 and 552 is preferably higher than that of the conductive layer 541 and the conductive layer 542 . Furthermore, the resistance of the layers 551 , 552 is preferably lower than the channel resistance of the OS transistors 505 , 506 . For example, the resistivity of the layers 551 and 552 is preferably not less than 0.1Ωcm and not more than 100Ωcm, not less than 0.5Ωcm and not more than 50Ωcm, or not less than 1Ωcm and not more than 10Ωcm. By setting the resistivities of the layers 551 and 552 within the above range, it is possible to relax the electric field concentration at the boundary between the channel and the drain. Therefore, variation in electrical characteristics of the transistor can be reduced. In addition, it is also possible to reduce the punch-through current caused by the electric field generated from the drain. Therefore, good saturation characteristics can also be achieved in transistors with short channel lengths. Note that in a circuit structure in which the source and drain of the OS transistors 505, 506 are not switched during operation, it is sometimes preferable to provide only one of layers 551 and 552 (for example, the layer on the drain side ).

＜<Wafer device structure example 1>> FIG. 22 shows an example of a device structure using a wafer composed of OS transistors and Si transistors. FIG. 22 is a diagram for explaining the stacked structure of PU 200 ( FIG. 13 ), and is a diagram describing more specifically the stacked structure of FIG. 14 . Note that FIG. 22 is not a diagram in which the wafer of PU 200 is cut along a specific cutting line.

The wafer is formed on a single crystal silicon wafer 270 . The FET layer 260 is provided with semiconductor elements such as Si transistors and capacitors constituting circuits other than the circuit RC50 . FIG. 22 typically shows a p-type Si transistor 271 and an n-type Si transistor 272 . The FET layer 260 is laminated with wiring layers W ₁ to W ₄ . _The wiring layer W4 is laminated with the FET layer 261 .

The FET layer 261 is a layer in which OS transistors, that is, transistors M1 to M3 are formed. Here, transistor M3 is typically shown. Transistors M1 and M2 have the same device structure as transistor M3. Here, the transistors M1 to M3 have the same structure as the OS transistor 504 (FIG. 20C). _In order to provide a back gate in the transistor M3, the wiring layer W4 is formed with a conductive layer 280.

Wiring layers W ₅ and W ₆ are stacked on the FET layer 261 , capacitor C11 is stacked on the wiring layer W ₆ , and wiring layers W ₇ and W ₈ are stacked on the capacitor C11 . The capacitor C11 includes conductive layers 281 , 282 and an insulating layer 284 . Here, the layer on which the conductive layer 281 is formed is used as a wiring layer. By stacking the capacitor C11 on the FET layer 261, the capacitance of the capacitor C11 can be easily increased. In addition, the capacitor C11 may be provided in the FET layer 261 although it varies depending on the magnitude of the capacitance of the capacitor C11 . In this case, two electrodes may be formed by using a conductive layer of the same layer as the source electrode and drain electrode of the transistor M3 and a conductive layer of the same layer as the gate electrode of the transistor M3. By disposing the capacitor C11 on the FET layer 261 , the number of manufacturing processes can be reduced, thereby reducing the manufacturing cost.

＜<Wafer device structure example 2>> Other FET layers in which OS transistors are formed may be stacked on the FET layer 261 . FIG. 23 shows an example of such a wafer having a three-dimensional device structure.

In the wafer of FIG. 23 , a capacitor C11 is formed on the FET layer 261 . Wiring layers W ₆ and W ₇ are laminated on the FET layer 261 . The FET layer 262 is laminated _on the wiring layer W7. The FET layer 262 is a layer in which OS transistors are fabricated. Transistor M80 is shown here. In order to provide a back gate in the transistor M80, a conductive layer 283 is formed _on the wiring layer W7.

Wiring layers W ₈ and W ₉ are laminated on the FET layer 262 . A capacitor layer 263 is stacked on the wiring layer _W9 . Wiring layers W ₁₀ and W ₁₁ are stacked on the capacitor layer 263 . The capacitance layer 263 is formed with a plurality of capacitors C80. For example, a transistor M80 and a capacitor C11 can be used to form a transistor-capacitor (1T1C) memory cell. Thus, a memory cell array can be stacked on the FET layer 261 .

In addition, the electrical characteristics of the OS transistors of the FET layer 261 and the OS transistors of the FET layer 262 may be made different. For example, the oxide semiconductor layer of the second layer of the OS transistor may be different. When the oxide semiconductor layer of the second layer is an In-Ga-Zn oxide formed by a sputtering method, targets having different In:Ga:Zn atomic number ratios may be used. For example, a target of In:Ga:Zn=1:1:1 is used as the transistor M3, and a target of In:Ga:Zn=4:2:4.1 is used as the transistor M80. Since the oxide semiconductor layer of the transistor M80 has a large In content, the mobility of the transistor M80 can be increased. On the other hand, since the In content of the oxide semiconductor layer of the transistor M3 is small, the mobility of the transistor M3 is lower than that of the transistor M80, but the off-state current of the transistor M3 is lower than that of the transistor M80.

As the insulator used for the wafers shown in Fig. 22 and Fig. 23, a compound selected from aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, An insulator made of one or more materials selected from yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. As the insulator, resins such as polyimide resins, polyamide resins, acrylic resins, silicone resins, epoxy resins, and phenolic resins can also be used. Note that in this specification, oxynitride refers to a compound having an oxygen content greater than that of nitrogen, and a nitrogen oxide refers to a compound having a nitrogen content greater than that of oxygen.

The insulating layers 291 to 295 preferably include at least one layer formed of an insulator having a blocking effect on hydrogen, water, and the like. Since water, hydrogen, etc. are one of the causes of generating carriers in the oxide semiconductor, by providing a barrier layer against hydrogen, water, etc., the reliability of the transistor M3 can be improved. Examples of insulators having a blocking effect on hydrogen, water, etc. include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttrium Stabilized zirconia (YSZ), etc.

＜＜Structure of Oxide Semiconductor＞＞ Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Non-single crystal oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor: c-axis aligned crystal oxide semiconductor), polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

In this specification, "parallel" means the state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, the state where this angle is -5 degrees or more and 5 degrees or less is also included. In addition, "substantially parallel" means a state where the angle formed by two straight lines is -30° or more and 30° or less. In addition, "perpendicular" means the state where the angle of two straight lines is 80 degrees or more and 100 degrees or less. Therefore, the state where this angle is 85 degrees or more and 95 degrees or less is also included. In addition, "approximately perpendicular" means a state where the angle formed by two straight lines is not less than 60° and not more than 120°. In addition, in this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

<CAAC-OS> CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals: c-axis aligned nanocrystals). CAAC-OS is one of oxide semiconductors including a plurality of c-axis aligned crystal parts (also referred to as grains).

In the composite analysis image (also called high-resolution TEM image) of CAAC-OS bright-field image and diffraction pattern obtained by observation with a transmission electron microscope (TEM: Transmission Electron Microscope), many particles were observed . However, in high-resolution TEM images, no clear boundaries between particles, that is, grain boundaries, can be observed. Therefore, it can be said that in CAAC-OS, reduction in electron mobility due to grain boundaries does not easily occur.

Note that when CAAC-OS is structurally analyzed by the out-of-plane method, a peak is sometimes observed around 2θ 36° in addition to the peak around 2θ 31°. A peak around 36° in 2θ means that a part of CAAC-OS contains crystals that do not have c-axis alignment. More preferably, when structural analysis is performed by the out-of-plane method, a peak appears around 2θ of 31° and no peak appears around 2θ of 36° in CAAC-OS.

When the structure of CAAC-OS was analyzed by the in-plane method in which X-rays were incident on the sample from a direction approximately perpendicular to the c-axis, a peak appeared around 56° in 2θ. This peak originates from the (110) plane of the InGaZnO ₄ crystal. In CAAC-OS, no clear peak was observed even when the analysis (Φ-scan) was performed with the sample rotated around the normal vector of the sample surface (Φ-axis) while fixing 2θ at around 56°. In contrast, in the single-crystal oxide semiconductor of InGaZnO ₄ , when Φ scanning was performed with 2θ fixed at around 56°, six peaks originating from crystal planes equivalent to the (110) plane were observed. Therefore, it was confirmed from structural analysis using XRD that the alignment of the a-axis and the b-axis in CAAC-OS is not regular.

In addition, CAAC-OS is an oxide semiconductor with a low density of defect states. Defects in the oxide semiconductor include, for example, defects due to impurities, oxygen defects, and the like. Therefore, CAAC-OS can be called an oxide semiconductor with a low impurity concentration or an oxide semiconductor with few oxygen defects. Impurities contained in oxide semiconductors may become carrier traps or carrier generation sources. In addition, oxygen vacancies in oxide semiconductors may serve as carrier traps or as a source of carrier generation by trapping hydrogen.

In addition, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, elements such as silicon, which have a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor, deprive oxygen in the oxide semiconductor, thereby disrupting the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity. In addition, since heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), the atomic arrangement of the oxide semiconductor is disturbed, resulting in a decrease in crystallinity.

An oxide semiconductor having a low density of defect states (few oxygen defects) can have a low carrier density. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The impurity concentration and defect state density of CAAC-OS are low. That is, CAAC-OS tends to be an oxide semiconductor of high-purity nature or substantially high-purity nature. Therefore, transistors using CAAC-OS seldom have the electrical characteristics of a negative threshold voltage (rarely become normally on). An oxide semiconductor having a high-purity nature or a substantially high-purity nature has few carrier traps. Therefore, transistors using CAAC-OS have little variation in electrical characteristics and high reliability. Due to the low density of defect states in CAAC-OS, few carriers generated by light irradiation etc. are captured by defect levels. Therefore, in a transistor using CAAC-OS, there is little variation in electrical characteristics due to irradiation of visible light or ultraviolet light.

Charges trapped by carrier traps of oxide semiconductors take a long time to be released and sometimes act like fixed charges. Therefore, a transistor using an oxide semiconductor having a high impurity concentration and a high defect state density may have unstable electrical characteristics.

＜Microcrystalline Oxide Semiconductor＞ In the high-resolution TEM image of a microcrystalline oxide semiconductor, there are regions where crystal parts can be observed and regions where clear crystal parts are not observed. The crystal portion contained in the microcrystalline oxide semiconductor often has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, a nanocrystalline oxide semiconductor including microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm is called nc-OS (nanocrystalline oxide semiconductor). For example, in high-resolution TEM images of nc-OS, sometimes grain boundaries cannot be clearly observed. Note that the origin of the nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystalline portion of nc-OS may be referred to as a particle below.

In nc-OS, the arrangement of atoms in a minute region (for example, a region between 1 nm and 10 nm, particularly a region between 1 nm and 3 nm) has periodicity. In addition, no regularity of crystallographic orientation was observed among different particles in nc-OS. Therefore, no alignment was observed in the entire portion of the film. Therefore, sometimes nc-OS does not differ from amorphous oxide semiconductors in some analytical methods. For example, when the structure of nc-OS is analyzed by an out-of-plane method using an XRD apparatus using X-rays whose beam diameter is larger than that of particles, peaks indicating crystallographic planes cannot be detected. When nc-OS is electron-diffraction (selected-area electron diffraction) using an electron beam whose beam diameter is larger than that of the particles (for example, 50 nm or more), a diffraction pattern similar to a halo pattern is observed. On the other hand, when nc-OS is subjected to nanobeam electron diffraction using electron rays whose beam diameter is close to that of the particles or smaller than the particles, spots are observed. In addition, in the nanobeam electron diffraction pattern of nc-OS, a circle-like (circular) high brightness region may be observed. Furthermore, in the nanobeam electron diffraction pattern of nc-OS, many spots in the annular region may be observed.

In this way, since there is no regularity in the crystallographic orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC ( Non-Aligned nanocrystals: oxide semiconductors without alignment nanocrystals.

nc-OS is an oxide semiconductor whose regularity is higher than that of an amorphous oxide semiconductor. Therefore, the defect state density of nc-OS is lower than that of amorphous oxide semiconductor. However, no regularity of crystal alignment was observed among different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

＜Amorphous Oxide Semiconductor＞ The amorphous oxide semiconductor is an oxide semiconductor in which the arrangement of atoms in a film is irregular and does not have a crystal portion. An example thereof is an oxide semiconductor having an amorphous form such as quartz. No crystal part can be observed in the high-resolution TEM image of the amorphous oxide semiconductor. When the structure of an amorphous oxide semiconductor is analyzed by an out-of-plane method using an XRD device, no peaks indicating crystal planes can be detected. When electron diffraction is performed on an amorphous oxide semiconductor, a halo pattern is observed. When nanobeam electron diffraction is performed on an amorphous oxide semiconductor, no spots but only halo patterns are observed.

There are various opinions on the amorphous structure. For example, a structure in which the arrangement of atoms is completely irregular is sometimes called a completely amorphous structure. The following structure is also sometimes called an amorphous structure: although it is not a long-range order, it can have a regular structure in the range from a certain atom to the nearest atom or the second closest atom. Therefore, according to the strictest definition, an oxide semiconductor having even a slight regularity of atomic arrangement cannot be called an amorphous oxide semiconductor. At least an oxide semiconductor with long-range order cannot be called an amorphous oxide semiconductor. Therefore, for example, CAAC-OS and nc-OS cannot be called amorphous oxide semiconductors or complete amorphous oxide semiconductors because they have crystal parts.

＜amorphous-like oxide semiconductor＞ Note that an oxide semiconductor sometimes has a structure intermediate between nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like oxide semiconductor).

Voids are sometimes observed in high-resolution TEM images of a-like OS. In addition, in the high-resolution TEM image, a region where the crystal part can be clearly observed and a region where the crystal part cannot be observed are included. Since a-like OS contains holes, its structure is unstable. In addition, since a-like OS contains cavities, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of that of a single crystal oxide semiconductor having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of that of a single crystal oxide semiconductor having the same composition. Note that it is difficult to form an oxide semiconductor whose density is less than 78% of that of a single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor whose atomic ratio satisfies In:Ga:Zn=1:1:1, the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in the case of an oxide semiconductor whose atomic number ratio satisfies In:Ga:Zn=1:1:1, the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ³ . In addition, for example, in the case of an oxide semiconductor whose atomic number ratio satisfies In:Ga:Zn=1:1:1, the density of nc-OS and the density of CAAC-OS are 5.9 g/cm ³ or more and less than 6.3 g /cm ³ .

Sometimes there is no single crystal oxide semiconductor of the same composition. At this time, by combining single crystal oxide semiconductors having different compositions in arbitrary ratios, the density of single crystal oxide semiconductors corresponding to a desired composition can be estimated. The density of single crystal oxide semiconductors corresponding to a desired composition may be calculated using a weighted average from the combination ratio of single crystal oxide semiconductors having different compositions. It is preferable to calculate the density by reducing the types of single crystal oxide semiconductors combined as much as possible.

Oxide semiconductors have various structures and various characteristics. For example, the semiconductor region of the OS transistor may be a stacked film including two or more of amorphous oxide semiconductor, a-like OS, microcrystalline oxide semiconductor, and CAAC-OS.

10: circuit 11: scanning flip-flop (SFF) 15: circuit 20: selection circuit 21: selection circuit (SEL) 30: circuit 31: flip-flop (FF) 31a: circuit 32M: latch 32S: latch 42: Inverter 43: Inverter 44: Inverter 45: Buffer (BUF) 50: SFF 100: Logic Circuit 101: Logic Circuit 102: Logic Circuit 103: Logic Circuit 110: SFF 112: SFF 113: SFF 114: SFF 115: SFF 116: SFF 200: PU 201: processor core 202: power management unit (PMU) 203: power switch (PSW) 204: clock control circuit 205: circuit 210: power circuit 220: terminal 221: Terminal 222: terminal 231: control device 232: program counter 233: pipeline register 234: pipeline register 235: register file 236: arithmetic logic arithmetic unit (ALU) 237: data bus 240: logic circuit 250: SFF 260: FET layer 261: FET layer 262: FET layer 263: capacitance layer 270: single crystal silicon wafer 271: p-type Si transistor 272: n-type Si transistor 280: conductive layer 281: conductive layer 282: conductive layer 283: conductive layer 284: insulating layer 291: insulating layer 292: insulating layer 293: insulating layer 294: insulating layer 295: insulating layer 501: OS transistor 502: OS transistor 503: OS transistor 504: OS transistor 505: OS transistor 506: OS transistor 510: substrate 511: insulating layer 512: insulating layer 513: insulating layer 514: insulating layer 515: insulating layer 520: OS layer 521: OS layer 522: OS layer 523: OS layer 530: conductive Layer 531: conductive layer 541: conductive layer 542: conductive layer 551: layer 552: layer 900: portable game machine 901: casing 902: casing 903: display part 904: display part 905: microphone 906: speaker 907: operation keys 908: touch pen 910: portable information terminal 911: shell 912: shell 913: display part 914: display part 915: connection part 916: operation key 920: laptop personal computer 921: shell 922: display part 923: Keyboard 924: pointing device 930: electric refrigerator-freezer 931: casing 932: refrigerator door 933: freezer door 940: video camera 941: casing 942: casing 943: display part 944: operation key 945: lens 946: connection part 950 : Automobile 951: Body 952: Wheel 953: Instrument panel 954: Lamp 7000: Electronic component 7001: Lead wire 7002: Printed circuit board 7003: Circuit part 7004: Circuit board BK: Terminal C1: Capacitor C11: Capacitor C12: Capacitor C80: Capacitor CK: terminal CK1: terminal CKB1: terminal D: terminal D0: terminal D1: terminal D2: terminal D3: terminal Dn: terminal EN: terminal FN: node FN11: node M1: transistor M2: transistor M3: transistor M80 : Transistor OBG: Terminal PL: Terminal Q: Terminal QB: Terminal RC1: Circuit RC2: Circuit RC3: Circuit RC4: Circuit RC11: Circuit RC12: Circuit RC13: Circuit RC14: Circuit RC15: Circuit RC16: Circuit RC50: Circuit RE: Terminal RT: Terminal SD: Terminal SD_IN: Terminal SE: Terminal SW1: Switch SW2: Switch SW3: Switch T0: Terminal T1: Terminal T2: Terminal VH: Terminal VL: Terminal W ₁ : Wiring layer W ₂ : Wiring layer W ₃ : Wiring layer W ₄ : Wiring layer W ₅ : Wiring layer W ₆ : Wiring layer W ₇ : Wiring layer W ₈ : Wiring layer W ₉ : Wiring layer W ₁₀ : Wiring layer W ₁₁ : Wiring layer

In the schema: FIG. 1A is a block diagram showing a structural example of a logic circuit, and FIG. 1B is a block diagram showing a structural example of the circuit 10 of FIG. 1A; 2A and 2B are block diagrams showing structural examples of logic circuits; 3 is a block diagram showing a structural example of a logic circuit; FIG. 4 is a circuit diagram showing a structural example of a scan FF (SFF); FIG. 5 is a circuit diagram showing a structural example of the SFF; FIG. 6 is a timing diagram showing an example of the operation of SFF; FIG. 7 is a timing diagram showing an example of the operation of SFF; FIG. 8 is a circuit diagram showing a structural example of the SFF; FIG. 9 is a circuit diagram showing a structural example of the SFF; FIG. 10 is a circuit diagram showing a structural example of the SFF; FIG. 11 is a circuit diagram showing a structural example of the SFF; FIG. 12 is a circuit diagram showing a structural example of the SFF; Fig. 13 is a block diagram showing a structural example of a processing device; Fig. 14 is a block diagram showing a structural example of a processor core; FIG. 15 is a diagram showing a device structure of SFF; 16A is a flow chart showing an example of a manufacturing method of an electronic component, and FIG. 16B is a schematic perspective view showing a structural example of an electronic component; 17A to 17F are diagrams illustrating examples of electronic devices; 18A is a top view showing a structural example of a transistor, and FIGS. 18B to 18D are cross-sectional views of the transistor of FIG. 18A; Fig. 19A is a partially enlarged view of the transistor of Fig. 18B, and Fig. 19B is an energy band diagram of the transistor; 20A to 20C are cross-sectional views showing structural examples of transistors; 21A and 21B are cross-sectional views showing structural examples of transistors; 22 is a cross-sectional view showing a structural example of a wafer; Fig. 23 is a cross-sectional view showing a structural example of a wafer.

none

21:Select circuit

31: flip-flop

SFF110: Scanning flip-flops

SFF11: Scanning flip-flops

RC11: Circuit

C11: Capacitor

FN11: Node

M1~M3: Transistor

SD_IN, RE, BK, PL, SD, D, SE, CK, Q: terminals

Claims (4)

A semiconductor device comprising: a logic circuit; and a holding circuit having a function of holding data output from the logic circuit and a function of outputting the held data to the logic circuit, wherein the data output from the holding circuit to the logic circuit The data is the same logic data as the data output from the logic circuit to the holding circuit. The holding circuit includes first to third transistors and elements for holding data. The output terminal of the logic circuit is connected by the second transistor It is electrically connected with the element holding data, the element holding data is electrically connected with the input terminal of the logic circuit through the third transistor, and the input terminal of the holding circuit is connected with the input terminal of the logic circuit through the first transistor Input terminals are electrically connected, a first layer and a second layer are stacked, one of the elements included in the logic circuit is included in the first layer, and one of the elements included in the holding circuit is included in the second layer one of. A semiconductor device comprising: a logic circuit; and a holding circuit having a function of holding data output from the logic circuit and a function of outputting the held data to the logic circuit, wherein the data output from the holding circuit to the logic circuit The data is the same logical data as the data output from the logic circuit to the holding circuit, and the holding circuit includes first to third transistors and elements for holding data, The output terminal of the logic circuit is electrically connected to the element holding data through the second transistor, the element holding data is electrically connected to the input terminal of the logic circuit through the third transistor, and the input terminal of the holding circuit By electrically connecting the first transistor to the input terminal of the logic circuit, a first layer and a second layer are laminated, the first layer is observed in section to form elements constituting the logic circuit, and the second layer The elements constituting the holding circuit are observed in section. A semiconductor device comprising: a logic circuit; and a holding circuit having a function of holding data output from the logic circuit and a function of outputting the held data to the logic circuit, wherein the data output from the holding circuit to the logic circuit The data is the same logic data as the data output from the logic circuit to the holding circuit. The holding circuit includes first to third transistors and elements for holding data. The output terminal of the logic circuit is connected by the second transistor It is electrically connected with the element holding data, the element holding data is electrically connected with the input terminal of the logic circuit through the third transistor, and the input terminal of the holding circuit is connected with the input terminal of the logic circuit through the first transistor The input terminal is electrically connected, the first layer and the second layer are stacked, the first layer is viewed in cross-section including the transistor included in the logic circuit, and the second layer is viewed in cross-section to constitute the elements constituting the holding circuit . A semiconductor device according to any one of items 1 to 3 of the patent application, Wherein, the logic circuit is a latch, flip-flop, shift register, counting circuit or frequency dividing circuit.

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