JPS60214629A - Analog signal selecting circuit - Google Patents

Analog signal selecting circuit

Info

Publication number
JPS60214629A
JPS60214629A JP7130384A JP7130384A JPS60214629A JP S60214629 A JPS60214629 A JP S60214629A JP 7130384 A JP7130384 A JP 7130384A JP 7130384 A JP7130384 A JP 7130384A JP S60214629 A JPS60214629 A JP S60214629A
Authority
JP
Japan
Prior art keywords
analog
signal
analog signal
input terminal
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7130384A
Other languages
Japanese (ja)
Inventor
Isao Sasao
笹尾 勇夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7130384A priority Critical patent/JPS60214629A/en
Publication of JPS60214629A publication Critical patent/JPS60214629A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means

Abstract

PURPOSE:To transmit accurately a selected analog signal while removing the influence of a leak current when an analog switch is turned off by providing a leading-out means which leads another unselected analog signal to an earth side when the analog signal is selected. CONSTITUTION:For example, an ''H'' signal is applied to a control signal input terminal 41 and an ''L'' signal is supplied to a control signal input terminal 42. Then, a transistor (TR)72A turns on through a resistor 72B once an internal switch 11 is turned on, so an input terminal I2 of an analog multiplier 1 is clamped at the on voltage of the TR72A. A terminal 42, on the other hand, is at ''L'', so an internal switch 12 turns off and TR71A also turns on. When the terminal 41 is at ''L'' and the terminal 42 is at ''H'', on the other hand, the switch 11 is off, TR71A on, switch 12 on, and TR72A is off. Consequently, the leak current between the inut and output in the off state becomes extremely small and an offset voltage is not influenced by the input voltages.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は牛導体アナログマルチプレクサを利用して、
複数のアナログ信号をディジタル信号に変換する回路に
督けるアナログ伯′号選択回路に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention utilizes a conductor analog multiplexer to
The present invention relates to an analog signal selection circuit that can be used in a circuit that converts a plurality of analog signals into digital signals.

〔従来技術〕[Prior art]

第3図は例えば[アナログ回路のトラブル対策、P25
B、図9.35(OQ出版社)」に示された従来のアナ
ログ信号選択回路であり、図において(1)は選択信号
にて0N−OFF動作する内部スイッチQll 、 f
121−i5内蔵したアナログマ“ルチプレクサ、12
1) 、 glは抵抗器t811.t321を介して上
記内部スイッチ011 、 (12)ヘアナログ信号を
印加するデータ入力端子を示す。しかして、田)、嘔1
はそれぞれ上記内部スイッチαη、 (121を閉成せ
しめてアナログ信号を選択しアナログマルチプレクサ(
1)より出力させる制御入力端子、(5)はアナログマ
ルチプレクサ(1)より出力されたアナログ信号をA/
D変換器(6)へ送出するボルテージフォロア回路であ
る。なお、1811.132)は電流制限抵抗器である
Figure 3 is an example of [Troubleshooting for analog circuits, p. 25]
This is a conventional analog signal selection circuit shown in Figure 9.35 (OQ Publishing), in which (1) is an internal switch Qll, f that operates ON-OFF in response to a selection signal.
121-i5 built-in analog multiplexer, 12
1), gl is resistor t811. t321 indicates a data input terminal that applies an analog signal to the internal switch 011 (12). However, Ta), O 1
respectively close the internal switches αη and (121) to select an analog signal and connect the analog multiplexer (
1) is a control input terminal that outputs the analog signal from the analog multiplexer (1), and (5) is the analog signal output from the analog multiplexer (1).
This is a voltage follower circuit that sends out data to the D converter (6). Note that 1811.132) is a current limiting resistor.

上記構成を備える従来のアナログ信号選択回路の動作例
を説明する。データ入力端子(21)と映に印加されて
いるアナログ信号の内例えばデータ入力端子(21)に
加えられているアナログ信号を選択し出力する場合、ハ
イレベル電圧の選択信号を制御信号入力端子世)より入
力端子C工を介して内部スイッチ(11)へ加える。そ
の結果内部スイッチ(121は閉成されデータ入力端子
(21)に印加されているアナログ信号は内部スイッチ
01)を通じて出力端子02へ出力される。次に該アナ
ログ1h号はボルテージフォロア回路(6)を介してA
 / D変換器(6)へ送出されディジタル値に変換さ
れる0崗、上記例では制御1ろ号入力端子囮へローレベ
ル電圧の選択信号が印加されている為内部スイッチ(1
2)は開成されているものと仮定する。
An example of the operation of a conventional analog signal selection circuit having the above configuration will be described. For example, when selecting and outputting an analog signal applied to the data input terminal (21) from among the analog signals applied to the data input terminal (21) and the control signal input terminal, a high-level voltage selection signal is applied to the control signal input terminal. ) to the internal switch (11) via input terminal C. As a result, the internal switch (121) is closed and the analog signal applied to the data input terminal (21) is outputted to the output terminal 02 through the internal switch 01. Next, the analog 1h is connected to A via the voltage follower circuit (6).
/ D converter (6) and converted into a digital value. In the above example, since a low level voltage selection signal is applied to the control 1 input terminal decoy, the internal switch (1
2) is assumed to have been developed.

続いて、データ入力端子(〃)に印加されているアナロ
グ信号を選択する場合には、制御信号入力端子t4i1
+ヲハイレベル電圧よりローレベル電圧へ切り替え、一
方制御信号入力端子嘔1をローレベル電圧よりハイレベ
ル電圧へ切り替えることで内部スイッチσ1)が開成さ
れると共に内部スイッチ(12)は閉成され、その結果
データ入力端子幽)に印加されたアナログ信号が内部ス
イッチ(121を介して出力端子02に出力され、ボル
テージフォロア回路(5)を通してA / D変換器(
6)へ送られ、ディジタル値に変換される。このように
選択信号に基づいて複数のアナログ信号より一つずつア
ナログ信号を切り替え辿択し、出力して順次A / D
変換する。
Next, when selecting the analog signal applied to the data input terminal (〃), the control signal input terminal t4i1
By switching + from high level voltage to low level voltage, and on the other hand switching control signal input terminal 1 from low level voltage to high level voltage, internal switch σ1) is opened and internal switch (12) is closed. The analog signal applied to the data input terminal 02 is outputted to the output terminal 02 via the internal switch 121, and is passed through the voltage follower circuit 5 to the A/D converter 02.
6) and converted into a digital value. In this way, analog signals are switched one by one from multiple analog signals based on the selection signal, outputted, and sequentially A/D.
Convert.

上記のように複数のアナログ信号より一つずつ信号を切
り替え順次ディジタル値に変換する場合、A / D変
換器(6)の前段にアナログマルチプレクサよりなるア
ナログ信号選択回路を備えることで、複数のアナログ信
号であっても単一のA/Di換器(6)にて順次A /
 D変換が可能となる。
As mentioned above, when switching signals one by one from multiple analog signals and converting them into digital values sequentially, by providing an analog signal selection circuit consisting of an analog multiplexer in the front stage of the A/D converter (6), it is possible to convert multiple analog signals one by one. Even if it is a signal, a single A/Di converter (6) sequentially converts A /
D conversion becomes possible.

しかしながら上述のようなアナログマルチプレクサ(1
)は内部スイッチQ”l + (12)が半導体で構成
されている為、例えば内部スイッチα1)がON状悪で
あり、一方、内部スイッチ(121がOFF状態の時、
内部スイッチ(121がOFF状態であっても該内部ス
イッチ(121の入出力間にリーク電流が流れ、このた
め内部スイッチα1)側のアナログ信号を正個に伝達で
きない場合がある。例えば、データ入力端子(21)に
QV、データ入力端子(2))に+IOVのアナログ信
号が印加され、内部スイッチ0刀がON、内部スイッチ
(援がOFFとして、抵抗器!81)がIOKΩである
場合に、内部スイッチ(121のリーク電流が1μAと
すると、この場合、内部スイッチ(誠のリーク電 5− 流が内部スイッチ01)−抵抗器(81)−データ入力
端子(211と流れ、抵抗器(81)の両端に1μAX
IOKΩ=lQmVの電圧降下が生じる。従って、ボル
テージフォロア回路(5)の入力にはlQmVの電圧が
印刀口されたことになる(以下、リーク電流により生じ
る電圧をオフセット電圧と称す)0 データ入力端子(211に印加される電圧がオフセット
電圧に較べ十分高い場合は回路誤差として問題にしなく
ても良いが微小電圧の場合問題となる。
However, the analog multiplexer (1
), the internal switch Q"l + (12) is composed of a semiconductor, so for example, when the internal switch α1) is in an ON state, and on the other hand, the internal switch (121) is in an OFF state,
Even if the internal switch (121) is in the OFF state, a leakage current flows between the input and output of the internal switch (121), so that the analog signal on the internal switch α1 side may not be transmitted correctly.For example, when the data input When an analog signal of QV is applied to the terminal (21) and +IOV is applied to the data input terminal (2)), the internal switch 0 is ON, and the internal switch (with the support OFF and the resistor !81) is IOKΩ, Assuming that the leakage current of the internal switch (121) is 1 μA, in this case, the leakage current of the internal switch (Makoto's leakage current is 5- current is internal switch 01) - resistor (81) - data input terminal (211), and the current flows from resistor (81). 1μAX on both ends of
A voltage drop of IOKΩ=1QmV occurs. Therefore, a voltage of 1QmV is applied to the input of the voltage follower circuit (5) (hereinafter, the voltage generated by leakage current is referred to as an offset voltage). If the voltage is sufficiently high compared to the voltage, there is no need to consider it as a circuit error, but if the voltage is very small, it becomes a problem.

すなわち、前述の例では、データ入力端子(21)にl
QmVの電圧を印加した場合、ボルテージフォロア回路
(5)の入力にはオフセット電圧外10mVが加算され
ほぼ2倍の20 mVの電圧が印加される。オフセット
を圧が一定であればA / D変換後の処理により補正
するか又はアナログ信号切換回路にオフセット補正回路
を付加することでオフセラ) %圧補正が容易である。
That is, in the above example, l is connected to the data input terminal (21).
When a voltage of QmV is applied, 10 mV in addition to the offset voltage is added to the input of the voltage follower circuit (5), and a voltage of 20 mV, which is approximately twice that, is applied to the input of the voltage follower circuit (5). If the pressure is constant, the offset can be easily corrected by processing after A/D conversion or by adding an offset correction circuit to the analog signal switching circuit.

しかしアナログスイッチのリーク電流はデータ入力端子
に印加された入力電圧によシ変化するため、従来の回路
においては微小電圧を取扱う場合に個入力の電圧に応じ
 6− たオフセット補正を行なわなければ正確にアナログ信号
をA/D変換ができないという問題を有していた。
However, the leakage current of an analog switch changes depending on the input voltage applied to the data input terminal, so when dealing with minute voltages in conventional circuits, it is difficult to accurately measure the leakage current unless offset correction is performed according to the voltage of each input. However, there was a problem in that analog signals could not be A/D converted.

〔発明の概要〕[Summary of the invention]

この発明は従来の欠点を解消するもので、オフセット電
圧の減少、及び、オフセット電圧が他のデータ入力端子
に印加された電圧値に影響されないアナログ信号選択回
路を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to overcome the conventional drawbacks and to provide an analog signal selection circuit in which the offset voltage is reduced and the offset voltage is not affected by voltage values applied to other data input terminals.

〔発明の実施例〕[Embodiments of the invention]

以下、第1図によりこの発明の一実施例を説明する。第
6図と同符号は同−又は相当部分を示す0σ1)はデー
タ入力端子(工、)の入力信号クランプ回路、問はデー
タ入力端子(工2)の入力信号クランプ回路で、このク
ランプ回路は、それぞれトランジスタ(71A)、 (
72A)と、そのペース抵抗器(71B) 。
An embodiment of the present invention will be described below with reference to FIG. The same reference numerals as in Fig. 6 indicate the same - or equivalent parts. 0σ1) is the input signal clamp circuit of the data input terminal (D), the question is the input signal clamp circuit of the data input terminal (D), and this clamp circuit is , respectively transistor (71A), (
72A) and its pace resistor (71B).

(72B)、及びベース・エミッタ間に挿入された抵抗
器(71c)、 (72c)を備えて成る0次にこの実
施例の動作を説明する。今、制御信号入力端子141)
に% HII倍信号+電圧)を印加し、制御信号入力端
子鴎1にはゝゝL〃信号(ユOv)が与えられたものと
する。制御信号入力端子間がXXH//に力ると、内部
スイッチ(11)がONすると同時に、抵抗器(72B
)を通してトランジスタ(72A)がONになるため、
アナログマルチプレクサ(1)の入力端子(工2)はト
ランジスタ(72A)のON電圧(二□v)にクランプ
される。一方、開側1信号入力端子嘔(はst L /
7となっているため、内部スイッチ(121はOFFと
々す、トランジスタ(71A)もOFF’となる。又、
制御信号入力端子間がゝゝL〃、制御信号入力端子□□
□(がSS H//の場合には、上記とは逆にスイッチ
(11)はOFF、)ランジスタ(7+A)はON、内
部スイッチ(廟はON、トランジスタ(72A)はOF
Fとなる。
(72B) and resistors (71c) and (72c) inserted between the base and emitter. Now, control signal input terminal 141)
It is assumed that %HII multiplied signal + voltage) is applied to the control signal input terminal 1, and a ゝゝL〃 signal (YOv) is applied to the control signal input terminal 马1. When XXH// is applied between the control signal input terminals, the internal switch (11) turns on and at the same time the resistor (72B
) because the transistor (72A) is turned on through
The input terminal (2) of the analog multiplexer (1) is clamped to the ON voltage (2□v) of the transistor (72A). On the other hand, the open side 1 signal input terminal (st L /
7, the internal switch (121) is turned OFF and the transistor (71A) is also turned OFF'.
The distance between the control signal input terminals is ゝゝL〃, the control signal input terminal□□
□(If SS H// is, switch (11) is OFF, contrary to the above), transistor (7+A) is ON, internal switch (Mausoleum is ON, transistor (72A) is OFF)
It becomes F.

すなわち、入力端子にどのような電圧が印加されても内
部スイッチがOFFとなっているアナログスイッチの入
力電圧は常にトランジスタのON電圧にクランプされる
。これによpOFF時の入出力間リーク′岨流は非常に
小さくなシ、かつオフセット電圧も入力電圧に影響され
ないことになる。
That is, no matter what voltage is applied to the input terminal, the input voltage of the analog switch whose internal switch is OFF is always clamped to the ON voltage of the transistor. As a result, the leakage current between the input and output at the time of pOFF is extremely small, and the offset voltage is not affected by the input voltage.

従って、信号選択回路のオフセット補正を無くすことが
できる。又、入力信号自身のオフセット、ボルテージフ
ォロア回路(5)のオフセット及びA/D変換器(6)
のオフセット等を含めてオフセット補正が必要な場合で
も、一定量の補正を行なえば良いことにな9補正回路が
簡単になる。
Therefore, offset correction of the signal selection circuit can be eliminated. Also, the offset of the input signal itself, the offset of the voltage follower circuit (5), and the A/D converter (6)
Even if offset correction is required, including the offset of

以上の説明ではアナログ信号として2人力の場合につい
て説明したが、n入力の場合でも同様な効果が得られる
のは言うまでもない0尚、この実施例ではアナログ入力
電圧として正電圧が印加されるものとする。
In the above explanation, we have explained the case in which two people input the analog signal, but it goes without saying that the same effect can be obtained even in the case of n inputs.In addition, in this embodiment, it is assumed that a positive voltage is applied as the analog input voltage. do.

次に第2図によシ他の実施例について説明すると、(8
)はアナログスイッチを利用した入力信号クランプ回路
である。アナログスイッチ(8)の制御化゛号入力端子
C3,C4及び出力端子0.及び04はアナログ典→÷
φマルチプレクサ(1)の制御信号入力端子02.Oよ
及び入力端チェ□、■2にそれぞれ接続され、アナログ
スイッチ(8)の入力端チェ、及び工 はそれぞれ接地
側へ接地されている。すなわち、制御信号入力端子間が
XVHI/になるとアナ 9 − ログ+マルチプレクサ(1)の内部スイッチ(111が
ONになると同時にアナログスイッチ(8)の内部スイ
ッチ(8)がONと、なシアナログQマルチ1プレクサ
(1)の入力端チェ、の電圧を抵抗器(’s4とスイッ
チ((至)のON抵抗値で定まる電圧にクランプされる
。一方、制御信号入力端子鴎1がSS H//になった
ときはアナログ主中≠ナマルチプレクサ(1)の内部ス
イッチ(121がONになると同時にアナログスイッチ
(明のON抵抗値で定まる電圧にクランプされ、第1図
に示した実施例と同じ効果が得られる。尚、この実施例
によればアナログ入力として正負の電圧を印加すること
が出来る。
Next, referring to FIG. 2, another embodiment will be explained. (8
) is an input signal clamp circuit that uses an analog switch. Control signal input terminals C3, C4 and output terminals 0. of the analog switch (8). and 04 are analog codes → ÷
Control signal input terminal 02 of φ multiplexer (1). The analog switch (8) input terminal channels □ and 2 are connected to the input terminal channels □ and 2, respectively, and the input terminal channels of the analog switch (8) are grounded to the ground side. In other words, when the control signal input terminal becomes XVHI/, the internal switch (111) of the analog 9-log+multiplexer (1) turns on, and at the same time the internal switch (8) of the analog switch (8) turns on. The voltage at the input terminal CH of the multi-1 plexer (1) is clamped to the voltage determined by the ON resistance value of the resistor ('s4) and the switch ((to).On the other hand, the control signal input terminal KATO1 is connected to the SS H// When the internal switch (121) of the multiplexer (1) turns on, it is clamped to the voltage determined by the ON resistance value of the analog switch (light), and the same effect as in the embodiment shown in Fig. 1 is obtained. According to this embodiment, positive and negative voltages can be applied as analog inputs.

上記各実施例によれば選択さ1.たアナログスイッチ以
外のアナログスイッチの入力をほぼOvにクランプする
ことにより、アナログスイッチのOFF時のリーク電流
によるオフセット電圧を非常に小さくかつ、入力電圧の
変化によるオフセット電圧の変動を無くすことができる
0これによシー 10− 量の変動が小でくなるためオフセット補正回路が簡単に
なる等の効果を有する。東に図示されない選択信号発生
回路の故障あるいは誤動作により、複数の信号が選択さ
れた場合には全入力がクランプ電圧になるため故障発見
が容易となる効果もあるO 〔発明の効果〕 以上説明した通り、アナログマルチプレクサを有したア
ナログ信号選択側Mにおいて、アナログ信号選択特に、
他の非選択アナログ信号を接地側へ導出させる導出手段
を設けたことにより、アナログスイッチのOFF時のリ
ーク電流による影響を除去して選択されたアナログ信号
を正確に伝達できる。また、図示されない選択信号発生
回路の故障あるいは誤動作により、複数の信号が選択さ
れた場合には全入力が接地側へ導出されるため故障発見
が容易となる効果が得られる。
According to each of the above embodiments, 1. By clamping the inputs of analog switches other than the analog switches set to approximately Ov, it is possible to make the offset voltage due to leakage current when the analog switch is OFF extremely small, and to eliminate fluctuations in the offset voltage due to changes in input voltage. This has the effect of simplifying the offset correction circuit because the fluctuation in the amount of sheath is reduced. If multiple signals are selected due to a failure or malfunction of the selection signal generation circuit (not shown), all inputs become clamp voltages, which has the effect of making failure detection easier. [Effects of the Invention] As explained above. In particular, on the analog signal selection side M with an analog multiplexer, the analog signal selection is
By providing a deriving means for deriving other non-selected analog signals to the ground side, the influence of leakage current when the analog switch is OFF can be removed, and the selected analog signal can be accurately transmitted. In addition, if a plurality of signals are selected due to a failure or malfunction of a selection signal generation circuit (not shown), all inputs are led to the ground side, which facilitates failure detection.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は不兜明によるアナログ選択回路の一実施例を示
す回路図、第2図はこの発明の他の実施例を示す回路図
、第6図は従来のアナログ信号選択(ロ)路を示す回路
図である。 (1)・・アナログマルチプレクサ (71A)、 (72A)・・トランジスタ(8)・・
アナログスイッチ なお、図中、同一部分は同一符号で示す。 代理人大岩増雄 第3図 手続補正書(自発) 2、発明の名称 アナログ信号選択回路 3、補正をする者 事件との関係 特許出願人 住 所 東京都千代田区丸の内二丁目2番3号名 称 
(601)三菱電機株式会社 代表者片山仁八部 4、代理人 住 所 東京都千代田区丸の内二丁目2番3号三菱電機
株式会社内 明細書の発明の詳細な説明の欄、および図面。 6、補正の内容 (1)明細書第3頁第7行の「しかして、」という記載
を「そしてJと補正する。 (2)明細書第3頁第13行の「電流制限抵抗器」とい
う記載を「アナログ信号源の出力インピーダンスを模擬
した抵抗器」と補正する。 (3)明細書第3頁第20行の「内部スイッチ(12)
J という記載を「内部スイッチ(11)Jと補正する
。 (4)明細書第4頁第2行の「出方端子02」という記
載を「出力端子oIJと補正する。 (5)図面中第1図、第2図及び第3図を別紙の通り補
正する。 7、添付書類の目録 図面 1 通 以 上
Fig. 1 is a circuit diagram showing one embodiment of the analog selection circuit by Akira Fuko, Fig. 2 is a circuit diagram showing another embodiment of the present invention, and Fig. 6 is a circuit diagram showing a conventional analog signal selection (b) circuit. FIG. (1)...Analog multiplexer (71A), (72A)...Transistor (8)...
Analog Switch Note that in the figures, the same parts are indicated by the same symbols. Agent Masuo Oiwa Figure 3 procedural amendment (voluntary) 2. Name of the invention Analog signal selection circuit 3. Person making the amendment Relationship to the case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name Name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. Detailed description of the invention in the specification and drawings. 6. Contents of the amendment (1) The statement "However," on page 3, line 7 of the specification is amended to "and J." (2) "Current limiting resistor" on page 3, line 13 of the specification. The description "A resistor that simulates the output impedance of an analog signal source" is corrected. (3) “Internal switch (12)” on page 3, line 20 of the specification
The description J is corrected to ``internal switch (11) J.'' (4) The description ``output terminal 02'' on the second line of page 4 of the specification is corrected to ``output terminal oIJ.'' (5) The description ``output terminal oIJ'' is corrected to ``output terminal oIJ.'' Figure 1, Figure 2, and Figure 3 are corrected as shown in the attached sheet. 7. Attached document catalog drawings 1 copy or more

Claims (1)

【特許請求の範囲】 (1)複数のアナログ信号より一つの信号を選択信号に
基づいて選択するアナログマルチプレクサを備えたアナ
ログ信号選択回路において、アナログ信号選択時に他の
非選択アナログ信号を接地側へ導出させる導出手段を備
えたことを特徴とするアナログ信号選択回路。 (2)上記導出手段は、コレクタがアナログマルチプレ
クサの入力端子に直結されると共にエミッタが接地側に
接地され、かつベースにて他のアナログ信号選択用信号
を受けて導通するトランジスタを備えたクランプ回路か
ら成り、アナログマルチプレクサの各入力側へそれぞれ
設置され他のアナログ信号選択用の信号を受けた時、上
記トランジスタが導通することにより、該トランジスタ
のコレクタにかかつている非選択アナログ信号を接地側
へ導出させる構成であることを特徴とする特許請求の範
囲第1項記載のアナログ信号選択回路。 (8)上記導出手段は、一端がアナログマルチプレクサ
の入力端子に直結されると共に他端が接地側へ接地され
、かつ制御信号入力端子にて他のアナログ信号選択用信
号を受けるアナログスイッチから151+、アナログマ
ルチプレクサの各入力側へそれぞれ設置され、他のアナ
ログ信号選択用信号を受けた時、該信号を受けたアナロ
グスイッチのみが閉成することにより該アナログスイッ
チの一端にかかつている非選択アナログ信号を接地側へ
導出させる構成であることを特徴とする特許請求の範囲
第1項記載のアナログ信号選択回路。
[Claims] (1) In an analog signal selection circuit equipped with an analog multiplexer that selects one signal from a plurality of analog signals based on a selection signal, when an analog signal is selected, other unselected analog signals are routed to the ground side. An analog signal selection circuit comprising derivation means for deriving the signal. (2) The above derivation means is a clamp circuit including a transistor whose collector is directly connected to the input terminal of the analog multiplexer, whose emitter is grounded to the ground side, and whose base becomes conductive upon receiving another analog signal selection signal. are installed on each input side of the analog multiplexer, and when receiving a signal for selecting another analog signal, the above-mentioned transistor becomes conductive, thereby sending the non-selected analog signal applied to the collector of the transistor to the ground side. 2. The analog signal selection circuit according to claim 1, wherein the analog signal selection circuit is configured to derive the signal. (8) The deriving means is connected to an analog switch 151+, which has one end directly connected to the input terminal of the analog multiplexer, and the other end is grounded to the ground side, and receives another analog signal selection signal at the control signal input terminal; When the analog switch is installed at each input side of the analog multiplexer and receives another analog signal selection signal, only the analog switch that receives the signal closes, thereby eliminating the unselected analog signal applied to one end of the analog switch. 2. The analog signal selection circuit according to claim 1, wherein the analog signal selection circuit is configured to lead out the signal to the ground side.
JP7130384A 1984-04-10 1984-04-10 Analog signal selecting circuit Pending JPS60214629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7130384A JPS60214629A (en) 1984-04-10 1984-04-10 Analog signal selecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7130384A JPS60214629A (en) 1984-04-10 1984-04-10 Analog signal selecting circuit

Publications (1)

Publication Number Publication Date
JPS60214629A true JPS60214629A (en) 1985-10-26

Family

ID=13456738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7130384A Pending JPS60214629A (en) 1984-04-10 1984-04-10 Analog signal selecting circuit

Country Status (1)

Country Link
JP (1) JPS60214629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10151416C1 (en) * 2001-10-18 2003-04-10 Siemens Ag Multiplexer circuit for monitoring several switch elements has integrated sampling circuit for interrogating switch conditions
JP2020061788A (en) * 2014-10-10 2020-04-16 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10151416C1 (en) * 2001-10-18 2003-04-10 Siemens Ag Multiplexer circuit for monitoring several switch elements has integrated sampling circuit for interrogating switch conditions
US6714064B2 (en) 2001-10-18 2004-03-30 Siemens Aktiengesellschaft Multiplexer circuit and method for detection of the switching state of switching elements
JP2020061788A (en) * 2014-10-10 2020-04-16 株式会社半導体エネルギー研究所 Semiconductor device
US11374023B2 (en) 2014-10-10 2022-06-28 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, processing unit, electronic component, and electronic device

Similar Documents

Publication Publication Date Title
JP2951217B2 (en) Telephone subscriber circuit
KR910019414A (en) Solid state imaging device
JPS60214629A (en) Analog signal selecting circuit
KR920009186A (en) Sample hold circuit for CCD image sensor signal
KR910019319A (en) Supply current compensation circuit device
JPS5831781B2 (en) Receive/bypass circuit for subsystems in polling systems
SU1371514A3 (en) Transformeless differential system
KR900001117A (en) Automatic gain control circuit
NO153590B (en) CONNECT LINE INTERFACE FOR CONNECTING A TWO-LINE CONNECTION LINE WITH A PHONE CENTER.
US4298953A (en) Programmable zero-bias floating gate tapping method and apparatus
KR910019422A (en) Signal clamp device for dual function input terminals
KR0155616B1 (en) Video signal clamp circuit
KR840008231A (en) Electrical signal processing equipment
JPS6083408A (en) Current converting circuit
JPS602809B2 (en) multiplexer circuit
KR840008728A (en) Emitter Follower SEPP Circuit
SU1310997A1 (en) Voltage-to-current converter
JP3048377B2 (en) Grain moisture meter
SU1142882A1 (en) Charge amplifier
KR950035047A (en) Bias current generator
SU463931A1 (en) Resistive sensor resistance meter
KR100189774B1 (en) Pulse conversion circuit independent to variation of power voltage
JP3461258B2 (en) Apparatus for measuring conductivity or pH
JP3261590B2 (en) Analog signal input device
JP2685765B2 (en) Dial pulse stable transmission circuit