DE10119051B4 - Circuit arrangement for enabling a clock signal in response to an enable signal - Google Patents

Abstract

Circuit arrangement for enabling a clock signal (CLK) in dependence on an enable signal (EN), comprising:
A first input terminal (10) for the clock signal (CLK),
A second input terminal (11) for the enable signal (EN),
A first signal path which contains a delay element (15) and which is connected on the input side to the first input connection (10),
A second signal path (163, 161, 164, 162) which is connected on the input side on the one hand to the first input terminal (10) and an input of the delay element (15) and on the other side to the second input terminal (11),
A first logic operation element (12), which is connected on the input side to the first and second signal paths (15; 163, 161, 164, 162) and is coupled on the output side to a connection (14) for tapping a released clock signal (OUT),
- wherein the delay element (15) of the first signal path has an even number of series-connected inverters (151, 152),
- wherein the second signal path comprises: ...

Description

The The invention relates to a circuit arrangement for enabling a clock signal in dependence of a release signal having a first input terminal for the clock signal and a second input terminal for the enable signal.

circuitry of the type mentioned are in digital circuit technology in many ways Jobs needed. For example, in integrated semiconductor memories, the isochronous operated, so-called SDRAMs (Synchronous Dynamic Random Access Memories), it is necessary that in response to a release signal a clock signal is passed or blocked. The to be released Clock signal is, for example, in a delay locked loop, so-called DLL (Delay Locked Loop), fed. The DLL circuit can because of their special internal operation when feeding clock signals, the not a predetermined minimum length have undefined operating states. So may the DLL circuit in particular not with respect to normal operation about only half as long or even shorter Pulses are controlled. In this special environment as well as in Therefore, there is a need that an existing Clock signal in dependence is forwarded by a release signal, with only complete, d. H. the half clock pulses having a clock period, generated on the output side become. At the same time, however, it is desirable that the first complete Clock pulse as possible early is provided after an edge of the enable signal.

In the US Pat. No. 6,204,695 B1 a clock enable circuit is shown in which a clock input signal is fed via two different paths to inputs of a NAND gate. One of the signal paths directly couples to one input of the NAND gate, the other of the signal paths is enabled by an enable signal containing a memory element and coupled to another input of the NAND gate. Runtime considerations play a minor role. The interdependent edges in the illustrated signal diagrams each switch simultaneously to one another.

The The object of the invention is to be seen in a circuit arrangement for releasing a clock signal in response to a release signal to indicate at incomplete Pulses are avoided.

According to the invention This object is achieved by a circuit arrangement for enabling a clock signal dependent on solved by a release signal, comprising: a first input terminal for the clock signal, a second input terminal Input terminal for the enable signal, a first signal path containing a delay element and the Input side is connected to the first input terminal, a second Signal path, the input side on the one hand to the first input terminal and a Input of the delay element and on the other hand connected to the second input terminal, a first logical linking element that Input side connected to the first and second signal paths is and output side with a connection to tap a shared Clock signal is coupled, wherein the delay element of the first signal path has an even number of series-connected inverters, wherein the second signal path comprises: a memory element having a Set input and a reset input, wherein the set and reset inputs of each a second logical link element can be controlled, on the input side, on the one hand in each case via a same Number of at least one inverter connected to the first input terminal are, and on the other hand over a different number of at least one inverter with the connected to the second input terminal are, wherein the circuit arrangement is dimensioned so that the first and second signal paths from the first input terminal and the second input terminal to the input terminals of first logical link element each having substantially equal signal propagation times.

The Circuit arrangement according to the invention makes sure that only generated at a low level of the clock signal on the output side, a pulse of full length becomes. At a high level of the clock signal becomes a pulse generation output suppressed. Only with the next Low level of the clock signal is the then already switched enable signal for the output-side generation of the first pulse of the released Clock signal used. The circuit arrangement according to the invention has about it addition, the advantage that the first pulse of the output-side clock signal relatively early is produced.

The circuit arrangement according to the invention can be used particularly advantageously in synchronous DRAMs (SDRAMs) in order to drive a delay locked loop (DLL). The delay locked loop generates the clock signal with which the data is provided intermittently on the output side. In order to respond as quickly as possible to a read command directed to the semiconductor memory and thereby to allow a short response time, it is necessary that the clock signal provided by the circuit arrangement as early as possible is generated as a complete pulse after a switch-on edge of the enable signal. The switchover from power-saving operation to normal operation of the DRAM, where the DLL must be ready for operation, is thereby accelerated.

The first logical linking element is expediently a NAND gate, which is followed by an inverter. At the exit of the inverter, the released clock signal is tapped.

the Another input of the second logic element is a so-called RS flip-flop upstream, so a memory element that with a pulse a first input and with a pulse at a second input Input reset can be. The entrances of the RS flip-flops are preceded by NAND gates, on the one hand inverted from the input side clock signal can be controlled and on the other hand complementary each other from the enable signal can be controlled. For this is the respectively an input of these NAND gates over an inverter connected to the first input terminal for the clock signal. The other input of the NAND gates is via an inverter with the second input terminal for the enable signal connected or over two inverters in series with this second input terminal.

The RS flip-flop is formed of NAND gates whose outputs each fed back to an input of the other NAND gate crosswise are. The RS flip-flop is triggered by negative pulses to each of the inputs the NAND gate is set or reset.

The Signal transit times of all Signal paths, so on the one hand from the first input terminal to the first logical linking element as well as from the first input connection via the two inputs of the RS flip-flops to the other input of the first logic element and on the other hand from the second input terminal via the two signal paths of the RS flip-flop to the first logic element are each the same size, so that a rising or falling Edge of the respective input signal up to the first logic operation element in about the same delay time experiences. By appropriate dimensioning of the transistors used NAND gate or the inverter can such delay times be set in a known manner. This is the Stromtreiberfähigkeit the transistors by adjusting their length / width ratio (W / L) of their To be sized accordingly.

following the invention will be explained in more detail in connection with the drawings. Show it:

1 a circuit diagram of the circuit arrangement according to the invention,

2 the timing of in the circuit of 1 occurring signals and

3 a circuit arrangement according to the prior art.

Conventionally, a clock signal CLK having periodically consecutive clock pulses is applied to an input terminal 31 provided. A release signal EN, which has a low level in the inactive state and indicates by a rising edge that the clock signal CLK is to be released, becomes at a second input terminal 32 provided. Both signals CLK, EN are in a NAND gate 33 logically linked together. An output of the NAND gate 33 downstream inverter 34 generated at the exit 35 the released clock signal OUT. A NAND gate performs a logical no-AND of its input signals.

A problem with the known circuit arrangement is when a rising edge for enabling the clock signal CLK or a falling edge for blocking the clock signal CLK is applied during a high-level phase of the clock signal CLK. The output signal OUT then has shortened pulses 36 . 37 on. When the output terminal 35 a delay locked loop, for example an SDRAM, is supplied, then the delay locked loop can assume unwanted operating conditions. Reading data from the SDRAM could then violate standardized specifications.

In the 1 The circuit shown also has an input shot 10 for the clock signal CLK and an input terminal 11 for the enable signal EN on. The enabled output signal OUT is at an output terminal 14 tapped. A first signal path 15 connects the input terminal 10 via a delay element 15 with an input of the NAND gate 12 , The delay element 15 comprises an even number of inverters, for example two inverters in series 151 . 152 , At the output of the delay element 15 is the clock signal CLK2 delayed from the input side clock signal CLK.

A second signal path 16 linked on the input side the input terminal 10 and the input terminal 11 and generates a modified enable signal EN2, which is the other input of the NAND gate 12 is supplied. The output signal OUT is from the output of the NAND gate 12 by inverting via the downstream inverter 13 generated. The output terminal 14 is directly to the output of the inverter 13 connected.

The second signal path 16 has an RS flip-flop with two NAND gates 161 . 162 , The output of the NAND gate 161 is on an input of the NAND gate 162 fed back, the output of the NAND gate 162 is on an input of the NAND gate 161 fed back. The other inputs 165 . 166 the NAND gate 161 respectively. 162 form the inputs of the RS flip-flop. A negative pulse / R resets the RS flip-flop, ie the output signal EN2 assumes a low level. By a negative pulse / S at the connection 166 the RS flip-flop is set, ie the signal EN2 assumes a high level. The inputs 165 . 166 are to the output terminals of each NAND gate 163 . 164 connected. The input connection 10 for the clock signal CLK is via an inverter 101 with the one input of NAND gates 163 . 164 connected. The input connection 11 for the enable signal EN is via an inverter 111 with the other input of the NAND gate 163 connected. The other entrance of the NAND gate 164 is via an inverter 112 that with the inverter 111 is connected in series with the input terminal 11 connected.

The signal diagram in 2 shows that the clock signal CLK2 from the clock signal CLK by the delay time, which from the delay element 15 is effected, is shifted. If the input signal EN is a rising edge 21 that still exists during the low phase 22 of the clock signal CLK, then, after the delay time, which is along the path 11 . 111 . 112 . 164 . 166 . 162 acts, with the modified enable signal EN2 a rising edge 23 generated. At the exit 14 is then delayed by the signal delay along the NAND gate 12 and the inverter 13 a first shared pulse 24 for the output side clock signal OUT. A falling edge 25 during a low phase 26 of the clock signal CLK causes a falling edge 27 after a delay along the path 11 . 111 . 163 . 165 . 161 , The output clock signal OUT is again blocked and remains at a low level.

It is essential that all delay times of a level at the input terminal 10 or at the input terminal 11 to the entrances of the NAND gate 12 are about the same length. So the delay times along the path 10 . 15 and along the path 10 . 101 . 163 . 165 . 161 and along the path 10 . 101 . 164 . 166 . 162 as well as along the path 11 . 111 . 163 . 165 . 161 and along the path 11 . 111 . 112 . 164 . 166 . 162 are each about the same length. This causes the signals CLK2 and EN2, which are at the inputs of the NAND gate 12 abut each other, have a phase shift of almost zero. The high phase of the signal CLK2, that at the output terminal 14 for the output signal OUT, therefore, in all cases is approximately equal to a high phase of the clock signal CLK at the input terminal 10 , The setup time of the enable signal EN, which must be adhered to before an edge of the clock signal CLK, is minimized. The setup time is the time that must hold an edge of the enable signal EN before a rising edge of the clock signal CLK to be processed during the subsequent high phase of the clock signal CLK can. Only if the enable signal EN has a lower setup time, the output signal OUT is generated only with the next but one high phase of the clock signal CLK.

The latter case is in the lower signal diagram of 2 shown. A flank 42 the enable signal EN violates the setup time with respect to the edge 40 of the clock signal CLK. The flank 42 lies behind the flank 40 , The modified enable signal EN2 has an edge 44 on that in response to the falling edge 43 of the clock signal CLK along the signal path 101 . 163 . 165 . 161 is delayed. The first impulse 45 of the output signal OUT eventually becomes the rising edge 41 of the clock signal CLK and the rising edge 46 of the delayed clock signal CLK2. A falling edge 47 the enable signal EN, which in turn the setup time with respect to the rising edge 48 of the clock signal CLK generates a falling edge of the modified enable signal EN2 in response to the falling edge 49 of the clock signal CLK, which along the signal path 101 . 164 . 166 . 162 is delayed. Finally, there will be the impulse 50 the output signal OUT terminated.

In the 1 shown circuit arrangement causes an edge, both rising and falling, of the enable signal EN only immediately causes a change of the output signal OUT when the clock signal CLK has a low level. When the clock signal CLK has a high level, the output signal OUT is not switched. This case leads to the in 1 The circuit shown in the prior art to shortened pulses 36 . 37 which would lead to specification violations when fed into a DLL in an SDRAM.

Claims (4)

Circuit arrangement for enabling a clock signal (CLK) in response to an enable signal (EN), comprising: - a first input terminal (CLK) 10 ) for the clock signal (CLK), A second input terminal ( 11 ) for the enable signal (EN), - a first signal path, a delay element ( 15 ) and the input side with the first input terminal ( 10 ), - a second signal path ( 163 . 161 . 164 . 162 ), the input side on the one hand with the first input terminal ( 10 ) and an input of the delay element ( 15 ) and on the other hand with the second input terminal ( 11 ), - a first logic element ( 12 ), the input side with the first and second signal paths ( 15 ; 163 . 161 . 164 . 162 ) and the output side with a connection ( 14 ) is coupled to the tap of a released clock signal (OUT), - wherein the delay element ( 15 ) of the first signal path an even number of series-connected inverters ( 151 . 152 ), wherein the second signal path comprises: a memory element ( 161 . 162 ) with a set input ( 166 ) and a reset input ( 165 ), - where the set and reset inputs ( 166 . 165 ) of a second logic element ( 164 . 163 ) are controllable, - the input side on the one hand in each case via an equal number of at least one inverter ( 101 ) with the first input terminal ( 10 ), and - on the other hand, via a different number of at least one inverter ( 111 . 112 ) with the second input terminal ( 11 ), wherein the circuit arrangement is dimensioned such that the first and second signal paths ( 15 ; 163 . 161 . 164 . 162 ) from the first input terminal ( 10 ) and from the second input terminal ( 11 ) to the input terminals of the first logic element ( 12 ) each have substantially equal signal propagation times. Circuit arrangement according to Claim 1, characterized in that the first logic operation element ( 12 ) is a NAND gate to which an inverter ( 13 ) and that the terminal for tapping the enabled clock signal (OUT) to the output of the downstream inverter ( 13 ) connected. Circuit arrangement according to Claim 1 or 2, characterized in that the respective second logic elements ( 164 . 163 ) NAND gates are, on the one hand, via an inverter ( 101 ) with the first input terminal ( 10 ) and, on the other hand, that one of the second logic elements ( 163 ) via an inverter ( 111 ) with the second input terminal ( 11 ) and that the other of the second logic elements ( 164 ) via two inverters connected in series ( 111 . 112 ) with the second input terminal ( 11 ) connected is. Circuit arrangement according to one of Claims 1 to 3, characterized in that the memory element has two NAND gates ( 161 . 162 ), one output of which is in each case fed back to one of the inputs of the other NAND gate.