TWI753735B - Display device - Google Patents

Abstract

Provided is a display device including a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on the first substrate of the display panel and extended to be exposed at the side. A patterned electrode layer is on the second substrate of the display panel and partially exposed at the side. A sealant is between the first and second substrates. A spacer layer is on the first substrate and covers the first and second leads. The thickness of the spacer layer on the first lead is smaller than the thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first lead.

Description

display device

The present invention relates to a display device, and more particularly, to a display device having an external circuit board with side bonding.

In the current display device technology, it has been in the direction of narrow bezel panels. For example, a side-bonding process can be used for display devices to achieve narrow bezels. In the side bonding process of the display device, conductive pads are formed at the sides of the display panel, and conductive glue is used to connect the external circuit board to the conductive pads, so that the external circuit board and the display panel are electrically connected by the conductive glue. sexual connection. Therefore, in the side bonding process, good electrical connection is often a subject of concern in the art.

The present invention provides a display device, wherein a part of the plurality of conductive pads extends to a space between two substrates, and a space for accommodating the conductive pads is defined by a spacer layer disposed between the two substrates.

The display device of the present invention includes a display panel with a central area and an edge area, a plurality of first conductive pads, a plurality of second conductive pads, a conductive adhesive layer and an external circuit board. The display panel includes a first substrate and a second substrate, a sealant and a spacer layer, which are arranged oppositely. A plurality of first pins and a plurality of second pins are disposed on the first substrate, extend into the edge region, and are exposed at the sides of the first substrate. The patterned electrode layer is disposed on the second substrate and partially exposed at the side of the second substrate. The sealant is disposed between the first substrate and the second substrate. The spacer layer is disposed on the first substrate and located in the edge region, and covers the first lead and the second lead, wherein the spacer layer on the first lead is less than the thickness of the rest of the spacer layer. The first conductive pads are arranged at the side of the display panel and connect the patterned electrode layer, the first pins and the spacer layer on the first pins, wherein the The first conductive pad extends between the patterned electrode layer and the spacer layer on the first lead. The second conductive pads are disposed at the side of the display panel and connect the second pins and the spacer layer on the second pins. The conductive adhesive layer is disposed on the side of the display panel and covers the first conductive pad and the second conductive pad. The external circuit board is disposed on the conductive adhesive layer.

Based on the above, in the display device of the present invention, a part of the plurality of conductive pads extends to the space between the two substrates, and the space for accommodating the conductive pads is defined by the spacer layer disposed between the two substrates. gap. In this way, the contact area between the conductive pad and the patterned electrode layer can be increased to ensure electrical connection between the first lead and the patterned electrode layer.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The following examples will be described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in full scale. In order to facilitate understanding, the same elements will be described with the same symbols in the following description.

The terms "including", "including", "having", etc. mentioned in the text are all open-ended terms, that is, "including but not limited to".

In addition, the directional terms such as "up", "down", "left" and "right" mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention.

When describing elements in terms of "first", "second", etc., they are only used to distinguish these elements from each other and do not limit the order or importance of the elements. Therefore, in some cases, the first element may also be referred to as the second element, and the second element may also be referred to as the first element, without departing from the scope of the patent application.

The display device of the present invention includes a display panel, conductive pads (as side electrodes) disposed on the side of the display panel, an external circuit board disposed on the side of the display panel, and the external circuit board and the conductive pads conductive adhesive layer between. These components will be described in detail below.

FIG. 1 is a schematic side view of a display panel according to an embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line A-A in FIG. 1 . FIG. 2B is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line B-B in FIG. 1 . FIG. 2C is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line C-C in FIG. 1 . In the present invention, the type of the display panel will not be limited. For example, in this embodiment, the display panel includes two substrates disposed opposite to each other, but the present invention is not limited thereto. In other embodiments, the display panel may also include only one substrate. In addition, in order to facilitate the description of the present invention, only the thin film transistor substrate constituting the display panel, the pins disposed on the thin film transistor substrate, and the color filter are simply drawn in FIG. 1 , FIG. 2A , FIG. 2B and FIG. 2C . The substrate, the patterned electrode disposed on the color filter substrate, and the sealant for bonding the thin film transistor substrate and the color filter substrate, but the present invention is not limited thereto, and these components are well known to those skilled in the art, It will not be described in detail here. Depending on actual needs, those skilled in the art can make appropriate changes to the structure of the display panel in this embodiment. In addition, FIG. 1 shows the case where the external circuit board COF is connected to the display panel, while the external circuit board COF is omitted in FIGS. 2A , 2B and 2C.

Please refer to FIGS. 1 , 2A, 2B and 2C at the same time. In this embodiment, the display panel 10 includes a first substrate 102 and a second substrate 104 disposed opposite to each other for bonding the first substrate 102 and the second substrate 104 The sealant 106 and the spacer layer 108 disposed on the first substrate 102 . The display panel 10 has a central area 10a, an edge area 10b and a bonding area 10c, wherein the edge area 10b is an area adjacent to a side of the display panel 10, the central area 10a is an area surrounded by the edge area 10b, and the bonding area 10c is used for The area where the sealant 106 is disposed is located between the central area 10a and the edge area 10b. The space S is defined by the first substrate 102 , the second substrate 104 and the sealant 106 . The space S is used to accommodate the liquid crystal LC.

The first substrate 102 is, for example, a thin film transistor substrate, and may have components such as active elements, circuit patterns, pins, etc., wherein the pins extend from the inside of the first substrate 102 to the sides and are exposed at the sides to communicate with the outside. Component connection. In FIG. 1 , FIG. 2A , FIG. 2B and FIG. 2C , for the convenience of description, only pins are shown, and the other components are well known to those skilled in the art, and will not be further described herein. In this embodiment, the first pins 102a and the second pins 102b are disposed on the first substrate 102 and extend into the edge region 10b, and the present invention does not vary the respective numbers of the first pins 102a and the second pins 102b and location restrictions.

The second substrate 104 is, for example, a color filter substrate, and may have components such as color filters, black matrix (BM) patterns, patterned electrodes, etc., wherein the patterned electrodes are disposed on the second substrate 104 and partially The ground is exposed at the side of the second substrate 104 for connection with external components. In FIG. 1 , FIG. 2A , FIG. 2B and FIG. 2C , for the convenience of description, only the patterned electrodes are shown, and the other components are well known to those skilled in the art, and will not be further described herein. In this embodiment, the patterned electrodes 104 a are disposed on the second substrate 104 and partially exposed at the sides of the second substrate 104 . In detail, in this embodiment, the first pin 102a needs to be electrically connected to the patterned electrode 104a, and the second pin 102b does not need to be electrically connected to the patterned electrode 104a, so only the patterned electrode 104a is located in the patterned electrode 104a. The portion above the first lead 102a needs to extend to the side of the second substrate 104 and be exposed at the side, while the remaining portion of the patterned electrode 104a does not need to extend to the side of the second substrate 104 and be exposed to the side place.

As shown in FIG. 2A , since the first lead 102a needs to be electrically connected to the patterned electrode 104a, the portion of the patterned electrode 104a located above the first lead 102a extends to the side of the second substrate 104 and is exposed to the side edge. As shown in FIG. 2B , since the second lead 102b does not need to be electrically connected to the patterned electrode 104a, the portion of the patterned electrode 104a located above the second lead 102b does not extend to the side of the second substrate 104 and is exposed on the side. As shown in FIG. 2C, in the area between two adjacent pins (for example, the area between two adjacent first pins 102a, the area between two adjacent second pins 102b, In the area between the adjacent first leads 102a and the second leads 102b), the patterned electrodes 104a also do not extend to the sides of the second substrate 104 and are exposed at the sides.

The spacer layer 108 is disposed on the first substrate 102 in the edge region 10b. In addition, the spacer layer 108 covers the first lead 102a, the second lead 102b, and the first substrate 102 between two adjacent leads. The spacer layer 108 disposed on the first lead 102 a and the second lead 102 b can ensure that the first lead 102 a and the second lead 102 b are securely disposed on the first substrate 102 . In this embodiment, the edge of the spacer layer 108 is aligned with the edge of the first substrate 102, but the present invention is not limited thereto. In other embodiments, the edge of the spacer layer 108 may not be aligned with the edge of the first substrate 102 , that is, the edge of the spacer layer 108 may be retracted from the edge of the first substrate 102 toward the central region 10a. The spacer layer 108 is preferably an insulating layer, such as a polystyrene (PS) layer or a color photoresist layer, but the invention is not limited thereto.

In this embodiment, the spacer layer 108 has different thicknesses in different regions. In detail, the thickness of the spacer layer 108 on the first lead 102a is smaller than the thickness of the rest of the spacer layer 108 . As shown in FIG. 2A , FIG. 2B and FIG. 2C , the thickness of the spacer layer 108 located on the first lead 102 a is smaller than the thickness of the spacer layer 108 located on the second lead 102 b , and is smaller than the thickness of the two adjacent leads The thickness of the spacer layer 108 on the first substrate 102 in between. In addition, in this embodiment, the thickness of the spacer layer 108 located on the second pin 102b is less than or equal to the thickness of the spacer layer 108 located on the first substrate 102 between two adjacent pins.

In the edge region 10 b, an air gap AG exists between the first substrate 102 and the second substrate 104 . In detail, in this embodiment, depending on the thickness of the spacer layer 108 in different regions, the air gap AG on the spacer layer 108 on the first pin 102a is defined by the spacer layer 108 and the patterned electrode layer 104a and With a first distance D1, the air gap AG on the spacer layer 108 on the second lead 102b is defined by the spacer layer 108 and the patterned electrode layer 104a and has a second distance D2, and is located between the first lead 102a and the second The air gap AG on the spacer layer 108 on the first substrate 102 between the pins 102b is defined by the spacer layer 108 and the patterned electrode layer 104a and has a third distance D3. In addition, in the central region 10a, there is a fourth distance D4 between the first lead 102a and the second lead 102b and the patterned electrode layer 104a. In this embodiment, the fourth distance D4 is the height of the space S, which may also be called a liquid crystal gap.

In this embodiment, the first distance D1 is 6% to 60% of the fourth distance D4, the second distance D2 is less than 6% of the fourth distance D4, and the third distance D3 is less than 6% of the fourth distance D4. In this embodiment, since the thickness of the spacer layer 108 on the first lead 102a is smaller than that of the rest of the spacer layer 108, the first distance D1 is greater than the second distance D2 and the third distance D3. In addition, as previously mentioned, the third distance D3 may be less than or equal to the second distance D3 depending on the thickness of the spacer layer 108 located between two adjacent pins and the thickness of the spacer layer 108 located on the second pin 102b Distance D2.

In addition, in other embodiments, as shown in FIGS. 5A , 5B and 5C , the display panel 10 may further include a first alignment layer 500 and a second alignment layer 502 . The first alignment layer 500 covers the first substrate 102 , the first lead 102 a , the second lead 102 b and the spacer layer 108 . The second alignment layer 502 covers the second substrate 104 and the patterned electrode layer 104a, and exposes a portion of the patterned electrode layer 104a located above the first lead 102a in the edge region 10b. Since the thicknesses of the first alignment layer 500 and the second alignment layer 502 are quite small compared to the height of the space S, in the presence of the first alignment layer 500 and the second alignment layer 502, the above-mentioned first distance D1, The two distances D2 , the third distance D3 and the fourth distance D4 may include the thicknesses of the first alignment layer 500 and the second alignment layer 502 .

In this embodiment, the material of the first lead 102a and the second lead 102b may be a conductive metal, such as copper. The patterned electrode layer 104a can be a transparent electrode, and its material can be indium tin oxide (ITO) or indium zinc oxide (IZO).

Returning to FIG. 1 , FIG. 2A , FIG. 2B and FIG. 2C , the first conductive pads 110 a are disposed at the sides of the display panel 10 and are connected to the patterned electrode layer 104 a , the first pins 102 a and the first pins 102 a spacer layer 108 above. In addition, the first conductive pad 110a extends between the patterned electrode layer 104a and the spacer layer 108 . The first pin 102a can be electrically connected to the patterned electrode layer 104a through the first conductive pad 110a. In addition, since the first conductive pads 110a extend between the patterned electrode layer 104a and the spacer layer 108, the contact area between the first conductive pads 110a and the patterned electrode layer 104a is increased, thereby ensuring the first pins Electrical connection between 102a and patterned electrode layer 104a. In addition, since the spacer layer 108 is disposed on the first lead 102a, the amount of the first conductive pad 110a extending between the patterned electrode layer 104a and the spacer layer 108 can be reduced to avoid material waste. Furthermore, since the first distance D1 is 6% to 60% of the fourth distance D4, the first conductive pad 110a can be prevented from being broken due to the excessive distance between the first lead 102a and the patterned electrode layer 104a. Therefore, the first lead 102a and the patterned electrode layer 104a cannot be electrically connected.

In addition, the second conductive pads 110b are disposed at the side of the display panel 10, and are connected to the second pins 102b and the spacer layer 108 on the second pins 102b, but are not connected to the patterned electrodes 104a. In detail, in this embodiment, since the second lead 102b does not need to be electrically connected to the patterned electrode 104a, the portion of the patterned electrode 104a above the second lead 102b does not extend to the second substrate 104 side and exposed at the side. In this way, the second conductive pads 110b are not in contact with the patterned electrodes 104a. In addition, since the second distance D2 is less than 6% of the fourth distance D4, the second conductive pad 110b can be prevented from extending between the patterned electrode layer 104a and the spacer layer 108 during the manufacturing process, so as to further ensure the second conductive contact Pad 110b does not make contact with patterned electrode 104a.

In addition, in the area between two adjacent pins, since the third distance D3 is less than 6% of the fourth distance D4, the adjacent first conductive pads 110a and/or the second conductive pads 110b will not extends into this area. In detail, since the third distance D3 is less than 6% of the fourth distance D4, the conductive pad material can be effectively prevented from entering the above-mentioned areas during the manufacturing process of the first conductive pad 110a and the second conductive pad 110b. In this way, the formed conductive pads will not extend into the above-mentioned areas, which can avoid material waste and avoid short circuits between adjacent conductive pads.

After the external circuit board is electrically connected to the display panel of the present invention, the display device of the present invention can be constructed. This will be explained below.

3A is a schematic cross-sectional view of a display device according to an embodiment of the present invention along line A-A in FIG. 1 . FIG. 3B is a schematic cross-sectional view of the display device according to the embodiment of the present invention along the line B-B in FIG. 1 . FIG. 3C is a schematic cross-sectional view of the display device according to the embodiment of the present invention along the line C-C in FIG. 1 . In FIGS. 3A , 3B and 3C, the same elements as those in FIGS. 2A, 2B and 2C will not be further described.

Referring to FIGS. 3A , 3B and 3C , in this embodiment, the display device 30 includes a display panel 10 , an external circuit board 300 and a conductive adhesive layer 302 . The external circuit board 300 mainly includes a substrate, circuit patterns disposed on the substrate, pins for connecting with external components, and a chip disposed on the circuit patterns, and these components are well known to those skilled in the art, and are not further described herein. instruction. In addition, in order to make the drawings clear, FIGS. 3A , 3B and 3C simply illustrate a part of the external circuit board 300 , and do not illustrate the above-mentioned components.

3A, 3B and 3C at the same time, in this embodiment, the conductive adhesive layer 302 is disposed on the side of the display panel 10 and covers the first conductive pads 110a and the second conductive pads 110b, and is connected to an external circuit The board 300 is disposed on the conductive adhesive layer 302 . The conductive adhesive layer 302 is, for example, a film layer formed by anisotropic conductive paste (ACP) or anisotropic conductive film (ACF). The external circuit board 300 can be bonded and electrically connected to the display panel 10 via the conductive adhesive layer 302 . The external circuit board 300 is, for example, a chip on film (COF) substrate. In this way, the display device 30 of the present embodiment is constructed. It can be seen from FIG. 3A that since the contact area between the first conductive pad 110a and the patterned electrode layer 104a is increased, the electrical connection between the first pin 102a and the patterned electrode layer 104a is ensured, thereby ensuring The performance of the display device 30 is improved. In addition, as can be seen from FIG. 3B and FIG. 3C , due to the arrangement of the spacer layer 108 , the extension of the second conductive pad 110b to contact the patterned electrode 104a and the generation between adjacent conductive pads are effectively avoided. short circuit, thereby ensuring the performance of the display device 30 .

In addition, as shown in FIG. 3C , in the region between two adjacent conductive pads, since there is no conductive pad, the conductive adhesive layer 302 is directly connected to the first substrate 102 , the second substrate 104 and the spacer layer 108 get in touch with. In addition, since the third distance D3 is less than 6% of the fourth distance D4, the conductive adhesive layer 302 does not extend into the above-mentioned area, so the usage amount of the conductive adhesive layer 302 can be reduced, and the infiltration of the conductive adhesive layer 302 can be avoided. short circuit problem.

In addition, in the embodiment shown in FIG. 5A , FIG. 5B and FIG. 5C , the first conductive pads 110 a are disposed at the sides of the display panel 10 and are connected to the patterned electrode layer 104 a , the first pins 102 a and located on the side of the display panel 10 . The spacer layer 108 on the first lead 102a. The second alignment layer 502 exposes a portion of the patterned electrode layer 104a above the first lead 102a in the edge region 10b. Therefore, the first conductive pad 110a extends between the patterned electrode layer 104a and the spacer layer 108, and since the second alignment layer 502 exposes part of the patterned electrode layer 104a, the first conductive pad 110a and the patterned electrode layer are The contact area between the 104a is increased, so the electrical connection between the first lead 102a and the patterned electrode layer 104a can be more ensured. In addition, since the spacer layer 108 is disposed on the first lead 102a, the amount of the first conductive pad 110a extending between the patterned electrode layer 104a and the spacer layer 108 can be reduced to avoid material waste. Furthermore, since the first distance D1 is 6% to 60% of the fourth distance D4, the first conductive pad 110a can be prevented from being broken due to the excessive distance between the first lead 102a and the patterned electrode layer 104a. As a result, the first pin 102a and the patterned electrode layer 104a cannot be electrically connected.

In addition, since the second distance D2 is less than 6% of the fourth distance D4, the second conductive pad 110b can be prevented from extending between the patterned electrode layer 104a and the spacer layer 108 during the manufacturing process, so as to further ensure the second conductive contact Pad 110b does not make contact with patterned electrode 104a.

In addition, since the third distance D3 is less than 6% of the fourth distance D4, during the manufacturing process of the first conductive pad 110a and the second conductive pad 110b, the conductive pad material can be effectively prevented from entering the above-mentioned area, and the material waste, and avoid short circuits between adjacent conductive pads. In detail, in the manufacturing process of the first conductive pads 110a and the second conductive pads 110b, the materials (eg, silver paste) of the first conductive pads 110a and the second conductive pads 110b are usually printed on the display panel first. 10, and then a part of the material is removed by laser processing to form a first conductive pad 110a and a second conductive pad 110b. Since the third distance D3 is less than 6% of the fourth distance D4, the printed material will not enter the above-mentioned area, thus avoiding material waste and short circuit problems.

In the above embodiment, the spacer layer 108 in the region between two adjacent pins has flat sidewalls, as shown in FIGS. 2C and 3C , but the present invention is not limited thereto. In other embodiments, the sidewall of the spacer layer 108 in the region between two adjacent pins may have a recess 108a (as shown in FIG. 4A ), and the external circuit board 300 is connected to the external circuit board 300 via the conductive adhesive layer 302 . After the display panel 10 is bonded, the conductive adhesive layer 302 may extend into the recess 108a (as shown in FIG. 4B ). In this way, the bonding strength between the external circuit board 300 and the display panel 10 can be further increased.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Display panel 10a: Central District 10b: Edge Zone 10c: junction zone 30: Display device 102: The first substrate 102a: first pin 102b: second pin 104: Second substrate 104a: Patterned Electrodes 106: Frame glue 108: Spacer Layer 108a: Sag 110a: first conductive pad 110b: second conductive pad 300, COF: external circuit board 302: Conductive Adhesive Layer 500: the first alignment layer 502: the second alignment layer D1: first distance D2: Second distance D3: The third distance D4: Fourth distance LC: liquid crystal S: space

FIG. 1 is a schematic side view of a display panel according to an embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line A-A in FIG. 1 . FIG. 2B is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line B-B in FIG. 1 . FIG. 2C is a schematic cross-sectional view of the display panel according to the embodiment of the present invention along the line C-C in FIG. 1 . 3A is a schematic cross-sectional view of a display device according to an embodiment of the present invention along line A-A in FIG. 1 . FIG. 3B is a schematic cross-sectional view of the display device according to the embodiment of the present invention along the line B-B in FIG. 1 . FIG. 3C is a schematic cross-sectional view of the display device according to the embodiment of the present invention along the line C-C in FIG. 1 . 4A and 4B are respectively schematic cross-sectional views of a display panel and a display device according to another embodiment of the present invention, taken along the line C-C in FIG. 1 . 5A is a schematic cross-sectional view of a display panel according to another embodiment of the present invention along the line A-A in FIG. 1 . 5B is a schematic cross-sectional view of a display panel according to still another embodiment of the present invention, taken along line B-B in FIG. 1 . FIG. 5C is a schematic cross-sectional view of a display panel according to another embodiment of the present invention along the line C-C in FIG. 1 .

10: Display panel

10a: Central District

10b: Edge Zone

10c: junction zone

102: The first substrate

102a: first pin

104: Second substrate

104a: Patterned Electrodes

106: Frame glue

108: Spacer Layer

110a: first conductive pad

500: the first alignment layer

502: the second alignment layer

D1: first distance

D4: Fourth distance

LC: liquid crystal

S: space

Claims (9)

A display device, comprising: a display panel with a central area and an edge area, comprising: a first substrate, wherein a plurality of first pins and a plurality of second pins are arranged on the first substrate and extend to the edge in the region, and exposed at the side of the first substrate; a second substrate, disposed relative to the first substrate, wherein the patterned electrode layer is disposed on the second substrate and partially exposed to the first substrate At the side edges of two substrates; a sealant, disposed between the first substrate and the second substrate; and a spacer layer, disposed on the first substrate and located in the edge region, and covering the The first pin and the second pin, wherein the thickness of the spacer layer on the first pin is smaller than the thickness of the remaining part of the spacer layer; a plurality of first conductive pads are arranged on the at the side of the display panel and connecting the patterned electrode layer, the first lead and the spacer layer on the first lead, wherein the first conductive pad extends to the between the patterned electrode layer and the spacer layer on the first pin; a plurality of second conductive pads are arranged at the side of the display panel and connect the second pin with the spacer on the first pin; the spacer layer on the second pin; The conductive adhesive layer is arranged on the side of the display panel and covers the first conductive pad and the second conductive pad; and an external circuit board is arranged on the conductive adhesive layer. The display device according to claim 1, wherein there is a first distance between the spacer layer on the first lead and the patterned electrode layer, and the space on the second lead There is a second distance between the layer and the patterned electrode layer, and a third distance between the spacer layer and the patterned electrode layer on the first substrate between two adjacent pins , there is a fourth distance between the first lead or the second lead and the patterned electrode layer in the central area, and the first distance is greater than the second distance and the first distance three distances. The display device of claim 2, wherein the first distance is 6% to 60% of the fourth distance. The display device of claim 2, wherein the second distance is less than 6% of the fourth distance. The display device of claim 2, wherein the third distance is less than 6% of the fourth distance. The display device of claim 2, wherein the third distance is less than or equal to the second distance. The display device of claim 1, wherein the spacer layer on the first substrate between the first pin and the second pin is exposed at the side edge of the display panel The surface has a depression, and a part of the conductive adhesive layer is located in the depression. The display device of claim 1, further comprising a first alignment layer covering the first substrate, the first leads, the second leads and the spacer layer. The display device of claim 1, further comprising a second alignment layer covering the second substrate and the patterned electrode layer, and exposing the edge region above the first lead Part of the patterned electrode layer.

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