TW202207498A - Flat display device and manufacturing method of flat display device - Google Patents

Abstract

A flat display device including a substrate and a plurality of side wires is provided. The substrate has a top surface and a bottom surface opposite to the top surface and a side surface connecting between the top surface and the bottom surface. The side surface has at least one wire disposing part. The wire disposing part extends along an arc trace on a plane of the substrate. The side wires extend from the top surface, passing through the wire disposing part of the side surface to the bottom surface. A manufacturing method of a flat display device is also provided herein.

Description

Flat display device and method of manufacturing the same

The present invention relates to a flat display device and a manufacturing method of the flat display device.

In response to the diversified applications of display devices, various manufacturing technologies and product designs are constantly being introduced. In order to provide more diverse applications, products suitable for curved display panels have been proposed one after another. However, products currently suitable for curved display panels generally require wide and long bezels to engage active elements or passive elements and the like. As such, the size of the display device is limited.

The present invention provides a flat display device, which utilizes the design of side wires to reduce the frame.

The present invention provides a manufacturing method of a flat display device, which can produce a flat display device that meets the requirements of narrow frame design.

The flat display device of the present invention includes a substrate and a plurality of side wires. The substrate has opposite top and bottom surfaces, and side surfaces connected between the top and bottom surfaces. The side surface has wire setting parts, and the wire setting parts are distributed along arc-shaped tracks on the plane of the substrate. The side lead wires extend continuously from the top surface of the substrate to the bottom surface through the lead wire setting portion.

In an embodiment of the present invention, the flat panel display device further includes a plurality of wire pads. The wire pads are disposed in a peripheral area of at least one of the top surface and the bottom surface of the substrate. Each of the plurality of wire pads has a bonding surface, and the bonding surface is in contact with one of the plurality of side wires.

In an embodiment of the present invention, the ends of the plurality of side wires are arranged in a row substantially along a straight line. The line width of the side conductors closer to the center of the column is wider, and the line width of the side conductors closer to the edge of the column is narrower.

In one embodiment of the present invention, each of the plurality of side conductors has a side segment. The side segment includes a side etch resist layer and a side conductor layer. The side etching resist layer is disposed on the side surface of the substrate. The side conductor layer is sandwiched between the side etching resist layer and the side surface of the substrate. Side sections closer to the column edge have thicker side etch resists, and side sections closer to the center of the column have thinner side etch resists. The side conductor layers of the side segments have substantially the same thickness.

In one embodiment of the present invention, each of the plurality of side wires has a curved end. The ends of the plurality of side wires are bent toward the same side, and the ends of the plurality of side wires are generally arranged along an arc trajectory.

In an embodiment of the present invention, each of the plurality of side wires includes a conductor layer and an etch-resistant layer, and the conductor layer is sandwiched between the etch-resistant layer and the substrate. The conductor layer shrinks inwardly relative to the etch-resistant layer, so that the substrate, the conductor layer and the etch-resistant layer form an undercut structure along the periphery of the conductor layer.

In an embodiment of the present invention, the above flat panel display device further includes at least one circuit board. The circuit board is arranged on the bottom surface of the substrate, and is electrically connected with the plurality of side wires.

In an embodiment of the present invention, the wire setting portion includes a first wire setting portion and a second wire setting portion. The radius of curvature of the first wire setting portion is larger than the radius of curvature of the second wire setting portion. The arrangement pitch of the plurality of side wires in the first wire arrangement portion is greater than the arrangement pitch of the second wire arrangement portion.

The manufacturing method of the flat display device of the present invention includes the following steps, but is not limited thereto. A base plate is provided, wherein the base plate has opposite top and bottom surfaces, and a side surface connected between the top surface and the bottom surface, the side surface has a wire setting part, and the wire setting part is arc-shaped on the plane of the base plate. A conductor material layer is formed, wherein the conductor material layer continuously covers the top surface of the substrate, the wire arrangement portions on the side surfaces, and the bottom surface. A resist pattern is placed on the transfer tool. The side surface of the substrate is abutted against the transfer tool, and the substrate is rotated relative to the transfer tool to transfer the anti-etching pattern onto the conductor material layer along the wire arrangement portion. A portion of the conductor material layer not shielded by the etch-resistant pattern is removed to form a plurality of side wires.

In an embodiment of the present invention, the ends of the plurality of side wires are bent along the rotation direction of the substrate.

Based on the above, the flat display device according to the embodiment of the present invention includes side wires arranged on the edge of the substrate, and the side wires continuously extend from the top surface of the substrate to the bottom surface through the wire setting portions on the side surfaces, so that it can be applied to a display panel with an arc shape. The flat-panel display device can reduce the frame width of the flat-panel display device to achieve a narrow frame design.

1A to FIG. 1E are schematic top views of some steps of manufacturing side wires of a flat display device according to some embodiments of the present invention;

Referring to FIG. 1A and FIG. 2A , a substrate 100 is provided, and a driving circuit structure 110 is pre-formed on the substrate 100 . The substrate 100 is an arc-shaped substrate having a certain mechanical strength and capable of supporting objects for disposing a plurality of film layers and/or objects thereon. In some embodiments, the material of the substrate 100 includes glass, polymer materials, ceramics, and the like. In other embodiments, the substrate 100 may be a multi-layer substrate, which is formed by stacking multiple sub-layers.

The substrate 100 has a top surface 102 and a bottom surface 104 opposite to the top surface 102 , and a side surface 106 connected between the top surface 102 and the bottom surface 104 . In this embodiment, FIG. 1A takes an example in which the top surface 102 of the substrate 100 is circular, but the invention is not limited to this. In other embodiments, the top surface 102 may be shaped with a combination of straight and curvilinear profiles or with only curvilinear profiles. In this embodiment, the side surface 106 is substantially extended along the Z direction by the contour edge of the top surface 102 , so the side surface 106 is marked on the contour of the top surface 102 in FIG. 1A for the convenience of description. The side surface 106 has at least one wire arrangement portion 106c, and the wire arrangement portion 106c is distributed along an arc-shaped track on the plane of the substrate 100 . When the top surface 102 is circular, the side surface 106 is configured as an annular surface with the center of the top surface 102 as the axis. On the other hand, the normal direction of the side surface 106 is different from that of the top surface 102 and also different from that of the bottom surface 104 . In some embodiments, the normal vectors of the top surface 102 and the bottom surface 104 may be parallel to each other, but not limited thereto. For example, the top surface 102 and the bottom surface 104 are respectively planes parallel to the X direction and the Y direction, and the side surface 106 is parallel to the Z direction, for example, the top surface 102 , the bottom surface 104 and the side surface 106 form a cylinder, for example.

The driving circuit structure 110 may include pixel pads 112 and wire pads 114 . In this embodiment, the pixel pads 112 and the wire pads 114 are both disposed on the top surface 102 of the substrate 100 . Specifically, the pixel pads 112 arranged in an array such as a display area on the top surface 102 of the substrate 100 are suitable for bonding, such as light emitting diodes or similar display elements, and the wire pads 114 are, for example, arranged on the top surface 102 of the substrate 100 . surrounding area. In some embodiments, the driving circuit structure 110 may further include a pixel circuit (not shown in FIG. 1A ) electrically connected to the pixel pads 112 and the wire pads 114 . For example, the pixel circuit (not shown in FIG. 1A ) may include signal lines, active elements, passive elements, etc., wherein the active elements are transistors, and the passive elements are capacitors, but not limited thereto. In some embodiments, the pixel circuit (not shown in FIG. 1A ) may be fabricated on the top surface 102 of the substrate 100 by means of film deposition and lithography or printing. Therefore, the above-mentioned transistor can be a thin film transistor, and the capacitor structure can be formed by stacking a conductive layer and a dielectric layer. In addition, in some embodiments, the driving circuit structure 110 may further include wire pads (not shown in FIG. 1A ) and/or corresponding wires disposed on the bottom surface 104 of the substrate 100 .

In FIG. 1A , the number of the wire bonding pads 114 is multiple, and the plurality of wire bonding pads 114 can be arranged along the X direction. The wire pads 114 are located on the top surface 102 , and the arrangement positions of the wire pads 114 are closer to the side surface 106 than the pixel pads 112 , especially, closer to the wire arrangement portion 106 c . Specifically, each wire pad 114 may have a bonding surface 114a. The bonding surface 114a may be the surface where the wire pad 114 contacts with the side wire (not shown in FIG. 1A ) to be formed subsequently. The bonding surfaces 114 a of the wire bonding pads 114 are arranged in a line along a straight line L1 adjacent to the side surface 106 , for example. It should be noted that the linear trajectory L1 in the drawings is a virtual line segment in the present embodiment for the convenience of clearer description, and is not a line segment that actually exists on the substrate 100 .

For example, the linear trajectory L1 may overlap an imaginary chord of the circular outline of the top surface 102, but is not limited thereto. In this embodiment, the wire pads 114 can be regularly arranged on the straight track L1. In an alternative embodiment, the wire pads 114 may be irregularly arranged along the straight line L1 or staggered into two rows, but the bonding surfaces 114a intended to be in contact with the subsequently fabricated side wires may be substantially located on the straight line L1. In some embodiments, a protective layer (not shown in FIG. 1A ) may also be formed on the wire pads 114 . For example, the protective layer (not shown in FIG. 1A ) may have a plurality of openings respectively corresponding to each wire pad 114 , each wire pad 114 is not covered by the protective layer in the area of the plurality of openings to define a bond The surface 114a enables the side wires to be fabricated subsequently to be in contact with the wire pads 114 in the corresponding openings.

Referring to FIG. 1B and FIG. 2B , a conductor material layer 122 is formed on the substrate 100 . The conductor material layer 122 may cover the peripheral area of the top surface 102 of the substrate 100 . In some embodiments, the conductor material layer 122 may also partially cover the display area of the top surface 102 of the substrate 100 . In other embodiments, a protective film or a similar structure may be used to cover the pixel pads 112 in the display area before forming the conductive material layer 122 , so that the conductive material layer 122 does not contact the pixel pads 112 . As shown in the top view of FIG. 1B , the conductor material layer 122 is, for example, annular. For example, the conductor material layer 122 presents a ring shape centered on the center of the top surface 102 . As shown in cross-sectional view 2B , the conductor material layer 122 continuously covers the top surface 102 of the substrate 100 , the lead wire installation portion 106 c of the side surface 106 , and the bottom surface 104 . The conductor material layer 122 may be formed on the substrate 100 by edge sputtering. The material of the conductor material layer 122 includes copper, aluminum, molybdenum, silver, gold, nickel, titanium, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and the like. The conductor material layer 122 may contact and directly cover the wire pads 114 . When pads (eg, wire pads, not shown) are provided on the bottom surface 104 , the conductor material layer 122 may contact and directly cover the wire pads on the bottom surface 104 .

Referring to FIG. 1C and FIG. 2C , the etching resist pattern P1 is disposed on the transfer tool 130 . Specifically, the transfer tool 130 may include a roller 132 and a carrier 134 , and the anti-etching pattern P1 is formed on the carrier 134 by, for example, coating, printing, or adhesion. After that, the roller 132 is moved along the moving direction D1 to press the carrier 134 against the wire setting portion 106c of the side surface 106 of the substrate 100, so that the etching resist pattern P1 on the carrier 134 is attached to the conductor material layer 122 at the wire setting portion 106c. In some embodiments, the anti-etching patterns P1 are, for example, strip-shaped patterns arranged side by side on the carrier 134 . The material of the anti-etching pattern P1 can be a conductive material, such as silver glue. In some embodiments, the material of the etching resist pattern P1 may be an insulating material, such as polyester resins, phenolic resins, alkyd resins, and polycarbonate resins. , Polyamide resins, Polyurethane resins, Silicone resins, Epoxy resins, Polyethylene resins, Acrylic resins, Polyphenylene Polystyrene resins, polypropylene resins, etc.

In some embodiments, the carrier 134 can be made of an elastic material, such as rubber. In this way, when the carrier 134 is pressed against the wire setting portion 106c of the substrate 100, deformation occurs, so that a part of the carrier 134 can be pressed against the conductor material layers 122 on the top surface 102 and the bottom surface 104, and the etching resist pattern P1 is imprinted on On the conductor material layer 122 on the top surface 102 and the bottom surface 104 . For example, the roller 132 of the transfer tool 130 can move horizontally along the moving direction D1 toward the wire arrangement portion 106c of the substrate 100 during the transfer process to transfer the anti-etching pattern P1 to the wire arrangement portion 106c and the top surface of the side surface 106 . 102 and the conductor material layer 122 on the bottom surface 104 . Here, the moving direction D1 is, for example, parallel to the Y direction, but the present invention is not limited to this. In other embodiments, the moving direction D1 may be parallel to the normal vector of the tangent plane corresponding to any point on the wire arrangement portion 106 c of the side surface 106 . In other embodiments, after the transfer tool 130 is moved toward the substrate 100 along the moving direction D1 to the pressing side 106 , the transfer tool 130 may be further rotated in a direction perpendicular to the moving direction D1 as an axis to transfer the corresponding anti-etching pattern P1 Transferred to the conductor material layer 122 on the top surface 102 and the bottom surface 104 . For example, when the moving direction D1 is parallel to the Y direction, the direction perpendicular to the moving direction D1 is, for example, the X direction.

After the transfer, the strip-shaped anti-etching pattern P1 can be attached to the conductor material layer 122 and the anti-etching pattern P1 can continuously extend from the top surface 102 to the bottom surface 104 through the wire arrangement portion 106c. Referring to FIG. 1D and FIG. 2D , after removing the transfer tool 130 , a curing step may be performed on the etching resist pattern P1 attached to the conductor material layer 122 to form the etching resist layer 124 . The anti-etching layer 124 may have a stripe pattern, and the anti-etching layer 124 may continuously extend from the top surface 102 to the bottom surface 104 through the wire arrangement portion 106 c of the side surface 106 . A plurality of strip-shaped anti-etching layers 124 can be arranged along the X direction, and a plurality of strip-shaped anti-etching layers 124 can be disposed corresponding to the wire pads 114 . In some embodiments, the orthographic projection of the etch resist layer 124 on the top surface 102 in the Z direction may overlap the orthographic projection of the wire pads 114 on the top surface 102 in the Z direction. Even, the orthographic projection of the wire pads 114 on the top surface 102 in the Z direction may lie completely within the orthographic projection of the etch resist layer 124 on the top surface 102 in the Z direction. The plurality of strip-shaped anti-etching layers 124 are disposed corresponding to the wire pads 114 in a one-to-one manner, so each anti-etching layer 124 only overlaps one wire pad 114 . In some embodiments, the strip-shaped etch-resistant layer 124 has an end 124t, and the connection between the end 124t of the etch-resistant layer 124 is substantially parallel to the straight track L1.

Referring to FIGS. 1E and 2E , after the etch-resistant layer 124 is fabricated, a patterning step may be performed to remove the conductor material layer 122 not shielded by the etch-resistant layer 124 to form the conductor layer 126 . Methods of patterning the conductor material layer 122 include isotropic etching. For example, the patterning step is, for example, contacting the conductive material layer 122 not covered by the etch-resistant layer 124 with the etchant. Here, the etchant for patterning the conductor material layer 122 is selective to the conductor material layer 122 and the etch-resistant layer 124 . That is, the etchant used in the patterning step has, for example, a composition that does not react with the etching resist layer 124, so the etching resist layer 124 is substantially not damaged during the etching step.

The conductor layer 126 is disposed on the substrate 100 and has a stripe pattern corresponding to the etching resist layer 124 . The number of the strip-shaped conductor layers 126 may be the same as the number of the strip-shaped anti-etching layers 124 . The conductor layer 126 extends from the top surface 102 of the substrate 100 to the bottom surface 104 of the substrate 100 through the wire arrangement portion 106 c of the side surface 106 . In this embodiment, the anti-etching layer 124 and the conductor layer 126 stacked on each other can form a side wire 120 . In other words, the side wires 120 may include the anti-etching layer 124 and the conductor layer 126 , and the conductor layer 126 is sandwiched between the anti-etching layer 124 and the substrate 100 . The etch-resistant layer 124 may completely cover the conductor layer 126 .

The side wire 120 may include a top surface segment 120A, a bottom surface segment 120B, and a side surface segment 120C. The top surface segment 120A is disposed on the top surface 102 of the substrate 100 , and extends from the corner between the top surface 102 and the side surface 106 toward the wire pads 114 along the Y direction, or even beyond the wire pads 114 . The top surface section 120A contacts the wire pads 114 on the substrate 100 and can completely cover the wire pads 114 . The bottom surface segment 120B is disposed on the bottom surface 104 and extends along the Y direction, for example, from the corner between the bottom surface 104 and the side surface 106 .

The conductor material layer 122 of FIG. 1D may be overetched in the step of FIG. 1E to ensure that adjacent conductor layers 126 are disconnected from each other. Due to the over-etching, the outline of the conductor layer 126 can shrink relative to the outline of the etch-resistant layer 124 , so that the substrate 100 , the conductor layer 126 and the etch-resistant layer 124 form an undercut structure UC along the periphery of the conductor layer 126 . As shown in FIG. 2E , the end 124t of the etch-resistant layer 124 may protrude toward the pixel pad 112 relative to the end 126t of the conductor layer 126 , or the end 126t of the conductor layer 126 may be retracted relative to the end 124t of the etch-resistant layer 124 An undercut structure UC is formed.

Below, FIGS. 3A to 3C are used to illustrate the specific structures of the side wires suitable for some embodiments, and the wire structures of FIGS. 3A to 3C can be obtained by, for example, the steps of FIGS. 1A to 1E (and FIGS. 2A to 2E ). production, but this disclosure is not limited to this.

As can be seen from FIGS. 3A to 3C , the top surface 102 of the substrate 100 may be provided with wire pads 114 and side wires 120 . The side wires 120 extend continuously from the top surface 102 of the substrate 100 to the bottom surface 104 through the wire setting portions 106 c of the side surfaces 106 . In some embodiments, the bonding surfaces 114a of the wire pads 114 may be in contact with the side wires 120 . Specifically, the side wires 120 cover the bonding surfaces 114 a of the wire pads 114 , so the side wires 120 may extend on the top surface 102 to the bonding faces 114 a of the overlapping wire pads 114 , for example, along the Y direction, and even the ends of the side wires 120 . 120t may extend beyond the wire pads 114 . In some embodiments, the ends 120t of the side wires 120 may be arranged substantially along a straight line parallel to the straight line track L1.

In some embodiments, as shown in FIG. 3A to FIG. 3C , the plurality of side wires 120 may respectively have different line widths W1 , and the plurality of side wires 120 with different line widths W1 are substantially along a straight line of line II′ Tracks are arranged side by side in columns. In this embodiment, the line width W1 of each side wire 120 refers to the width of each side wire 120 along the X direction. Specifically, the line width W1 of the side conducting wire 120 closer to the column center Rc is wider, and the line width W1 of the side conducting wire 120 closer to the column edge Rb is narrower. For example, among the three adjacent side wires 120, the side wire 120 with the narrowest line width W1 is not arranged in the center. In other words, among the three adjacent side conductors 120, the line width W1 of the central side conductor 120 is not simultaneously narrower than the line width W1 of the side conductors 120 on both sides.

In some embodiments, different line widths W1 of the side wires 120 may be caused by the fabrication method. For example, in the steps of FIG. 1C and FIG. 2C , when the transfer tool 130 is pressed against the wire setting portion 106c of the substrate 100, since the wire setting portion 106c is arc-shaped and the transfer tool 130 is substantially linear, Different parts of the wire arrangement portion 106c have different contact times with the transfer tool 130, and correspondingly, the pressures received by the anti-etching patterns P1 at different positions are also different. In FIG. 1C , the portion of the wire arrangement portion 106 c that is farther from the transfer tool 130 is subjected to less pressure, and the portion closer to the transfer tool 130 is subjected to greater pressure. On the section subjected to greater pressure, the anti-etching pattern P1 will be flattened, so that the width of the anti-etching pattern P1 attached to the conductor material layer 122 becomes larger. Correspondingly, the width of the etching resist pattern P1 is relatively small on the section subjected to less pressure. In this way, the side wires 120 fabricated by using the above-mentioned anti-etching patterns P1 with different widths can have different line widths corresponding to the anti-etching patterns P1. The width of the etching resist pattern P1 may vary as shown in FIGS. 3A to 3C , and the width becomes wider toward the center Rc of the column.

On the other hand, the ends 120t of the plurality of side wires 120 are also generally arranged along a straight line parallel to the straight track L1, so the plurality of side wires 120 can respectively have different extension lengths EL1. In this embodiment, the extension length EL1 of each side wire 120 refers to the length of each side wire 120 extending along the Y direction on the top surface 102 or the bottom surface 104 . Specifically, the side conductors 120 closer to the column center Rc have longer extension lengths EL1 , and the side conductors 120 closer to the column edge Rb have shorter extension lengths EL1 . Therefore, the side wire 120 with the wider line width W1 has the longer extension length EL1, and the side wire 120 with the narrower line width W1 has the shorter extension length EL1. In this way, the impedances of the plurality of side wires 120 can be matched with each other, so as to have substantially similar conductive transmission capabilities, which helps to maintain the quality of the display device.

The cross-sectional structure of FIG. 2E can be applied to this embodiment. It can be seen from FIGS. 2E and 3A to 3C that the top surface segment 120A and the bottom surface segment 120B may have corresponding structures. For example, the length of the top surface segment 120A along the Y direction can be substantially equal to the length of the bottom surface segment 120B along the Y direction; the width of the top surface segment 120A along the X direction can be substantially equal to the width of the bottom surface segment 120B along the X direction. In other embodiments, the structures of the top surface segment 120A and the bottom surface segment 120B can be adjusted according to the requirements of process design, but the present invention is not limited thereto. The side segment 120C is disposed on the side 106 and extends along the Z direction to connect to the top segment 120A and the bottom segment 120B, and the side segments 120C are arranged side by side on the side 106 of the substrate 100 . Therefore, as shown in FIG. 3A , the side wires 120 are three-dimensional wires having a three-dimensional U-shaped structure surrounding the edge of the substrate 100 .

Similarly, the etch resist layer 124 may include a top etch resist layer 124A, a bottom etch resist layer 124B, and a side etch resist layer 124C. The conductor layer 126 may include a top conductor layer 126A, a bottom conductor layer 126B and a side conductor layer 126C. In other words, the top segment 120A may include a top etch resist layer 124A and a top conductor layer 126A; the bottom segment 120B may include a bottom etch resist 124B and a bottom conductor layer 126B; the side segment 120C may include a side etch resist 124C and a side conductor Layer 126C.

As shown in FIGS. 3B and 3C , the thicknesses t1 of the top conductor layer 126A, the bottom conductor layer 126B, and the side conductor layer 126C are substantially equal to each other. For example, the conductive material layer 122 formed by edge sputtering surrounds the edge of the substrate 100 and may have a uniform thickness. Therefore, the conductor layer 126 patterned from the conductor material layer 122 also has a uniform thickness. In other words, for the same side conductor 120 , the thickness t1 of the top conductor layer 126A located on the top surface 102 , the thickness t1 of the bottom conductor layer 126B located on the bottom surface 104 , and the thickness t1 of the side conductor layer 126C located on the side surface 106 substantially equal. In addition, the thickness t1 of the top conductor layer 126A of the side conductor 120 near the column center Rc is substantially equal to the thickness t1 of the top conductor layer 126A of the side conductor 120 near the column edge Rb. Similarly, the bottom conductor layers 126B of the wires 120 on different sides have substantially the same thickness t1 , and the side conductor layers 126C of the wires 120 on different sides have substantially the same thickness t1 .

The thickness t2 of the top etch resist layer 124A and the thickness t2 of the bottom etch resist layer 124B may be approximate. Specifically, the thickness t2 of the top etch resist layer 124A near the column center Rc is substantially equal to the thickness t2 of the top etch resist 124A near the column edge Rb. The thickness t2 of the bottom etch resist layer 124B near the column center Rc is substantially equal to the thickness t2 of the bottom etch resist 124B near the column edge Rb. On the other hand, the top etch resist layer 124A and the bottom etch resist layer 124B may have corresponding structures. For example, the thickness t2 of the top etch resist layer 124A is substantially equal to the thickness t2 of the bottom etch resist layer 124B.

In some embodiments, as shown in FIG. 3C , the thickness t3 of the side etch resist layer 124C of the side segment 120C may be different. For example, in the step of FIG. 1C , the etching resist pattern P1 corresponding to the side conductors 120 closer to the row center Rc is subjected to greater pressure, so the side segments 120C of the side conductors 120 closer to the row center Rc have thinner The side etching resist layer 124C. Meanwhile, the side section 120C of the side wire 120 which is closer to the column edge Rb has the thicker side etch resist layer 124C. For example, among the side segments 120C of the three adjacent side wires 120 , the side segment 120C with the side etching resist layer 124C having the thickest thickness t3 is not arranged in the center. In other words, in the side segments 120C of the three adjacent side conductors 120 , the thickness t3 of the central side etch resist layer 124C is not simultaneously thicker than the thickness t3 of the side etch resist layers 124C on both sides.

According to the above manufacturing steps, as shown in FIG. 3B and FIG. 3C , the sidewall of the conductor layer 126 can be retracted relative to the sidewall of the etch-resistant layer 124 to form an undercut structure UC along the sidewall of the conductor layer 126 . The undercut structure UC along the end 126t of the conductor layer 126 in FIG. 2E and the undercut structure UC along the sidewall of the conductor layer 126 in FIGS. 3B and 3C may be a continuous body. Therefore, the undercut structure UC is substantially a structure distributed along the contour of the conductor layer 126 .

4A and 4B are schematic plan views of some steps of manufacturing a flat display device according to some embodiments of the present invention; FIGS. 5A and 5B are schematic cross-sectional views along the line A-A' in FIGS. 4A and 4B . Referring to FIGS. 4A and 5A , after the steps in FIGS. 1A to 1E have been completed and the side wires 120 are formed, the circuit board 140 can be further bonded to the bottom surface 104 of the substrate 100 . The circuit board 140 can be electrically connected to the plurality of side wires 120 . The circuit board 140 may be a chip on film (COF), a printed circuit board, or the like that can be bonded to the traces or pads on the bottom surface 104 without being bonded to the top surface 102 . In this way, the periphery of the top surface 102 does not need to reserve a bonding area for bonding external circuit structures. In other words, a larger area can be left on the top surface 102 for the arrangement of functional elements such as light-emitting elements and display elements, thereby realizing the design of a narrow frame. When the anti-etching layer 124 is made of conductive material, the circuit board 140 can directly bond the anti-etching layer 124 of the plurality of side wires 120 . When the anti-etching layer 124 is made of insulating material, lines or pads may be further provided on the bottom surface 104 for bonding with the circuit board 140 .

Referring to FIG. 4B and FIG. 5B , a protective layer 150 is formed. So far, the fabrication of the flat display device 10 of this embodiment has been substantially completed. The protective layer 150 covers the plurality of side wires 120 and continuously covers the top surface 102 , the side surfaces 106 and the bottom surface 104 of the substrate 100 . Specifically, the protective layer 150 is disposed on the substrate 100 and covers the etching resist layer 124 . In FIG. 5B , in addition to covering the etching resist layer 124 , the protective layer 150 also fills the undercut structure UC, so that the protective layer 150 can contact the periphery of the conductor layer 126 . In other words, the protective layer 150 may wrap the side wires 120 such that the side wires 120 are sealed in the protective layer 150 . In some embodiments, the protective layer 150 undulates, for example, with the distribution and profile of the side conductors 120 . That is, the protective layer 150 is farther from the substrate 100 at the position corresponding to the side wires 120 , and closer to the substrate 100 at the interval of the side wires 120 . In some embodiments, the protective layer 150 may be a flat layer with a flat outer surface.

In some embodiments, the protective layer 150 may be formed on the substrate 100 by dipping, spraying, transfer printing, coating or transfer printing. For example, the protective layer 150 can be fabricated by immersing the substrate 100 in a solution of protective material to make the protective material adhere to the substrate 100 , and then the protective layer 150 can be formed after the protective material is cured. Materials of the protective layer 150 may include polyester resins, phenolic resins, alkyd resins, polycarbonate resins, polyamide resins, polyurethane Polyurethane resins, silicone resins, epoxy resins, polyethylene resins, acrylic resins, polystyrene resins, polypropylene resins ( polypropylene resins), or other insulating materials.

The flat panel display device 10 includes a substrate 100 , a driving circuit structure 110 , side wires 120 , a circuit board 140 and a protective layer 150 . In some embodiments, the flat panel display device 10 may be a device formed by bonding light-emitting elements and the like (not shown) to the pixel pads 112 . In other embodiments, the substrate 100 may be further provided with other functional elements such as touch elements, sensing elements, and the like. Specifically, the structural design and configuration relationship of the substrate 100 , the driving circuit structure 110 , the side wires 120 , the circuit board 140 and the protective layer 150 can be referred to the descriptions in the preceding paragraphs, and will not be repeated.

In the flat display device 10, the layout design of the side wires 120 may be as shown in FIG. 3A to FIG. 3C . For example, the side wires 120 continuously extend from the top surface 102 of the substrate 100 to the bottom surface 104 through the wire setting portions 106 c of the side surfaces 106 , and the ends 120 t of the side wires 120 are approximately parallel to each other along a straight line parallel to the X direction. Therefore, the plurality of side wires 120 may have different extension lengths EL1 respectively. For example, the side conductors 120 closer to the column center Rc have the longer extension length EL1, and the side conductors 120 closer to the column edge Rb have the shorter extension length EL1. In one embodiment, the plurality of side conductors 120 may have different line widths W1 respectively, and the plurality of side conductors 120 with different line widths W1 are generally arranged side by side along the above-mentioned straight track. For example, the line width W1 of the side conductive line 120 closer to the column center Rc is wider, and the line width W1 of the side conductive line 120 closer to the column edge Rb is narrower.

In some embodiments, as shown in FIG. 3C , each side wire 120 has a side segment 120C, and the side segment 120C includes a side etch resist layer 124C and a side conductor layer 126C. The side etch resist layer 124C is disposed on the side surface 106 of the substrate 100 , and the side conductor layer 126C is sandwiched between the side etch resist layer 124C and the side surface 106 of the substrate 100 . In one embodiment, the thickness t3 of the side etch resist layer 124C of the side segment 120C may be non-uniform. For example, the side segment 120C closer to the column edge Rb has the thicker side etch resist layer 124C, and the side segment 120C closer to the column center Rc has the thinner side etch resist layer 124C. In addition, the side conductor layers 126C of the side segments 120C have substantially the same thickness t1.

6A to 6C are schematic top views of some steps of manufacturing a flat display device according to some embodiments of the present invention; FIGS. 7A to 7C are schematic cross-sectional views along the line AA' in FIGS. 6A to 6C ; and FIG. 8 shows the present invention FIG. 9A and FIG. 9B are schematic top views of some steps of manufacturing a flat display device according to some embodiments of the present invention; FIGS. 10A and 10B are diagrams along the lines of FIGS. 9A and 9B . Schematic cross-section of the midline AA'. It must be noted here that this embodiment uses the element numbers and part of the content of the previous embodiment, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here. In addition, the arc locus L2 in FIG. 6A is a virtual line segment in the present embodiment for the convenience of clearer description, and is not a line segment that actually exists on the substrate 100 .

Referring to FIG. 6A and FIG. 7A , a substrate 100 is provided, and a driving circuit structure 210 is pre-formed on the substrate 100 . In this embodiment, the driving circuit structure 210 may include the pixel pads 112, the first wire pads 214 and the second wire pads 214'. Specifically, the pixel pads 112 and the first wire pads 214 are both disposed on the top surface 102 of the substrate 100 . The second wire pads 214' may be disposed on the bottom surface 104 of the substrate 100 corresponding to the first wire pads 214 . In this embodiment, the driving circuit structure 210 further includes a plurality of connecting wires 216 . Specifically, the connection traces 216 are disposed on the bottom surface 104 of the substrate 100, and are electrically connected to the second wire pads 214'. The connection traces 216 may be wires used to bond the second wire pads 214' to a circuit board or other external circuit structures intended to be bonded to the bottom surface 104 of the substrate 100. In one embodiment, the driving circuit structure 210 may further include a pixel circuit (not shown in FIG. 6A ) electrically connected to the pixel pad 112 and the first wire pad 214 .

In FIG. 6A , the number of the first wire bonding pads 214 is multiple, and the plurality of first wire bonding pads 214 can be arranged along the contour of the top surface 102 . The first wire pads 214 are located on the top surface 102 , and the arrangement position of the first wire pads 214 is closer to the side surface 106 than the pixel pads 112 , especially, closer to the wire arrangement portion 106 c . Specifically, each of the first wire pads 214 may have a bonding surface 214a. The bonding surface 214a may be the surface where the first wire pad 214 contacts with the side wire (not shown in FIG. 6A ) to be formed subsequently. The bonding surfaces 214 a of the first wire pads 214 surround the plurality of pixel pads 112 , for example, along the arc track L2 adjacent to the side surface 106 , and are arranged in an arc shape in the peripheral area of the top surface 102 of the substrate 100 . For example, the arc trajectory L2 may overlap an imaginary arc of the circular outline of the top surface 102 , but not limited thereto. In one embodiment, the contour of the top surface 102 is, for example, a circle, and the arc trajectory L2 can be a circular trajectory having the same center as the contour of the top surface 102 .

In this embodiment, the first wire pads 214 can be regularly arranged on the arc track L2, and the arc track L2 can be surrounded by a circle, but not limited thereto. In some embodiments, a protective layer (not shown in FIG. 6A ) may also be formed on the first wire pads 214 . For example, the protective layer (not shown in FIG. 6A ) may have a plurality of openings corresponding to the bonding surfaces 214 a of the first wire pads 214 , respectively, and each of the first wire pads 214 is not in the area of the plurality of openings. The bonding surface 214a is defined by being covered by the protective layer, so that the side wires formed subsequently can be in contact with the first wire pads 214 in the corresponding openings. FIG. 6A mainly shows the configuration design of the first wire bonding pad 214, and the design of FIG. 6A can also be applied to the second wire bonding pad 214', so the configuration design of the second wire bonding pad 214' will not be repeated.

Referring to FIG. 6B and FIG. 7B , a conductor material layer 122 is formed on the substrate 100 . The conductor material layer 122 may contact and directly cover the first wire pads 214 . On the other hand, the conductor material layer 122 may also contact and directly cover the second wire pads 214' (not shown) on the bottom surface 104. A conductor material layer 122 is formed on the substrate 100 . The conductor material layer 122 may cover the peripheral area of the substrate 100 and surround in a ring. The material of the conductor material layer 122 includes copper, aluminum, molybdenum, silver, gold, nickel, titanium, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and the like.

Referring to FIG. 6C and FIG. 7C , an etching resist layer 224 is formed on the conductor material layer 122 . The anti-etching layer 224 may have a stripe pattern, and the anti-etching layer 224 may extend from the top surface 102 to the bottom surface 104 continuously through the wire arrangement portion 106 c of the side surface 106 . A plurality of strip-shaped anti-etching layers 224 may be arranged along the contour of the top surface 102 , and a plurality of strip-shaped anti-etching layers 224 may be disposed corresponding to the first wire pads 214 . In this embodiment, the entire side surface 106 of the substrate 100 is expected to be provided with wires. As shown in FIG. 6C , the strip-shaped anti-etching layers 224 are radially arranged on the peripheral region of the top surface 102 , for example. Therefore, the entire side surface 106 can be regarded as the lead wire setting portion 106c. In some embodiments, the etch-resistant layer 224 may overlap the first wire pads 214 . The plurality of strip-shaped anti-etching layers 224 are disposed corresponding to the first wire pads 214 in a one-to-one manner, so each of the anti-etching layers 224 only overlaps one first wire pad 214 . In some embodiments, the strip-shaped anti-etching layer 224 has an end 224t, and the end 224t of the anti-etching layer 224 is arranged substantially along the arc track L2. In this embodiment, the ends 224t of the etching resist layer 224 are bent toward the same side, for example.

Below, FIG. 8 is used as an example to illustrate the fabrication steps of the etching resist layer 224 suitable for this embodiment, but the present disclosure is not limited thereto.

Referring to FIG. 8 , the etching resist pattern P2 is disposed on the transfer tool 130 . Specifically, the pre-designed anti-etching pattern P2 can be formed on the carrier 134 of the transfer tool 130 by, for example, coating, printing, or sticking. Next, the wire setting portion 106c of the substrate 100 is abutted against the transfer tool 130, and the substrate 100 is rotated relative to the transfer tool 130 to transfer the etching resist pattern P2 onto the conductor material layer 122 along the wire setting portion 106c. For example, the wire setting portion 106c can be abutted against the carrier 134, and the substrate 100 can be moved along the moving direction D2 and rotated along the rotating direction D3. In other embodiments, the substrate 100 may also be rotated relative to the transfer tool 130 along the rotation direction D3 while the transfer tool 130 is moving against the moving direction D2. Here, the movement direction D2 is, for example, parallel to the extending direction of the transfer tool 130 , and the rotation direction D3 is, for example, a direction perpendicular to the movement direction D2 as the rotation axis. For example, when the moving direction D2 is parallel to the plane of the X direction and the Y direction, the rotation direction D3 takes the Z direction as the rotation axis, for example. Therefore, the anti-etching pattern P2 on the carrier 134 can be transferred on the conductive material layer 122 on the wire arrangement portion 106 c (eg, the entire side surface 106 ), the top surface 102 and the bottom surface 104 , and on the top surface 102 and the bottom surface 104 The anti-etching pattern P2 is, for example, bent along the rotation direction D3 of the substrate 100 in compliance with the force in the rotation direction D3.

In some embodiments, the anti-etching patterns P2 are strip-shaped patterns arranged side by side on the carrier 134 , so after transferring, the strip-shaped anti-etching patterns P2 can be formed on the conductor material layer 122 . In one embodiment, the material of the etching resist pattern P2 can be an insulating material, such as polyester resin, phenolic resin, alkyd resin, polycarbonate resin, polyamide resin, polyurethane resin, silicone resin, epoxy resin , polyethylene resin, acrylic resin, polystyrene resin, polypropylene resin, etc.

After that, after the transfer tool 130 is removed, the etching resist pattern P2 attached to the conductor material layer 122 can be cured to form the etching resist layer 224 . Corresponding to the anti-etching pattern P2, the end 224t of the anti-etching layer 224 is bent, for example, along the rotation direction D3 of the substrate 100, as shown in FIG. 6C.

Referring to FIGS. 9A and 10A , after the etching resist layer 224 of FIG. 6C is fabricated, a patterning step may be performed to remove the conductor material layer 122 not covered by the etching resist layer 224 to form the conductor layer 226 . The method of removing the conductor material layer 122 may include performing a patterning step as described in FIG. 1E, wherein the conductor material layer 122 may be patterned with an etchant that does not react with the etch-resistant layer 224, so that the etch-resistant layer 224 is There is substantially no damage during the patterning step. In one embodiment, the conductor material layer 122 may be overetched to ensure that adjacent conductor layers 226 are disconnected from each other. For example, an undercut structure UC along the periphery of the conductor layer 226 may be formed. The undercut structure UC is essentially a structure distributed along the contour of the conductor layer 226 .

The conductor layer 226 may have a stripe pattern corresponding to the etching resist layer 224 . The number of the strip-shaped conductor layers 226 may be the same as the number of the strip-shaped anti-etching layers 224 . In this embodiment, the anti-etching layer 224 and the conductor layer 226 which are stacked on each other can form a side wire 220 . In other words, the side wires 220 may include the anti-etching layer 224 and the conductor layer 226 , and the conductor layer 226 is sandwiched between the anti-etching layer 224 and the substrate 100 . The etch-resistant layer 224 may completely cover the conductor layer 226 .

In the present embodiment, the side wires 220 extend continuously from the top surface 102 of the substrate 100 to the bottom surface 104 through the wire arrangement portion 106 c (eg, the entire side surface 106 ). Therefore, the side wires 220 are, for example, three-dimensional wires, which have a three-dimensional U-shaped structure and surround the edge of the substrate 100 . The side wires 220 may cover the bonding surfaces 214a of the first wire pads 214 and the bonding surfaces 214'a of the second wire pads 214'. As such, the side wires 220 can electrically connect the first wire pads 214 on the top surface 102 to the second wire pads 214' on the bottom surface 104. Specifically, on the top surface 102 of the substrate 100 , the side wires 220 may extend from the wire setting portion 106 c along the Y direction to the bonding surface 214 a of the first wire pads 214 , and even the ends 220 t of the side wires 220 extend beyond the first wires Pad 214 . On the bottom surface 104 of the substrate 100 , the side wires 220 may extend from the wire setting portion 106 c along the Y direction to the bonding surfaces 214 ′ a of the second wire pads 214 ′, even the ends 220 t of the side wires 220 extend beyond the second wire pads 214'. In other words, the side wire 220 substantially overlaps the bonding surface 214a and the bonding surface 214'a.

In this embodiment, each side wire 220 has a curved end 220t. Specifically, the end 220t of each side wire 220 corresponds to the transferred etching resist pattern P2 in FIG. 8 , and is bent in accordance with the rotation direction D3 of the substrate 100 . In this way, the ends 220t of the side wires 220 are bent toward the same side. Referring to FIG. 9A , the layout of each side wire 220 on the top surface 102 may be extended from the side surface 106 toward the center of the substrate 100 and the ends 220t are offset counterclockwise relative to the centripetal direction.

A plurality of side wires 220 may be arranged along the contour of the top surface 102 . Specifically, the plurality of side wires 220 are radially arranged on the top surface 102, for example. In other words, the adjacent side wires 220 are not parallel to each other. In this way, a plurality of side wires 220 can be fabricated to conform to the contour of the top surface 102 , so that it can be applied to the substrate 100 having an arc-shaped contour. In some embodiments, the plurality of side wires 220 may have substantially the same extension length EL2. In this embodiment, the extension length EL2 of each side wire 220 refers to the length of each side wire 220 extending along the radial direction on the top surface 102 or the bottom surface 104 .

On the other hand, the plurality of side wires 220 may respectively have substantially the same line width W2. In this embodiment, the line width W2 of each side wire 220 refers to the width of each side wire 220 along the tangential direction of the contour of the top surface 102 . For example, in the step of FIG. 8 , when the transfer element 130 is pressed against the wire setting portion 106c of the substrate 100, since the substrate 100 rotates while moving relative to the transfer member 130, different parts of the wire setting portion 106c The contact time of the transfer element 130 is substantially the same, and correspondingly, the pressures on different parts of the anti-etching pattern P2 are also substantially the same. In this way, the transferred anti-etching patterns P2 may have substantially the same width, and the side wires 220 obtained by using them as masks have substantially the same line width W2 corresponding to the anti-etching patterns P2.

On the bottom surface 104 of the substrate 100 , the plurality of side wires 220 can be electrically connected to the corresponding connection wires 216 . In one embodiment, the connection traces 216 may be further electrically connected to at least one circuit board (eg, the circuit board 140 of FIG. 4A ). The circuit board or other external circuit structures intended to be bonded to the substrate 100 can be bonded to the lines or pads on the bottom surface 104 without being bonded to the top surface 102 . Therefore, the periphery of the top surface 102 does not need to reserve a bonding area for bonding external circuit structures. In other words, the flat-panel display device 20 can have a smaller peripheral area width, and can be applied to designs that require a very small frame width or even no frame.

Referring to FIG. 9B and FIG. 10B , a protective layer 250 is formed on the substrate 100 . So far, the fabrication of the flat display device 20 of this embodiment has been substantially completed. The protective layer 250 covers the plurality of side wires 220 , fills the undercut structure UC, and continuously covers the top surface 102 , the side surfaces 106 and the bottom surface 104 of the substrate 100 . In other words, the protective layer 250 may wrap the side wires 220 such that the side wires 220 are sealed in the protective layer 250 . For example, the protective layer 250 may adopt the same design as that of the protective layer 150 in FIG. 4B , and details are not described herein again.

FIG. 11A is a schematic perspective view of a flat-panel display device according to some embodiments; FIG. 11B is a schematic top view of a flat-panel display device according to some embodiments of the disclosure. Here, FIG. 11A and FIG. 11B are, for example, schematic diagrams of a modification of the flat-panel display device 20 of FIG. 9B . It should be noted that the embodiments of FIG. 11A and FIG. 11B use the element numbers and part of the content of the embodiment of FIG. 9B , wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

The flat display device 20' of this embodiment is different from the flat display device 20 of FIG. 9B in that the wire arrangement portion 106c of the flat display device 20' includes a first wire arrangement portion 106A and a second wire arrangement portion 106B. More specifically, the radius of curvature of the first wire setting portion 106A is larger than the radius of curvature of the second wire setting portion 106B. In this embodiment, as shown in FIG. 11B , the substrate 100 ′ of the flat display device 20 ′ is, for example, a substrate with an elliptical outline, and the first wire arrangement portion 106A refers to, for example, the side surfaces located at both ends of the short axis of the substrate 100 ′ , the second wire setting portion 106B refers to, for example, the side surfaces located at both ends of the long axis of the substrate 100 ′. In the step shown in FIG. 8 , the anti-etching patterns P2 are arranged on the transfer tool 130 at equal intervals, for example, when the anti-etching patterns P2 are attached to the edge of the substrate 100 ′, they are transferred at the first wire setting portion 106A The pitch of the anti-etching patterns P2 is greater than the pitch of the anti-etching patterns P2 transferred at the second wire arrangement portion 106B. Therefore, the pitch of the side wires 220A arranged along the first wire arrangement portion 106A is larger than the pitch of the side wires 220B arranged along the second wire arrangement portion 106B, corresponding to the transferred etching resist pattern P2. In other words, the distribution density of the plurality of side wires 220A arranged along the first wire arrangement portion 106A is smaller than the distribution density of the plurality of side wires 220B arranged along the second wire arrangement portion 106B.

To sum up, the flat display device according to the embodiment of the present invention includes side wires arranged on the edge of the substrate according to the outline of the substrate, and the side wires continuously extend from the top surface of the substrate to the bottom surface through the wire setting portions on the side surfaces. In this way, it can be applied to a flat display device having a curved display panel. In addition, the circuit structure intended to be bonded to the flat panel display device, such as a circuit board, can be bonded to the bottom surface of the flat panel display device, and the width of the peripheral area of the flat panel display device can be reduced to achieve a narrow frame design, or even a frameless design.

10, 20, 20': Flat Display Devices 100, 100': substrate 102: Top surface 104: Underside 106: Side 106A: First wire setting part 106B: Second wire setting part 106c: Lead wire setting part 110, 210: Drive circuit structure 112: Pixel pads 114: wire pads 114a, 214a, 214'a: joint surface 120, 220, 220A, 220B: side conductors 120A: Top section 120B: Bottom section 120C: Side Section 120t, 124t, 126t, 220t, 224t: end 122: Conductor material layer 124, 224: Anti-etching layer 124A: top etch resist 124B: Bottom etch resist 124C: Side etching resist 126, 226: Conductor layer 126A: Top conductor layer 126B: Bottom conductor layer 126C: side conductor layer 130: Transfer tool 132: Roller 134: Carrier 140: circuit board 150, 250: protective layer 214: first wire pad 214': 2nd wire pad 216: connect traces D1, D2: moving direction D3: Rotation direction EL1, EL2: extension length L1: Straight track L2: arc trajectory P1, P2: Anti-etching pattern Rb: column edge Rc: column center t1, t2, t3: thickness UC: Undercut Structure W1, W2: line width X, Y, Z: direction

1A to FIG. 1E are schematic top views of some steps of manufacturing a side wire of a flat display device according to some embodiments of the present invention. Figures 2A to 2E present schematic cross-sectional views along the line A-A' in Figures 1A to 1E. 3A is a three-dimensional schematic diagram of a side wire of a flat display device according to some embodiments of the present invention. Fig. 3B is a schematic cross-sectional view along the line I-I' of Fig. 3A. Fig. 3C is a schematic cross-sectional view along the line II-II' of Fig. 3A. 4A and 4B are schematic plan views showing some steps of manufacturing a flat display device according to some embodiments of the present invention. Figures 5A and 5B are schematic cross-sectional views taken along the line A-A' in Figures 4A and 4B. 6A to 6C are schematic top views of some steps of manufacturing a flat display device according to some embodiments of the present invention. Figures 7A to 7C present schematic cross-sectional views along the line A-A' in Figures 6A to 6C. FIG. 8 presents a schematic perspective view of some steps of manufacturing a flat panel display device according to some embodiments of the present invention. 9A and 9B are schematic top views of some steps of manufacturing a flat display device according to some embodiments of the present invention. Figures 10A and 10B are schematic cross-sectional views taken along the line A-A' in Figures 9A and 9B. FIG. 11A is a schematic perspective view of a flat-panel display device according to some embodiments. FIG. 11B is a schematic top view of a flat display device according to some embodiments of the disclosure.

10: Flat display device

100: Substrate

102: Top surface

104: Underside

106: Side

106c: Lead wire setting part

110: Drive circuit structure

112: Pixel pads

114: wire pads

114a: Joint surface

120: side wire

124: Anti-etching layer

126: Conductor layer

140: circuit board

150: protective layer

UC: Undercut Structure

X, Y, Z: direction

Claims (10)

A flat display device, comprising: A substrate, having opposite top and bottom surfaces, and a side surface connected between the top surface and the bottom surface, wherein the side surface has at least one wire arrangement portion and the wire arrangement portion is along the plane of the substrate arc-shaped trajectory distribution; and A plurality of side wires extend continuously from the top surface of the substrate to the bottom surface through the wire setting portion. The flat display device according to claim 1, further comprising: a plurality of wire bonding pads, disposed in a peripheral region of at least one of the top surface and the bottom surface of the substrate, each of the plurality of wire bonding pads has a bonding surface, the bonding surface and the One of the plurality of side wires is in contact. The flat display device according to claim 1, wherein the ends of the plurality of side wires are arranged in a row substantially along a straight line, The line width of the side conductors closer to the center of the column is wider, and the line width of the side conductors closer to the edge of the column is narrower. The flat display device of claim 3, wherein each of the plurality of side wires has a side segment, the side segment comprising: a side etching resist layer, disposed on the side surface of the substrate; and a side conductor layer, sandwiched between the side etching resist layer and the side surface of the substrate, the side segment closer to the edge of the column has the thicker side etch resist layer, the side segment closer to the center of the column has the thinner side etch resist layer, The side conductor layers of the side segments have substantially the same thickness. The flat display device of claim 1, wherein each of the plurality of side wires has a bent end, the ends of the plurality of side wires are bent toward the same side and all of the plurality of side wires have ends that are bent The ends are arranged substantially along an arc trajectory. The flat-panel display device of claim 1, wherein each of the plurality of side wires includes a conductor layer and an etch-resistant layer, the conductor layer is sandwiched between the etch-resistant layer and the substrate, The conductor layer is retracted relative to the etch-resistant layer so that the substrate, the conductor layer and the etch-resistant layer form an undercut structure along the periphery of the conductor layer. The flat display device according to claim 1, further comprising: At least one circuit board is disposed on the bottom surface of the substrate and is electrically connected to the plurality of side wires. The flat display device according to claim 1, wherein the wire setting part comprises a first wire setting part and a second wire setting part, and the curvature radius of the first wire setting part is larger than that of the second wire setting part radius, The arrangement pitch of the plurality of side wires in the first wire arrangement portion is greater than the arrangement pitch of the second wire arrangement portion. A method of manufacturing a flat display device, comprising: A substrate is provided, which has opposite top and bottom surfaces, and a side surface connected between the top surface and the bottom surface, wherein the side surface has at least one wire arrangement portion, and the wire arrangement portion is on the plane of the substrate arc-shaped forming a conductor material layer, the conductor material layer continuously covering the top surface of the substrate, the wire arrangement portion on the side surface, and the bottom surface; Setting the anti-etching pattern on the transfer tool; The side surface of the substrate is abutted against the transfer tool, and the substrate is rotated relative to the transfer tool to transfer the anti-etching pattern to the conductor along the wire arrangement portion on the material layer; and A portion of the conductor material layer not shielded by the etch-resistant pattern is removed to form a plurality of side wires. The method of manufacturing a flat display device according to claim 9, wherein ends of the plurality of side wires are bent along a rotation direction of the substrate.

Images