TWI736096B - 電路板 - Google Patents
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Abstract
一種電路板用以電性連接一晶片,該電路板包含一基板及一線路層,該線路層具有至少一第一線路及複數個第二線路,該些第二線路設置於該基板的一電路佈局區,該第一線路設置於該基板的一晶片設置區,該第一線路包含一主線路及至少一支流接腳,該支流接腳以一連接段連接該主線路,且該支流接腳的一延伸段及一接合段至該主線路之間具有間隙,該接合段用以接合該晶片的一凸塊,藉由該支流接腳增加該電路板接合該晶片的導接腳,且由於該接合段、該延伸段與該主線路之間具有間隙,因此一熱壓合製程中,能避免設置於該主線路上的焊料沿著該支流接腳往該凸塊方向流動,進而使該支流接腳上的焊錫溢流出該支流接腳。
Description
本發明是關於一種電路板,特別是在一晶片設置區設置有一主線路及至少一支流接腳的電路板(如可撓性電路板等)。
請參閱第1圖,習知的覆晶封裝技術是在一熱壓合製程中,將一晶片(圖未繪出)的複數個凸塊21熱壓合至一基板10的一晶片設置區11中的複數個內引腳12,然由隨著該晶片的電性功能增加,用以電性連接該些內引腳12的該晶片的該些凸塊21的數量也隨著增加,在縮小或不改變該晶片設置區的面積的條件下,相鄰的凸塊容易發生橋接短路的情形。
本發明的主要目的是在一基板的一晶片設置區設置複數個內引腳、一主線路及至少一支流接腳,該支流接腳用以接合一凸塊。
本發明之一種電路板包含一基板及一線路層,該基板具有一電路佈局區及一晶片設置區,該線路層具有至少一第一線路及複數個第二線路,各該第二線路包含一內引腳及一基線,該基線連接該內引腳,該內引腳具有一第一寬度,該基線設置於該電路佈局區,沿著一縱軸線方向該內引腳設置於該晶片設置
區,該第一線路設置於該晶片設置區,沿著該縱軸線方向,該內引腳位於該第一線路與該晶片設置區的一邊緣之間,該第一線路包含一主線路及至少一支流接腳,該主線路具有一第二寬度,該第二寬度不小於該第一寬度,該主線路沿著與該縱軸線相交的一第一軸線方向延伸,該支流接腳具有一接合段、一連接段及一延伸段,該延伸段位於該連接段與該接合段之間,該接合段用以接合一晶片的一凸塊,該連接段具有一第三寬度,該第三寬度小於該第二寬度,沿著與該縱軸線相交的一第二軸線方向,該連接段連接該主線路,且該延伸段與該主線路之間具有一第一間隙,該接合段與該主線路之間具有一第二間隙,該接合段的一自由端不與該主線路相連接。
本發明藉由設置於該晶片設置區中的該支流接腳,供該凸塊電性連接,其增加了該電路板接合該晶片的導接腳,解決了習知技術中在縮小或不改變該晶片設置區的面積的條件下,相鄰的凸塊發生橋接短路的問題。
此外,本發明藉由該連接段的該第三寬度小於該主線路的該第二寬度、該延伸段與該主線路之間的該第一間隙及該接合段、該主線路之間的該第二間隙及該接合段的該自由端不與該主線路相連接,避免在一熱壓合製程中,形成於該第一線路的焊料沿著該主線路朝向該凸塊的方向流動,導致接合該凸塊的該接合段或該延伸段周圍發生焊料過量而溢流的情形。
10:基板
11:晶片設置區
12:內引腳
21:凸塊
30:凸塊
100:電路板
110:基板
111:電路佈局區
112:晶片設置區
112a:邊緣
120:線路層
121:第一線路
121a:主線路
121b:支流接腳
121c:接合段
121d:連接段
121e:延伸段
121f:凹槽
121g:第一側邊
121h:第二側邊
121i:穿孔
121j:子線路
121k:自由端
121l:邊緣
122:第二線路
122a:內引腳
122b:基線
130:焊料層
A:第一軸線
B:第二軸線
C:縱軸線
G1:第一間隙
G2:第二間隙
G3:第三間隙
W1:第一寬度
W2:第二寬度
W3:第三寬度
W4:第四寬度
第1圖:習知的電路板的局部示意圖。
第2圖:本發明第一實施例的電路板的示意圖。
第3圖:本發明第一實施例的電路板的局部示意圖。
第4圖:第3圖的局部放大圖。
第5圖:本發明第二實施例的電路板的局部示意圖。
第6圖:第5圖的局部放大圖。
請參閱第2、3及4圖,本發明的一種電路板100的一第一實施例,該電路板100包含一基板110及一線路層120,較佳地,該電路板100另包含一焊料層130,該焊料層130覆該蓋線路層120,且該焊料層130之厚度不大於0.3μm,請參閱第2圖,該基板110具有一電路佈局區111及一晶片設置區112,該晶片設置區112用以設置一晶片(圖未繪出),且該晶片設置區112為該晶片的一凸塊設置區投影至該基板110的區域,該凸塊設置區設置有複數個凸塊30。
請參閱第2、3及4圖,該線路層120具有至少一第一線路121及複數個第二線路122,各該第二線路122包含一內引腳122a及一基線122b,該基線122b連接該內引腳122a,該基線122b設置於該電路佈局區111,沿著一縱軸線C方向,該內引腳122a設置於該晶片設置區112,該內引腳122a具有一第一寬度W1。
請參閱第2、3及4圖,該第一線路121設置於該晶片設置區112,沿著該縱軸線C方向,該些內引腳122a位於該第一線路121與該晶片設置區112的一邊緣112a之間,該第一線路121包含一主線路121a及至少一支流接腳121b,該主線路121a具有一第二寬度W2,該第二寬度W2不小於該第一寬度W1,該主線路121a沿著一與該縱軸線C相交的一第一軸線A方向延伸,該支流接腳121b連接該主線路121a,該支流接腳121b具有一接合段121c、一連接段121d及一延伸段121e,
該延伸段121e位於該連接段121d與該接合段121c之間,該焊料層130至少覆蓋該第一線路121及該些內引腳122a,該接合段121c用以接合該晶片的該凸塊30,沿著一與該縱軸線C相交的一第二軸線B方向,該連接段121d連接該主線路121a,該連接段121d具有一第三寬度W3,該第三寬度W3小於該第二寬度W2,且該延伸段121e與該主線路121a之間具有一第一間隙G1,該接合段121c與該主線路121a之間具有一第二間隙G2,且該接合段121c的一自由端121k不與該主線路121a相連接,請參閱第3及4圖,在本實施例中,該第二軸線B方向與該第一軸線A方向相同,較佳地,該延伸段121e沿著該第一軸線A方向延伸,更佳地,該接合段121c沿著該第一軸線A方向延伸,以使該晶片設置區112能設置另一第一線路121,以使該電路板100能接合更多的凸塊。
請參閱第2及3圖,藉由設置於該晶片設置區112中的該支流接腳121b,供該凸塊30電性連接,其增加了該電路板100接合該晶片的導接腳。
請參閱第3及4圖,在本實施例中,該主線路121a具有一凹槽121f,該凹槽121f凹設於該主線路121a的一邊緣121l,該凹槽121f具有一第一側邊121g及一第二側邊121h,該連接段121d連接該第一側邊121g,在本實施例中,該連接段121d、該延伸段121e及該接合段121c位於該凹槽121f中,且該接合段121c與該第二側邊121h之間具有一第三間隙G3,然而,在不同的實施例中,可依據線路設計需求,選擇性地使至少該連接段121d、該延伸段121e或該接合段121c的其中之一未位於該凹槽121f中。
請參閱第2、3及4圖,藉由該連接段121d的該第三寬度W3小於該主線路121a的該第二寬度W2、該延伸段121e與該主線路121a之間的該第一間隙G1、該接合段121c與該主線路121a之間的該第二間隙G2及該接合段121c的該自
由端121k不與該主線路121a相連接,避免在一熱壓合製程中,形成於該第一線路121的該焊料層130因受熱而沿著該主線路121a朝向該凸塊30的方向流動,導致接合該凸塊30的該接合段121c或該延伸段121e周圍發生焊料過量而溢流的情形。
請參閱第5及6圖,本發明的該電路板100的一第二實施例,其與第一實施例的差異在於該第二軸線B與該第一軸線A相交,沿著該第二軸線B方向,該連接段121d連接該主線路121a的該邊緣1211,且該延伸段121e及該接合段121c位於該主線路121a外側,在本實施例中,該主線路121a設有至少一穿孔121i,使該主線路121a形成有一位於該穿孔121i側邊的一子線路121j,該子線路121j位於該連接段121d與該穿孔121i之間,且該連接段121d連接該子線路121j,該子線路121j具有一第四寬度W4,該第四寬度W4小於該第二寬度W2。
請參閱第5及6圖,藉由該連接段121d連接線寬小於該主線路121a的該子線路121j,避免在一熱壓合製程中,形成於該主線路121a的該焊料層130因受熱而沿著該子線路121j及該支流接腳121b朝向該凸塊30的方向流動,導致接合該凸塊30的該接合段121c或該延伸段121e周圍發生焊料過量而溢流的情形。
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。
30...凸塊 110...基板
112...晶片設置區 112a...邊緣
121...第一線路 121a...主線路
121b...支流接腳 121c...接合段
121d...連接段 121e...延伸段
121f...凹槽 121l...邊緣
122a...內引腳 122b...基線
130...焊料層
Claims (10)
- 一種電路板,包含:一基板,具有一電路佈局區及一晶片設置區;以及一線路層,具有至少一第一線路及複數個第二線路,各該第二線路包含一內引腳及一基線,該基線連接該內引腳,該內引腳具有一第一寬度,該基線設置於該電路佈局區,沿著一縱軸線方向,該內引腳設置於該晶片設置區,該第一線路設置於該晶片設置區,沿著該縱軸線方向,該內引腳位於該第一線路與該晶片設置區的一邊緣之間,該第一線路包含一主線路及至少一支流接腳,該主線路具有一第二寬度,該第二寬度不小於該第一寬度,該主線路沿著與該縱軸線相交的一第一軸線方向延伸,該支流接腳具有一接合段、一連接段及一延伸段,該延伸段位於該連接段與該接合段之間,該接合段用以接合一晶片的一凸塊,該連接段具有一第三寬度,該第三寬度小於該第二寬度,沿著與該縱軸線相交的一第二軸線方向,該連接段連接該主線路,且該延伸段與該主線路之間具有一第一間隙,該接合段與該主線路之間具有一第二間隙,該接合段的一自由端不與該主線路相連接。
- 如申請專利範圍第1項所述之電路板,其中該第二軸線方向與該第一軸線方向相同。
- 如申請專利範圍第1項所述之電路板,其中該延伸段沿著該第一軸線方向延伸。
- 如申請專利範圍第3項所述之電路板,其中該接合段沿著該第一軸線方向延伸。
- 如申請專利範圍第1或3項所述之電路板,其中該主線路具有一凹 槽,該凹槽凹設於該主線路的一邊緣,該凹槽具有一第一側邊及一第二側邊,該連接段連接該第一側邊。
- 如申請專利範圍第5項所述之電路板,其中該延伸段位於該凹槽中。
- 如申請專利範圍第5項所述之電路板,其中該接合段位於該凹槽中,且該接合段與該第二側邊之間具有一第三間隙。
- 如申請專利範圍第1項所述之電路板,其中該第二軸線與該第一軸線相交,沿著該第二軸線方向,該連接段連接該主線路的一邊緣,該延伸段及該接合段位於該主線路外側。
- 如申請專利範圍第8項所述之電路板,其中該主線路具有至少一穿孔及一子線路,該子線路位於該連接段與該穿孔之間,且該連接段連接該子線路。
- 如申請專利範圍第1項所述之電路板,其另包含一焊料層,該焊料層至少覆蓋該第一線路,該焊料層之厚度不大於0.3μm。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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TW108148759A TWI736096B (zh) | 2019-12-31 | 2019-12-31 | 電路板 |
CN202010120399.2A CN113133181B (zh) | 2019-12-31 | 2020-02-26 | 电路板 |
JP2020108588A JP6989657B2 (ja) | 2019-12-31 | 2020-06-24 | 回路基板 |
KR1020200077661A KR102366204B1 (ko) | 2019-12-31 | 2020-06-25 | 회로 기판 |
US16/914,844 US10999928B1 (en) | 2019-12-31 | 2020-06-29 | Circuit board |
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TW108148759A TWI736096B (zh) | 2019-12-31 | 2019-12-31 | 電路板 |
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TW202127983A TW202127983A (zh) | 2021-07-16 |
TWI736096B true TWI736096B (zh) | 2021-08-11 |
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US (1) | US10999928B1 (zh) |
JP (1) | JP6989657B2 (zh) |
KR (1) | KR102366204B1 (zh) |
CN (1) | CN113133181B (zh) |
TW (1) | TWI736096B (zh) |
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TW201347135A (zh) * | 2012-05-03 | 2013-11-16 | Wintek Corp | 線路板 |
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JP2000150712A (ja) * | 1998-11-16 | 2000-05-30 | Toshiba Corp | 実装用配線基板および実装回路装置 |
JP3379477B2 (ja) * | 1999-05-31 | 2003-02-24 | 日本電気株式会社 | 配線基板、半導体実装装置および電子機器 |
JP3674424B2 (ja) * | 1999-11-30 | 2005-07-20 | セイコーエプソン株式会社 | 実装構造体、電気光学装置および電子機器 |
JP3536023B2 (ja) * | 2000-10-13 | 2004-06-07 | シャープ株式会社 | Cof用テープキャリアおよびこれを用いて製造されるcof構造の半導体装置 |
US7420282B2 (en) * | 2004-10-18 | 2008-09-02 | Sharp Kabushiki Kaisha | Connection structure for connecting semiconductor element and wiring board, and semiconductor device |
KR100632807B1 (ko) * | 2004-11-26 | 2006-10-16 | 삼성전자주식회사 | 반도체 칩 및 그를 포함하는 탭 패키지 |
JP4378387B2 (ja) * | 2007-02-27 | 2009-12-02 | Okiセミコンダクタ株式会社 | 半導体パッケージ及びその製造方法 |
JP4980960B2 (ja) * | 2008-03-14 | 2012-07-18 | ラピスセミコンダクタ株式会社 | テープ配線基板及び半導体チップパッケージ |
KR101692956B1 (ko) * | 2010-09-20 | 2017-01-04 | 삼성전자 주식회사 | 테이프 패키지 |
KR102252380B1 (ko) * | 2014-04-24 | 2021-05-14 | 삼성전자주식회사 | 테이프 배선 기판, 반도체 패키지 및 상기 반도체 패키지를 포함한 디스플레이 장치 |
TWI641106B (zh) * | 2016-12-15 | 2018-11-11 | 南茂科技股份有限公司 | 晶片封裝基板與晶片封裝結構 |
TWI653717B (zh) * | 2017-09-11 | 2019-03-11 | 南茂科技股份有限公司 | 薄膜覆晶封裝結構 |
JP6948302B2 (ja) * | 2017-10-16 | 2021-10-13 | シトロニックス テクノロジー コーポレーション | 回路のパッケージ構造 |
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US5537328A (en) * | 1992-01-14 | 1996-07-16 | Nec Corporation | Method for laying out power supply wiring conductors in integrated circuits |
TW410536B (en) * | 1998-11-07 | 2000-11-01 | Hyundai Electronics Ind | Printed circuit board and method for wiring signal lines on the same |
US20130166796A1 (en) * | 2010-09-09 | 2013-06-27 | Zte Corporation | Mobile terminal |
TW201347135A (zh) * | 2012-05-03 | 2013-11-16 | Wintek Corp | 線路板 |
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KR102366204B1 (ko) | 2022-02-21 |
KR20210086938A (ko) | 2021-07-09 |
CN113133181B (zh) | 2022-02-11 |
TW202127983A (zh) | 2021-07-16 |
CN113133181A (zh) | 2021-07-16 |
US10999928B1 (en) | 2021-05-04 |
JP6989657B2 (ja) | 2022-01-05 |
JP2021111772A (ja) | 2021-08-02 |
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