TWI707475B - 具有氣隙結構的射頻切換器 - Google Patents

具有氣隙結構的射頻切換器 Download PDF

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TWI707475B
TWI707475B TW106132441A TW106132441A TWI707475B TW I707475 B TWI707475 B TW I707475B TW 106132441 A TW106132441 A TW 106132441A TW 106132441 A TW106132441 A TW 106132441A TW I707475 B TWI707475 B TW I707475B
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air gap
substrate
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trenches
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安東尼Ｋ 史坦普
史蒂芬Ｍ 尚克
莫納漢 約翰Ｊ 艾立斯
希瓦Ｐ 艾杜蘇米利
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美商格芯（美國）集成電路科技有限公司
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Abstract

本揭露係關於一種半導體結構，且特定而言，係關於具有氣隙結構的射頻(RF)切換器及製造方法。該結構包括具有至少一氣隙結構之基板，該氣隙結構在至少一閘極結構下方之井區中形成，且其延伸至由該至少一閘極結構之源極/汲極區域形成之接面。

Description

具有氣隙結構的射頻切換器
本揭露係關於一種半導體結構，且特定而言，係關於具有氣隙結構的射頻(RF)切換器及製造方法。
射頻(RF)裝置用在許多不同類型的商業應用中。例如，RF裝置可用在具有無線通訊組件(例如：切換器、MOSFETs、電晶體及二極體)之行動電話中。
由於行動電話變得更加複雜與商品化，對於無線通訊組件持續地需要提供更高的性能與更低的價位。例如，製造RF切換器之成本的主要部份是工程化極高之線性度使得諧波失真極低並符合產品規格的成本。
RF裝置通常製造在高電阻率的矽晶圓或基板上以達到所需的RF線性度。現有技術中的陷阱富集絕緣體上矽(SOI)高電阻率基板提供極佳的垂直隔離性及線性度，但該SOI晶圓可佔高達50%之總製造成本，因為其等可為高電阻率非SOI基板之成本的5至10倍，即在SOI晶圓上形成之RF裝置可具有1.0之總標準化製造成本，而在高電阻率非SOI塊體晶圓上形成之類似裝置可具有六成之總標準化製造成本。已知在塊體Si基板上建構之裝置易遭受到劣化之線性度、諧波、雜訊、及洩漏電流，其等任一者將使裝置性能劣化因而迫使SOI晶圓之成本變高。
在本揭露之一態樣中，一結構包含具有至少一氣隙結構之基板，該氣隙結構在至少一閘極結構下方之井區中形成，且其延伸至由該至少一閘極結構之源極/汲極區域形成之接面。
在本揭露之一態樣中，一結構包含：具有至少一井區之基板；位於至少一井區上之至少一閘極結構；延伸至至少一井區內之複數個溝槽；以及自該等複數個溝槽延伸之至少一氣隙結構，其在該至少一閘極結構之源極/汲極區域下方及在該至少一井區中。
在本揭露之一態樣中，一方法包含：在一基板之一井區內形成複數個溝槽；以絕緣材料將該等複數個溝槽鋪襯裡；以及藉由通過該等複數個溝槽蝕刻該高電阻率基板以形成至少一氣隙結構，其自該井區內之複數個溝槽延伸。
10:結構
10’:結構
10”:結構
10''':結構
12:基板/矽晶圓
13:對準標記
14:p井區/NFET切換井/井區
15:墊介電膜/介電質/墊膜/介電層
16:淺溝槽隔離(STI)結構
16a:氧化材料/絕緣材料/氣隙溝槽
18:電晶體
18a:源極區域
18b:汲極區域
19:源極/汲極區域
20:深溝槽隔離結構
21:NFET閘極導體/n型源極/汲極區域
22:溝槽/氣隙通孔
23:間隔件
24:氣隙結構
24a:氣隙結構
24b:側壁
24c:氧化區域
25:矽化物
26:矽化物
28:障壁層/深溝槽隔離結構
30:層間介電材料
31:障壁介電層
32:接觸
34:接觸
43:多閘極間隔件
45:介電質/介電塗層
本揭露藉由本揭露之例示性實施例之非限制實例參照所述諸圖式描述在以下之實施方式中。
圖1A至圖1C顯示根據本揭露之態樣之進入結構及各別之製造過程。
圖2A至圖2F顯示根據本揭露之態樣之數個不同結構及各別之製造過程。
圖3顯示根據本揭露之態樣之除其它特徵外之圖2氣隙結構間之閘極結構及各別之製造過程。
圖4A顯示根據本揭露之態樣之除其它特徵外在一井結構中鋪襯裡之氣隙結構及各別之製造過程。
圖4B顯示根據本揭露之態樣之除其它特徵外在一井結構中合併襯裡之氣隙結構及各別之製造過程。
圖4C顯示根據本揭露之態樣之除其它特徵外在一井結構中單一襯裡之氣隙結構及各別之製造過程。
圖5顯示根據本揭露之態樣之圖1至圖4C結構之另一示意局部俯視圖。
本揭露係關於一種半導體結構，且特定而言，係關於具有氣隙結構的射頻(RF)FETs或NPNs，諸如FET切換器，該氣隙結構形成於該等切換器下方之基板中。更特定而言，本揭露係關於用在前端模組接收器中之射頻(RF)切換器，其使用具有在FET源極/汲極下方之氣隙結構之FET形成。在實施例中，該等結構除其它特徵外可進一步包括區域SOI及深溝槽隔離結構。有利地，閘極結構間之氣隙結構將改善該裝置之RF參數，諸如線性度及介入損失(insertion loss)。
在實施例中，氣隙結構可在塊體高電阻率矽晶圓中形成，例如電阻率>>1 ohm-cm或約1 Kohm-cm至約10 Kohm-cm或更高。在實施例中，該氣隙結構在該等源極/汲極區域下方延伸至閘極結構下方之一PN接面之底部形成。在進一步實施例中，該等氣隙結構可形成有具有深溝槽隔離結構之雙井堆疊，以避免空乏區穿過或進入無深溝槽隔離結構之三井結構中。在另外之實施例中，該等氣隙結構可經氧化以彼此合併；或個別之氣隙可合併成更大之氣隙。例如，接觸及接線在該氣隙結構上方形成以提供FET源極/汲極電壓偏壓及/或RF信號路徑。
本揭露之結構可使用數種不同工具以數種方式製造。但一般而言，使用該等方法及工具以形成尺寸在微米及奈米等級之結構。用來製造本揭露之結構之方法(即技術)已採用自積體電路(IC)技術。例如，該等結構建構在晶圓上且以藉由光微影製程圖案化之材料膜實現在晶圓之頂部上。尤其，結構之製造使用三個基本的建構區塊：(i)在一基板上沉積薄膜 材料，(ii)在該等膜之頂部上藉由光微影成像施加圖案化光罩，及(iii)選擇性地將該等膜蝕刻至該光罩。
圖1A顯示根據本揭露之態樣之進入結構。尤其，作為一說明性實例，該結構10包括一基板12，其可為範圍在約1 Kohm-cm至10 Kohm-cm之間之高電阻率基板。應認明，1K ohm-cm及更高之電阻率足以顯著地減少基板誘發之諧波失真及損失。然而，較高電阻率亦可高達20 Kohm-cm。在實施例中，該基板12可由任何合適之半導體材料構成，例如：Si、SiGe、SiGeC、SiC、GaAs、InAs、InP、及其它III/V或II/VI複合半導體。
再參照圖1A，一視需要選用之對準標記13經圖案化及蝕刻至該基板12內。此視需要選用之對準標記用來對準後續的微影位準。接著，將一或多個墊介電膜15沉積在該基板12上，墊介電膜15係諸如(但不限於)10nm之熱氧化物及100nm之CVD氮化物。
參照圖1B，開口或溝槽22在該墊介電膜15上圖案化，該介電質15經蝕刻，且溝槽22經蝕刻至該基板12內。該等溝槽22之寬度由微影解析度及待蝕刻深度確定。在一實施例中，該等溝槽為120nm寬及0.7微米深。
參照圖1C，藉由沉積介電質及自該底部及頂部平面特徵各向異性(anisotropic)地蝕刻該間隔件介電質13而在該等溝槽22之側壁上形成介電質作為一間隔件23。該各向異性蝕刻可使用全氟碳基化學由反應性離子蝕刻(RIE)組成，如本技術領域中已知，其自平面表面蝕刻材料，但在側壁上形成介電質且將該介電質留在側壁上。該等類型之間隔件蝕刻通常用在MOSFET多閘極上以使得離子植入物與該多閘極間隔開。
在溝槽形成後，以絕緣材料(亦稱之為襯料或間隔件23)將該等溝槽22鋪襯裡。在實施例中，該絕緣材料為任何合適介電材料之一或多者，諸如使用任何已知沉積方法(例如：化學氣相沉積(CVD)、矽基板之熱 氧化、或原子層沉積(ALD))沉積之一或多個氧化物或氮化物層。該間隔件23必須強固地塗布該等溝槽22之側壁。為達到此強固之側壁覆蓋，該間隔件膜必須夠厚以將厚膜留在該等溝槽22之側壁上，但不能太厚使得其夾掉(pinch off)該等溝槽22之頂部開口，其將防止該間隔件23形成。在實施例中，該等溝槽22為100nm寬，及沉積40nm之氮化物，且該間隔件23經各向異性地蝕刻。在另一實施例中，該等溝槽22之側壁經熱氧化以形成SiO2層，其在該墊膜15下方延伸。在此熱氧化後，在形成該間隔件23之前，以各向異性蝕刻形成該間隔件23或使用CVD/ALD-型沉積來沉積例如氧化物或氮化物之一或多個膜。
在使用矽基板之實施例中，在圖2A中之氣隙結構24通過該等溝槽22之底部藉由矽蝕刻製程形成。在實施例中，亦可使用用來自矽移除薄或天然介電質或殘餘間隔件蝕刻聚合物之視需要選用之氣相或液相HF處理、氫電漿、退火、鹼性或酸性化學清潔、或任何已知製程來移除在該等溝槽22之底部處之任何過量介電質。該等後間隔件蝕刻清潔應在該溝槽22之頂部及側壁上留下強固之介電襯裡以避免後續矽蝕刻蝕刻該溝槽22之側壁上或該矽晶圓12之頂部上之矽。在該間隔件形成及視需要選用之清潔之後，可移除該溝槽22之底部處在該基板12中之暴露基板材料以形成一氣隙結構24。在實施例中，可藉由濕式蝕刻製程或乾式蝕刻製程移除在該基板12中之該暴露基板材料。例如，乾式蝕刻劑可包括電漿基CF4、電漿基SF6、或氣態XeF4矽蝕刻等，且濕式蝕刻製程可包括KOH及NH4OH。在實施例中，該氣隙結構24形成在將為FET源極/汲極區域者下方，其延伸至閘極結構下方及其間之一PN接面之底部。例如，氣隙結構24之上表面深度可為約300nm；而本文亦考量其它尺寸。
為避免蝕刻不在該等溝槽22之底部處的矽基板，重要的是介電層15及間隔件23作為介電層完全地覆蓋該矽以避免不預期之矽蝕刻。圖2A及圖2B顯示氣隙結構24形成使得氣隙延伸至該溝槽22之底部 之上，且該間隔件23暴露。圖2A及圖2B顯示該暴露之間隔件23，其等在暴露時未改變其形狀。該暴露間隔件23可由於其殘留之應力而捲曲。
圖2B顯示另一實施例，其中該氣隙結構24在該等溝槽22下方形成且不延伸至該溝槽22之底部之上。在此情況中，該間隔件膜23未經底切(undercut)。
圖2B’顯示另一實施例，其中該氣隙結構24以一各向異性蝕刻形成，其使用例如通過該溝槽22之垂直定向離子撞擊之SF6-基蝕刻。作為該氣隙底部之此離子撞擊使得該氣隙結構24之頂部較不呈圓形，其可改善其通過該FET源極/汲極接面之後續延伸。該間隔件可在該氣隙結構24頂部處停止，如圖2B中所示，或延伸至該氣隙內，如圖2A所示。
圖2C顯示除其它特徵外之填充有介電質(諸如氧化物、或介電襯裡及多晶矽)之深溝槽結構20及對準該等溝槽22之氣隙結構24。該等溝槽經蝕刻夠深至高電阻率基板內，以延伸超過該pn接面之最大空乏深度。由於深溝槽結構20延伸超過最大接面空乏深度，其等避免在該矽中之相鄰摻雜井彼此短路。特定而言，如圖2C中所示，在基板12中形成深溝槽隔離結構20。該等深溝槽隔離結構20經蝕刻數十個微米至該基板內且填充有介電質(諸如氧化物、或介電襯裡及多晶矽)，其使用化學機械研磨以將過量材料自該表面移除或使用本技術領域中已知之其它方法。在實施例中，該(矽晶圓)基板12具有3000 ohm-cm之電阻率且該溝槽隔離20經蝕刻70微米深，以避免空乏穿透。
例如，在實施例中，該深溝槽隔離結構20將圍繞電晶體18(例如，參見圖5中所示之俯視圖)。該深溝槽隔離結構20將該植入井區(未示出)與相鄰井區(例如：在n井及p井區中之FET源極/汲極接面)、或三井接面區域隔離，且亦將良好避免基板空乏區合併因而減少諧波。因此，藉由提供深溝槽隔離結構20，可在高電阻率塊體基板上減少諧波、改善洩漏電流、及減少雜訊。
圖2D顯示其中該等深溝槽隔離結構20圍繞該FET及具有觸碰該等深溝槽20在一FET下方合併之氣隙結構24(參見例如圖3)的情形。在此實施例中，該等深溝槽20對該氣隙結構24提供機械支撐且該氣隙上之電晶體以完全延伸至隔離結構20之邊緣之氣隙與該基板12完全地隔離。
在圖2E中，在該基板12中形成淺溝槽隔離(STI)結構16。在實施例中，作為一實例，該等STI結構16可由氧化物材料構成，且可使用習知微影、蝕刻及沉積步驟，接著化學機械研磨(CMP)步驟形成。在實施例中，該等STI結構16可在形成電晶體之前形成，且可具有約0.3μm之深度；但本文亦考量其它深度。在進一步實施例中，該深溝槽隔離結構20可在該STI結構20之前或之後、該FET's之前或之後、及較佳地超過該p井區14之深度形成。在實施例中，該STI結構16可延伸至該等深溝槽隔離結構20之兩側上、一側上或不延伸至其側上。
在沉積用於STI結構16或深溝槽隔離結構20之氧化物或其它絕緣材料期間，氧化材料(或其它絕緣材料)16a將覆蓋或塞住該等溝槽22之頂部，例如：封閉該等氣隙結構24，以避免水份在後續製程期間進入該等氣隙結構24。
在圖2E中之氣隙結構24顯示其頂區域22填充且該氣隙結構24之側壁以介電質45部份塗布在其等表面上。介電塗層45可由一或多個熱氧化或CVD氧化物沉積組成，其與用來填充該淺溝槽隔離溝槽16者分開或與其等相同；或可與該淺溝槽隔離16氧化物填充分開地形成。
如圖2F進一步所示，深溝槽20之深度在該p井區14之下，且更特定而言，可為30μm或更大，例如，約20μm至約100μm，使得自基板中之井的空乏區保持在由該深溝槽隔離圍繞之區域內。在進一步實施例中，該深溝槽隔離結構20可經形成為該基板12之一背側研磨介面以將相鄰井區及RF裝置與DC基板電流完全地隔離。該深溝槽之直徑或寬度可 係約1μm；但本案易可採用其它尺寸，視技術節點或其他其它考量而定。
圖2F顯示多指NFET切換器。若顯示PFET切換器，則該井與源極/汲極摻雜極性將交換，如本技術領域中所知。圖中顯示該NFET切換井14與源極/汲極區域19、NFET閘極導體21、視需要選用之多閘極間隔件43、及矽化物25。該源極/汲極區域19可含有該電晶體p型暈圈(halo)、n型延伸植入物、及n型源極/汲極植入物，如本技術領域中所知。該n型源極/汲極區域21截住該氣隙結構24，使得該電晶體之n型源極/汲極與p型p井間之pn接面區域減少。此源極/汲極接面區域之減少將減少該接面電容。由於該接面電容與電壓不呈線性，此減少將改善該電晶體線性度。
在實施例中，該電晶體18可以是主動RF裝置，例如RF切換器，或其它主動或被動裝置，其提供有與該基板偏壓不同之偏壓。該電晶體18可在該基板頂部上形成，例如，基板材料(Si)保持在該等電晶體18(例如：FET閘極)下方。該等電晶體18可在交替之源極/汲極/源極/汲極/...等組態之陣列中使用多閘極形成，如本技術領域中所示。在實施例中，多指(例如：平行接線之電晶體閘極18)間之間隙可為約600nm；但亦可使用尺寸，取決於該技術節點。另外，可放置多堆疊之多指電晶體，如本技術領域中所知。該等電晶體可具有在圖5所示之深溝槽隔離20之環內形成之本體接觸，其使用任何標準裝置佈局形成，如本技術領域中所知。
所屬技術領域中具有通常知識者亦應了解，可藉由包括習知之CMOS製程形成該等電晶體18：沉積閘極介電質(例如：高k介電質，諸如氧化鉿等)，接著閘極金屬(例如：不同工作函數之金屬)，使用微影及蝕刻圖案化該等材料(例如：反應性離子蝕刻(RIE)以形成該等閘極堆疊，接著側壁形成，例如在該等閘極堆疊上沉積之氧化物或氮化物材料)。使用習知摻雜劑或離子植入製程(因此不需另外說明)將源極區域18a及汲極區域18b形成於該基板12(井區14)內或該井區14上方之基板12上(例如：用於 抬升式源極及汲極區域)。在實施例中，可使用磊晶生長製程形成抬升式源極及汲極區域。如所示，在源極/汲極區域中形成該等氣隙結構24，其延伸至在該等電晶體18下方之一PN接面之底部，例如：觸碰該等源極區域18a/汲極區域18b。
如圖2F所示，在該等源極區域18a及汲極區域18b上及在該氣隙結構24上方形成矽化物25。在實施例中，該矽化物製程以薄過渡金屬層(例如：鎳、鈷或鈦)在完全形成及圖案化之半導體裝置(例如：摻雜或離子撞擊之源極區域18a及汲極區域18b及各別之裝置18)上方之沉積開始。在沉積該材料之後，加熱該結構使得該過渡金屬與在該半導體裝置之主動區(例如：源極、汲極、閘極接觸區域)中之暴露矽(或如本文所述之其它半導體材料)反應，形成一低電阻率過渡金屬矽化物。在反應後，藉由化學蝕刻移除任何餘留之過渡金屬，在該裝置(例如圖3所示之電晶體18)之主動區域中留下矽化物接觸26。矽化物25顯示架橋跨過氧化物密封氣隙溝槽16a，但亦可不架橋跨過此氧化物填充間隙(未示出)。在任一情況中，後續形成之接觸32將觸碰此矽化區域25以與該FET之源極/汲極接觸。
在圖3中，可在該裝置(例如：電晶體18)之主動區域中之矽化物26上方形成一障壁介電層31。該障壁層28可係使用一習知沉積製程(例如：CVD製程)沉積之一障壁氮化物膜。一視需要選用之障壁介電質31及一層間介電材料30在該結構之暴露表面上方形成，例如在該等電晶體18及障壁層28上方。該視需要選用之障壁介電層可係SiN、SiCN等，如本技術領域中所知。該層間介電材料30可係氧化材料，諸如：SiO2、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、SiCOH等等，其使用任何習知沉積製程(例如：CVD)沉積。使用習知之金屬或金屬合金製程之微影、蝕刻及沉積在該層間介電材料30內形成接觸32。若該矽化物25未架橋跨過氧化物16a，則該等接觸32具有大於該等溝槽22之寬度且將與該矽化物26直接電接觸。再次使用習知CMOS沉積及圖案化製程形成該等襯裡結構34之接線層及其它 後端以與該等接觸32接觸。
圖4A、圖4B及圖4C顯示根據本揭露之額外態樣之額外結構及各別製造製程。更特定而言，除了具有絕緣(例如氧化)側壁24b之氣隙結構24外，圖4A所示之結構10'包括圖1所述之結構及材料。如圖4B所示，在結構10"中，該氧化側壁24b與相鄰氣隙結構24合併在一起，如由元件符號24c所示，其包括觸碰該深溝槽氧化物隔離20或與其合併。氣隙結構24與氧化區域24c之組合提供該FET與該基板之隔離。有效地，該隔離FET類似於在一SOI基板上形成之FET，其亦與該基板隔離。
如圖4C所示，在該結構10'''中，具經絕緣(例如氧化)側壁24b之單一氣隙結構24a經顯示在該p井14中之該等電晶體18下方形成。該等側壁可使用任何習知熱氧化製程氧化。及，如所屬技術領域中具有通常知識者應了解，所有此等結構可為三井堆疊之代表，其消除了深溝槽隔離結構之需要。
應知圖1A至圖4C之結構可係含有複數個閘極結構(電晶體)18之多堆疊FET，其形成如本技術領域中所知之平行對準之多指FET，例如：RF切換器或其它FET。在該等複數個電晶體18間提供源極區域18a及汲極區域18b。應進一步了解圖1A-圖4C所示之多個佈局可提供有一深溝槽隔離結構28，其等在分離該等電晶體堆疊之複數個電晶體18之上方與下方間共用。
圖5顯示根據本揭露之態樣之圖4A與類似圖式之結構之另一示意局部俯視圖。如圖5所示，該等氣隙結構24可沿著該結構之Y方向合併在一起。尤其，圖5顯示平行於該FET閘極垂直地合併之該等氣隙。藉由平行於該FET閘極垂直地合併該等氣隙，實質上減少該源極/汲極接面區域。因此，沿縱向翼片方向之連續氣隙結構(例如：平行於該等FET閘極)可藉由本文描述之製程形成。如此局部視圖進一步所示，絕緣材料16a將塞住該等溝槽或氣隙通孔22。接觸32、接觸34亦延伸至該基板12以偏壓 所示之基板，在此情形中，其未與該等氣隙溝槽16a相交。對於圖2D所示之合併氣隙，該氣隙在圖5中沿x方向與y方向沿伸，兩種狀況皆延伸至該等深溝槽隔離20。在此情況中，該等深溝槽隔離20將提供機械支撐以撐起釋出之矽及FET。
在此實施例中，該等接觸32、接觸34交錯以不與該等氣隙通孔22重合。或者，若該等接觸具有較該等氣隙通孔22大之寬度或直徑以允許電流流入該FET源極/汲極，則該等接觸32、接觸34可部份或全部與該等氣隙通孔22重合。在實施例中(未示出)，該等接觸32、接觸34可設計成條狀而非孔洞；且該等氣隙通孔22可由條狀而非孔洞形成。
上述之方法用在積體電路晶片之製造。所得積體電路晶片可以原晶圓形式(即，作為一單一晶圓，其具有多個未封裝晶片)、作為一裸晶粒、或以封裝形式由製造者分配。在後者情況下，該晶片係安裝在一單一晶片封裝中(諸如一塑膠載體，具有固定在母板或其它較高級載體之導線)或在一多晶片封裝中(諸如一陶瓷載體，其具有表面互連或埋入互連之任一者或兩者)。接著在任何情況下，該晶片與其它晶片、離散電路元件、及/或其它信號處理裝置整合為(a)一中間產品，諸如母板，或(b)一最終產品任一者之部分。該最終產品可係任何產品，其包括積體電路晶片，範圍自玩具及其它低端應用至具有顯示器、鍵盤或其它輸入裝置之先進電腦產品，以及一中央處理器。
本揭露之各種實施例之描述已針對說明之目的而呈現，但未意欲詳盡或限制所揭示之實施例。在不背離本揭示實施例之範疇與精神下之許多修正及變化對於所屬技術領域中具有通常知識者為顯而易見的。本文所用術語經選擇以最佳地解釋該等實施例之原理、實施應用或優於市場上所見之技術的技術改善，或可使其他所屬技術領域中具有通常知識者了解本文揭示之實施例。
12:基板/矽晶圓
15:墊介電膜
22:溝槽
23:間隔件膜
24:氣隙結構

Claims (14)

  1. 一種半導體結構，其包含具有一基板，該基板上有從該基板之一表面延伸至至少一氣隙結構之至少一溝槽結構，該至少一氣隙結構在至少一閘極結構下方該基板之井區中形成，且該至少一氣隙結構在該基板中延伸至由該至少一閘極結構在該基板中之源極/汲極區域所形成之接面；其中該至少一溝槽結構被絕緣材料覆蓋，而該絕緣材料封閉該至少一氣隙結構，以避免水份進入該至少一氣隙結構；其中該至少一氣隙結構提供在相鄰閘極結構之間。
  2. 如申請專利範圍第1項之半導體結構，其中該至少一氣隙結構以該絕緣材料鋪襯裡並塞住。
  3. 如申請專利範圍第2項之半導體結構，其中該絕緣材料為氧化材料，其合併至少一氣隙結構之複數個氣隙結構。
  4. 如申請專利範圍第1項之半導體結構，其中該至少一氣隙結構為具有氧化側壁之單一氣隙，且自該井區中多個溝槽延伸。
  5. 如申請專利範圍第1項之半導體結構，其中該基板包括具有與該等閘極結構相鄰之深溝槽隔離結構之雙井堆疊，且其延伸至底部背側研磨介面。
  6. 如申請專利範圍第1項之半導體結構，其中該深溝槽隔離結構延伸至低於該井區。
  7. 一種半導體結構，其包含：一基板，其具有至少一井區；至少一閘極結構，係位在該至少一井區上；複數個溝槽，從該至少一井區之一表面延伸至該至少一井區內；至少一氣隙結構，係位於該基板之該至少一井區之中且自該等複數個溝槽延伸，該至少一氣隙結構在該至少一閘極結構之源極/汲極區域下方且在該至少一井區中；其中該至少一氣隙結構提供在相鄰閘極結構之間。
  8. 如申請專利範圍第7項之半導體結構，其中該複數個溝槽及該至少一氣隙結構係以該絕緣材料鋪襯裡。
  9. 如申請專利範圍第8項之半導體結構，其中將該至少一氣隙鋪襯裡之該絕緣材料係一氧化材料。
  10. 如申請專利範圍第9項之半導體結構，其中該氧化材料合併該至少一氣隙結構之複數個氣隙結構。
  11. 如申請專利範圍第9項之半導體結構，其中該至少一氣隙結構為在多個閘極結構下方之單一氣隙，其自多個溝槽延伸。
  12. 如申請專利範圍第7項之半導體結構，進一步包含深溝槽隔離結構，其圍繞一底部背側研磨介面之延伸且約在該至少一井區周圍。
  13. 如申請專利範圍第7項之半導體結構，其中該基板包括具有 圍繞該至少一閘極結構之深溝槽隔離結構之雙井堆疊。
  14. 如申請專利範圍第7項之半導體結構，其中該深溝槽隔離結構延伸至低於該至少一井區。
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