TWI671812B - 半導體晶片之製造方法、半導體晶片及半導體裝置 - Google Patents
半導體晶片之製造方法、半導體晶片及半導體裝置 Download PDFInfo
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- TWI671812B TWI671812B TW103138234A TW103138234A TWI671812B TW I671812 B TWI671812 B TW I671812B TW 103138234 A TW103138234 A TW 103138234A TW 103138234 A TW103138234 A TW 103138234A TW I671812 B TWI671812 B TW I671812B
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- Prior art keywords
- wafer
- semiconductor
- etching
- semiconductor substrate
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Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Dicing (AREA)
- Weting (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013235470 | 2013-11-13 | ||
| JP2013-235470 | 2013-11-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201528363A TW201528363A (zh) | 2015-07-16 |
| TWI671812B true TWI671812B (zh) | 2019-09-11 |
Family
ID=53216461
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103138234A TWI671812B (zh) | 2013-11-13 | 2014-11-04 | 半導體晶片之製造方法、半導體晶片及半導體裝置 |
| TW105114218A TWI671813B (zh) | 2013-11-13 | 2014-11-04 | 半導體晶片之製造方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105114218A TWI671813B (zh) | 2013-11-13 | 2014-11-04 | 半導體晶片之製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6462747B2 (ko) |
| KR (3) | KR101695066B1 (ko) |
| CN (1) | CN104637877B (ko) |
| TW (2) | TWI671812B (ko) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6081647B1 (ja) * | 2016-07-28 | 2017-02-15 | 株式会社東芝 | エッチング方法、半導体チップの製造方法及び物品の製造方法 |
| JP6899252B2 (ja) * | 2017-05-10 | 2021-07-07 | 株式会社ディスコ | 加工方法 |
| US10586751B2 (en) * | 2017-08-03 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
| JP2019140225A (ja) * | 2018-02-09 | 2019-08-22 | 株式会社東芝 | エッチング方法、半導体チップの製造方法及び物品の製造方法 |
| JP7080781B2 (ja) | 2018-09-26 | 2022-06-06 | 株式会社東芝 | 多孔質層の形成方法、エッチング方法、物品の製造方法、半導体装置の製造方法、及びめっき液 |
| JP7314001B2 (ja) * | 2019-09-20 | 2023-07-25 | 株式会社東芝 | コンデンサ |
| JP7282710B2 (ja) * | 2020-03-19 | 2023-05-29 | 株式会社東芝 | 半導体装置の製造方法 |
| CN113809509B (zh) * | 2020-06-11 | 2023-07-18 | 华为技术有限公司 | 一种天线成型方法、盖板组件及终端设备 |
| JP2022044894A (ja) * | 2020-09-08 | 2022-03-18 | ソニーセミコンダクタソリューションズ株式会社 | 半導体チップ、製造方法 |
| US11574861B2 (en) | 2021-03-25 | 2023-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201126648A (en) * | 2010-01-18 | 2011-08-01 | Semiconductor Components Ind | Semiconductor die singulation method |
| TW201216347A (en) * | 2010-10-08 | 2012-04-16 | Wakom Semiconductor Corp | Method for forming a micro-pores structure or a trench structure on a silicon-chip substrate surface |
| TW201306301A (zh) * | 2011-07-25 | 2013-02-01 | Samsung Electronics Co Ltd | 製造半導體發光二極體的方法 |
| CN103227259A (zh) * | 2012-01-31 | 2013-07-31 | 丰田合成株式会社 | 半导体发光元件、半导体发光元件的制造方法和发光装置 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3904496B2 (ja) * | 2002-09-06 | 2007-04-11 | 株式会社リコー | 半導体装置の製造方法 |
| JP4495916B2 (ja) * | 2003-03-31 | 2010-07-07 | 富士通マイクロエレクトロニクス株式会社 | 半導体チップの製造方法 |
| JP2005311321A (ja) * | 2004-03-22 | 2005-11-04 | Sharp Corp | 半導体装置およびその製造方法、並びに、該半導体装置を備えた液晶モジュールおよび半導体モジュール |
| TW200620451A (en) * | 2004-11-09 | 2006-06-16 | Univ Osaka | Method for forming hole in crystal substrate, and crystal substrate having hole formed by the method |
| JP4546483B2 (ja) * | 2005-01-24 | 2010-09-15 | パナソニック株式会社 | 半導体チップの製造方法 |
| JP2007194469A (ja) * | 2006-01-20 | 2007-08-02 | Renesas Technology Corp | 半導体装置の製造方法 |
| CN100477162C (zh) * | 2006-02-21 | 2009-04-08 | 探微科技股份有限公司 | 切割晶片的方法 |
| KR100772016B1 (ko) * | 2006-07-12 | 2007-10-31 | 삼성전자주식회사 | 반도체 칩 및 그 형성 방법 |
| JP4488037B2 (ja) * | 2007-07-24 | 2010-06-23 | パナソニック株式会社 | 半導体ウェハの処理方法 |
| WO2010042209A1 (en) * | 2008-10-09 | 2010-04-15 | Bandgap Engineering, Inc. | Process for structuring silicon |
| US8278191B2 (en) * | 2009-03-31 | 2012-10-02 | Georgia Tech Research Corporation | Methods and systems for metal-assisted chemical etching of substrates |
| JP5322173B2 (ja) * | 2009-09-07 | 2013-10-23 | 国立大学法人 宮崎大学 | 微細流路の形成方法 |
| US8802545B2 (en) * | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
-
2014
- 2014-11-04 TW TW103138234A patent/TWI671812B/zh active
- 2014-11-04 TW TW105114218A patent/TWI671813B/zh active
- 2014-11-10 KR KR1020140155382A patent/KR101695066B1/ko active IP Right Grant
- 2014-11-13 CN CN201410640037.0A patent/CN104637877B/zh active Active
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2016
- 2016-12-13 KR KR1020160169443A patent/KR20160148491A/ko not_active Application Discontinuation
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2017
- 2017-03-16 JP JP2017050977A patent/JP6462747B2/ja active Active
- 2017-10-27 KR KR1020170141100A patent/KR20170123598A/ko active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201126648A (en) * | 2010-01-18 | 2011-08-01 | Semiconductor Components Ind | Semiconductor die singulation method |
| TW201216347A (en) * | 2010-10-08 | 2012-04-16 | Wakom Semiconductor Corp | Method for forming a micro-pores structure or a trench structure on a silicon-chip substrate surface |
| TW201306301A (zh) * | 2011-07-25 | 2013-02-01 | Samsung Electronics Co Ltd | 製造半導體發光二極體的方法 |
| CN103227259A (zh) * | 2012-01-31 | 2013-07-31 | 丰田合成株式会社 | 半导体发光元件、半导体发光元件的制造方法和发光装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20160148491A (ko) | 2016-12-26 |
| CN104637877A (zh) | 2015-05-20 |
| KR20170123598A (ko) | 2017-11-08 |
| JP2017118145A (ja) | 2017-06-29 |
| TWI671813B (zh) | 2019-09-11 |
| JP6462747B2 (ja) | 2019-01-30 |
| TW201528363A (zh) | 2015-07-16 |
| KR20150055567A (ko) | 2015-05-21 |
| TW201631648A (zh) | 2016-09-01 |
| CN104637877B (zh) | 2018-04-06 |
| KR101695066B1 (ko) | 2017-01-10 |
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