TWI647753B - 半導體元件之製造方法及半導體元件 - Google Patents

半導體元件之製造方法及半導體元件 Download PDF

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TWI647753B
TWI647753B TW103138097A TW103138097A TWI647753B TW I647753 B TWI647753 B TW I647753B TW 103138097 A TW103138097 A TW 103138097A TW 103138097 A TW103138097 A TW 103138097A TW I647753 B TWI647753 B TW I647753B
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semiconductor wafer
semiconductor
cutting
manufacturing
dicing
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TW103138097A
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TW201523721A (zh
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松浦文章
佐藤知稔
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日商夏普股份有限公司
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Ceramic Engineering (AREA)
  • Dicing (AREA)

Abstract

本發明之半導體元件之製造方法包含：半導體元件形成步驟，其形成包含介電質膜之半導體元件；切割區域形成步驟，其去除區劃半導體元件之區劃區域中的介電質膜而形成切割區域；及切割步驟，其將切割區域進行切割。

Description

半導體元件之製造方法及半導體元件
本發明係關於半導體元件之製造方法及半導體元件。
近年來，盛行開發具有高耐壓特性，且用於流通大電流之用於之電源裝置。於此種電源裝置之開發中，具有較高之絕緣破壞電場及較高之飽和電子速度之材料即氮化物半導體備受矚目。其中亦期待使用GaN(氮化鎵)系半導體之電源裝置係如非專利文獻1及非專利文獻2所揭示，對將來之低損失、高速電源開關系統之節能化做出巨大貢獻。
然而，在GaN電源裝置之製造中，若於矽製半導體晶圓之切斷時進行通常所使用之刀片切割，則因GaN膜較硬，故無法順利切斷半導體晶圓。又，因矽基板與GaN膜之晶格常數或熱膨脹係數不同，故於半導體晶圓，矽系基板與GaN膜之界面附近產生有較大之應力。若於該狀態下，切割之機械性衝擊施加於上述界面附近，則存在產生以上述界面附近為起點之龜裂等之問題。因此，在GaN電源裝置之製造中，大多使用雷射切割。
[先前技術文獻] [專利文獻]
[專利文獻1]日本公開專利公報「日本特開2005-12206號(2005年1 月13日公開)」
[非專利文獻]
[非專利文獻1]上田哲三「GaN現状応用」、KEC資訊、2013年1月、NO.224、p.35-38
[非專利文獻2]生方映徳、外5名「Si基板上向 MOCVD装置開発」、大陽日酸技報、2011年、No.30、p.23-28
然而，雷射切割存在因會產生碎片(蒸發物殘渣)而必須去除該碎片、或因切斷需要時間而使切割之成本變高之問題點。再者，存在因雷射切割，晶片側面導通而形成洩漏通道之問題。
為解決上述雷射切割中之問題，有藉由蝕刻去除GaN膜後進行切割之方法。例如，專利文獻1中揭示有在分斷半導體晶圓前，於包含氮化物系半導體之積層體形成電極用凹部及區劃槽之氮化物系半導體元件之製造方法。一般而言，因GaN為化學性非常穩定之物質，故GaN膜不會溶解於一般之酸(鹽酸、硫酸、硝酸等)或鹼，且於室溫下不會被任何溶液蝕刻。因此，於上述專利文獻1中，作為GaN膜之蝕刻，較佳為使用利用反應性離子蝕刻進行之乾蝕刻。
然而，乾蝕刻存在因蝕刻速度較慢而生產率降低之問題。
本發明係為解決上述問題點而完成者，其目的在於提供一種減少切割時產生於基板與GaN系半導體膜之界面附近之龜裂之GaN系半導體元件之製造方法。
為解決上述問題，本發明之一態樣之半導體元件之製造方法其特徵在於包含：半導體元件形成步驟，其係藉由於形成於基板上之GaN系半導體膜上形成介電質膜，而形成複數個半導體元件；切割區 域形成步驟，其係藉由去除區劃上述複數個半導體元件之區劃區域中的上述介電質膜而形成槽形狀之切割區域；及切割步驟，其係藉由切割上述切割區域，而切出上述複數個半導體元件。
又，本發明之一態樣之半導體元件其特徵在於：其係自半導體晶圓切出者，該半導體晶圓具有形成於基板上之GaN系半導體膜、與形成於上述GaN系半導體膜上之介電質膜，且上述半導體元件係藉由對已去除上述介電質膜之切割區域進行切割，而自上述半導體晶圓切出。
根據本發明之一態樣，可發揮提供一種減少切割時產生於基板與GaN系半導體膜之界面附近之龜裂的GaN系半導體元件之製造方法之效果。
1‧‧‧矽系基板(基板)
2‧‧‧GaN系半導體膜
3‧‧‧介電質膜
4‧‧‧密封環
5‧‧‧保護膜
6‧‧‧槽
6a‧‧‧槽
6b‧‧‧端部
7‧‧‧單軸切割區域
8‧‧‧2軸切割區域
9‧‧‧區劃區域
10‧‧‧元件區域(半導體元件)
11‧‧‧切割區域
20‧‧‧表面崩缺
21‧‧‧層間龜裂
100‧‧‧半導體裝置
101‧‧‧半導體晶圓
102‧‧‧表面保護膠帶
103a‧‧‧膠帶輥
103b‧‧‧膠帶輥
104‧‧‧磨石
105‧‧‧研磨滾輪
106‧‧‧研磨載台
107‧‧‧切割膠帶
108‧‧‧晶圓環
109‧‧‧剝離膠帶
110‧‧‧切割刀片
111‧‧‧半導體晶片(半導體元件)
112‧‧‧島狀物
113‧‧‧漿料
114‧‧‧夾頭
115‧‧‧接合焊墊
116‧‧‧引線
117‧‧‧導線
118‧‧‧鑄模模具
119‧‧‧鑄模樹脂
120‧‧‧活塞
121‧‧‧封裝
圖1係用以說明本發明之實施形態1之半導體晶片之製造方法之圖，(a)係放大顯示半導體晶圓之一部分之俯視圖，(b)係半導體晶片之各製造步驟中(a)所示之半導體晶圓之A-A線箭頭向視剖面圖。
圖2係本發明之實施形態1之半導體裝置之剖面圖。
圖3係用以說明本發明之實施形態1之半導體裝置之製造方法之各製造步驟之示意圖。
圖4(a)係顯示本發明之實施形態1之半導體晶圓之整體之俯視圖，(b)係放大顯示(a)所示之半導體晶圓之一部分之俯視圖，(c)係(b)所示之半導體晶圓之B-B線箭頭向視剖面圖。
圖5係顯示先前之半導體晶片之製造方法中切割後之半導體晶圓之表面狀態之圖。
圖6係顯示先前之半導體晶片之製造方法中切割後之半導體晶圓之剖面狀態之圖。
圖7係顯示實施形態1之半導體晶片之製造方法中切割後之半導體晶圓之表面狀態之圖。
圖8係顯示關於切割後之半導體晶圓中表面崩缺及層間龜裂之產生量，比較實施形態1之半導體晶片之製造方法與先前之半導體晶片之製造方法之圖表。
圖9係用以說明本發明之實施形態2之半導體晶片之製造方法之圖，(a)係放大顯示半導體晶圓之一部分之俯視圖，(b)係半導體晶片之各製造步驟中(a)所示之半導體晶圓之C-C線箭頭向視剖面圖。
圖10係顯示實施形態2之半導體晶片之製造方法中切割後之半導體晶圓之表面狀態之圖。
圖11係顯示利用實施形態2之半導體晶片之製造方法切割後之半導體晶圓之狀態之剖面圖。
圖12係顯示關於切割後之半導體晶圓中表面崩缺及層間龜裂之產生量，比較實施形態1之半導體晶片之製造方法與實施形態2之半導體晶片之製造方法之圖表。
以下，對本發明之實施形態進行說明。
〔實施形態1〕
關於本發明之實施形態1之半導體晶片111之製造方法，基於圖1至圖8進行說明。
(半導體裝置100之構成)
首先，對具備半導體晶片111之半導體裝置100之構成進行說明。圖2係本實施形態之半導體裝置100之剖面圖。半導體裝置100係如圖2所示，具備半導體晶片111(半導體元件)、島狀物112、漿料113、接合焊墊115、引線116、導線117、及封裝121。
半導體晶片111係介隔漿料113搭載於島狀物112。又，半導體晶 片111與引線116係藉由接合焊墊115及導線117而彼此電性連接。
島狀物112係介隔漿料113搭載有半導體晶片111。
漿料113係為了於島狀物112上搭載半導體晶片111，而使半導體晶片111與島狀物112接著。
接合焊墊115係用於與引線116或其他半導體晶片之電性連接之電極，且設置於半導體晶片111之上端面。
引線116係用於與外部之電性連接之端子。引線116之封裝121外之部分係與供安裝半導體裝置100之配線基板等連接，引線116之封裝121內之部分係與導線117電性連接。
導線117係使半導體晶片111與引線116彼此電性連接之連接配線。導線117之一端連接於接合焊墊115，導線117之另一端連接於引線116之上端面。
封裝121係被覆半導體晶片111、島狀物112、漿料113、接合焊墊115、導線117、及引線116之一部分之密封構件。
此處，半導體晶片111係自半導體晶圓101(參照圖4)切出元件區域10者。詳細內容予以後述。
(半導體裝置100之製造方法之概要)
關於本實施形態之半導體裝置100之製造方法之概要，基於圖3說明各步驟之內容。
本實施形態之半導體裝置100之製造方法係如圖3所示，包含有半導體晶圓製造步驟(步驟1)、表面保護膠帶貼附步驟(步驟2)、背面研磨步驟(步驟3)、切割膠帶貼附步驟(步驟4)、表面保護膠帶剝離步驟(步驟5)、切割步驟(步驟6)、晶片接合步驟(步驟7)、打線接合步驟(步驟8)、樹脂鑄模步驟(步驟9)、外裝鍍敷步驟(步驟10)、標記步驟(步驟11)、成形加工步驟(步驟12)、測試步驟(步驟13)、外觀檢查步驟(步驟14)、及包裝步驟(步驟15)。
於步驟1之半導體晶圓製造步驟中，製造半導體晶圓101。關於半導體晶圓101之構成及製造之細節予以後述。
於步驟2之表面保護膠帶貼附步驟中，為了保護半導體晶圓101之表面(電路部)免受步驟3進行之背面研磨時之應力或污染，而於半導體晶圓101之表面貼附表面保護膠帶102。詳細而言，於藉由膠帶輥103a而移動之表面保護膠帶102之下固著半導體晶圓101。藉由將半導體晶圓101之表面按壓於表面保護膠帶102之接著面，而於半導體晶圓101之表面貼附表面保護膠帶102。其後，使用膠帶切割器依半導體晶圓101之形狀切取表面保護膠帶102，並將沿著半導體晶圓101切掉之無用膠帶部分捲繞回收。
於步驟3之背面研磨步驟中，為了將半導體晶圓101設為特定之厚度，而研磨半導體晶圓101之背面(未貼附表面保護膠帶102之面)。於背面研磨步驟中，作為研磨裝置使用研磨滾輪105及研磨載台106。半導體晶圓101係背面向上固定於研磨載台106。研磨滾輪105配置於研磨載台106之上方，且於半導體晶圓101側具備磨石104。以使研磨載台106與研磨滾輪105旋轉之狀態藉由磨石104研磨半導體晶圓101之背面，藉此將半導體晶圓101之厚度調整成與封裝之種類相應之特定厚度。
於步驟4之切割膠帶貼附步驟中，作為步驟6之切割(半導體晶圓101之切斷)之準備，將半導體晶圓101之背面貼附於切割膠帶107。詳細而言，切割膠帶107係貼附於晶圓環108，半導體晶圓101係於晶圓環108之內側貼附於切割膠帶107。
於步驟5之表面保護膠帶剝離步驟中，使用剝離膠帶109，自半導體晶圓101剝離表面保護膠帶102。詳細而言，將藉由膠帶輥103b而移動之帶狀之剝離膠帶109貼附於表面保護膠帶102，其後自半導體晶圓101剝離，藉此將表面保護膠帶102自半導體晶圓101剝離。
於步驟6之切割步驟中，半導體晶圓101被切斷(切割)成特定之晶片尺寸(元件區域10：參照圖4)。半導體晶圓101係使用切割刀片110，沿著下述之切割區域11(劃線：參照圖4)，於縱向及橫向切斷。藉由切割半導體晶圓101，使每個元件區域10(參照圖4)單片化，而形成半導體晶片111即半導體元件。
於步驟7之晶片接合步驟中，將半導體晶片111配置於島狀物112，且搭載於引線框架(未圖示)。詳細而言，於島狀物112上塗佈漿料113。又，使藉由夾頭114拾取之半導體晶片111載置於漿料113上之特定位置。再者，以使半導體晶片111載置於漿料113之特定位置之狀態，使漿料113熱硬化。
於步驟8之打線接合步驟中，半導體晶片111與引線116、或半導體晶片111與其他半導體晶片電性連接。詳細而言，將接合焊墊115與引線116藉由導線117電性連接，藉此將半導體晶片111與引線116電性連接。又，同樣，將接合焊墊115與形成於其他半導體晶片111之接合焊墊115藉由導線117電性連接，藉此將半導體晶片111與其他半導體晶片111電性連接。導線117可使用例如金線、銀線、銅線、鋁線等。
於步驟9之樹脂鑄模步驟中，以鑄模樹脂119被覆半導體晶片111、島狀物112、漿料113、接合焊墊115、導線117、及引線116之一部分，而形成上述之封裝121。詳細而言，於固著有引線框架(未圖示)之鑄模模具118，以活塞120注入鑄模樹脂119(塑膠樹脂)，其後使鑄模樹脂119熱硬化，藉此形成封裝121。
於步驟10之外裝鍍敷步驟中，去除漏出至外部引線、即未以鑄模樹脂119被覆之引線116上之鑄模樹脂溢料。其後，使用者以可將半導體裝置100焊錫安裝於基板之方式，對外部引線實施焊錫鍍敷。
於步驟11之標記步驟中，於封裝121之表面標記品種名等必要資訊。必要資訊之標記時，係使用例如使用熱硬化油墨等之油墨印刷必 要資訊之方法、或藉由雷射照射於封裝表面刻入必要資訊之方法。
於步驟12之成形加工步驟中，將各封裝自引線框架各個切離，且使用模具，將外部引線加工成特定形狀。
於步驟13之測試步驟中，使用測試器判定所製造之封裝為電性良品或不良品。
於步驟14之外觀檢查步驟中，根據所設定之檢查基準之內容，確認所製造之半導體裝置100之最終外觀狀態。外觀檢查時，例如使用人為確認之目視檢查或利用檢查機進行之測定檢查等。
於步驟15之包裝步驟中，將所製造之半導體裝置100收納於特定之包裝。作為上述特定之包裝，例如具有使用塑膠套之套包裝、使用塑膠托盤之托盤包裝、及使用包裝捲帶之捲帶與捲軸之包裝等。再者，藉由鋁疊層密封上述包裝，而將封裝防濕包裝。又，上述包裝係收納於指定之盒體並出貨。
以上為每次製造半導體裝置100時必要之步驟之概要。本實施形態之半導體晶片111之製造方法係尤其在與步驟1之半導體晶圓製造步驟及步驟6之切割步驟對應之步驟中具有特徵。於下文中進行詳細說明。
(半導體晶圓101之構成)
首先，關於半導體晶圓101之構成，基於圖4予以說明。圖4(a)係顯示半導體晶圓101之整體之俯視圖。圖4(b)係放大顯示半導體晶圓101之一部分之俯視圖。圖4(c)係(b)所示之半導體晶圓101之B-B線箭頭向視剖面圖。
半導體晶圓101係如圖4(a)、(b)所示，具有複數個元件區域10(半導體元件)及切割區域11。切割區域11係以區劃複數個元件區域10之方式設置成格柵狀。又，各元件區域10係以密封環4包圍，且於密封環4之內側，形成有電路及接合焊墊115。
又，半導體晶圓101係如圖4(c)所示，具有矽系基板1、GaN系半導體膜2、介電質膜3、密封環4、保護膜5、及切割區域11。
於矽系基板1(基板)之表面，形成有GaN系半導體膜2。於GaN系半導體膜2上，形成有介電質膜3及密封環4。於對向之密封環4之間形成有切割區域11。
(半導體晶片111之各製造步驟中的半導體晶圓101)
其次，關於半導體晶片111之各製造步驟中的半導體晶圓101，基於圖1(a)、(b)進行說明。圖1(a)、(b)係用以說明本實施形態之半導體晶片111之製造方法之圖。詳細而言，圖1(a)係放大顯示半導體晶圓101之一部分之俯視圖。又，圖1(b)係半導體晶片111之各製造步驟中圖1(a)所示之半導體晶圓101之A-A線箭頭向視剖面圖。此處，圖1(b)所示之第1步驟至第7步驟係如下所述，與上述之半導體裝置100之製造方法之各製造步驟對應。
第1步驟至第4步驟係與上述步驟1之半導體晶圓製造步驟對應。第5步驟係與上述步驟2之表面保護膠帶貼附步驟及步驟3之背面研磨步驟對應。第6步驟係與上述步驟4之切割膠帶貼附步驟及步驟5之表面保護膠帶剝離步驟對應。第7步驟係與上述步驟6之切割步驟對應。以下對第1步驟至第7步驟進行說明。
於第1步驟中，於矽系基板1上形成GaN系半導體膜2。矽系基板1之厚度及大小係適當設定，於本實施形態中，矽系基板1設為厚度625μm、6英吋尺寸。
於第2步驟(半導體元件形成步驟)中，於GaN系半導體膜2上形成介電質膜3，且形成複數個元件區域10(半導體元件)。又，於複數個元件區域10形成電路。再者，於各元件區域10之周邊以包圍元件區域10之方式形成密封環4。又，密封環4係以自介電質膜3突出之方式形成。
再者，於半導體晶圓101中，由密封環4包圍之元件區域10以外之部位係區劃區域9。換言之，於第2步驟中，以將半導體晶圓101區劃成複數個元件區域10之方式，以格柵狀形成區劃區域9。
於第3步驟中，於介電質膜3及密封環4上形成保護膜5。
於第4步驟(切割區域形成步驟)中，於區劃區域9中，藉由以蝕刻去除介電質膜3及保護膜5，而形成槽6、即切割區域11。詳細而言，於半導體晶圓101中，對區劃區域9以外之區域進行標記。換言之，於元件區域10之位置配置遮罩(未圖示)。其後，以去除介電質膜3及保護膜5之方式進行蝕刻(例如濕蝕刻)。其結果，因可抑制配置有遮罩之元件區域10之腐蝕，故殘留元件區域10，且去除未被遮蔽之區劃區域9中的介電質膜3及保護膜5，而形成槽6，即槽形狀之切割區域11。此時，於本實施形態中，完全去除區劃區域9內之介電質膜3及保護膜5。槽6之寬度係適當設定，於本實施形態中，將槽6之寬度設為90μm。
於第5步驟中，為了保護半導體晶圓101之表面免受半導體晶圓101之背面研磨時之應力或污染，而於半導體晶圓101之表面貼附表面保護膠帶102。又，為了將半導體晶圓101設為特定之厚度，而研磨半導體晶圓101之背面。此時，因矽系基板1與GaN系半導體膜2之熱膨脹係數或晶格常數不同，故於矽系基板1與GaN系半導體膜2之界面附近產生有較大之應力。因此，於半導體晶圓101之背面研磨時存在半導體晶圓101破裂之可能性。因此，為避免半導體晶圓101破裂之風險，亦可使用WSS(晶圓支撐系統)。
於第6步驟中，作為切割之準備，將半導體晶圓101貼附於切割膠帶107。又，使用剝離膠帶109(參照圖3)，自半導體晶圓101剝離表面保護膠帶102。此時，亦可逆轉順序，首先剝離表面保護膠帶102後，貼附至切割膠帶107等。
於第7步驟(切割步驟)中，將半導體晶圓101切斷成特定之晶片尺寸。對藉由去除介電質膜3及保護膜5而形成之槽6、即切割區域11進行切割，藉此切斷半導體晶圓101。半導體晶圓101係藉由切斷而單片化，形成半導體晶片111。
於本實施形態中，半導體晶圓101係藉由區劃區域9而區劃成複數個元件區域10。因此，藉由對形成於區劃區域9之切割區域11進行切割，可獲得複數個半導體晶片111(半導體元件)。又，藉由於區劃區域9中去除介電質膜3及保護膜5，而形成切割區域11。因此，由於可於已去除介電質膜3及保護膜5之切割區域11切斷半導體晶圓101，故而可於半導體晶圓101之切斷時減少產生於矽系基板1與GaN系半導體膜2之界面附近之層間龜裂、表面崩缺、及膜剝落。因此，由於可不使用雷射切割而減少上述層間龜裂等，故可抑制製造成本。又，因可不蝕刻GaN系半導體膜2而減少上述層間龜裂等，故可縮短製造時間。其結果，可謀求半導體晶片111之製造中的成品率之改善及生產率之提高。關於層間龜裂、表面崩缺、及膜剝落之減少，詳細內容係予以後述。
另，切割條件係適當設定，於本實施形態中，將切割條件設為刀片旋轉數30,000rpm、切割速度5mm/s。
又，刀片切割之方式不特別限定。然而，於藉由沿著切斷線(本實施形態中為切割區域11)切削1次而切斷半導體晶圓101之全切方式中，切割刀片110之負載較大，使表面崩缺或層間龜裂之產生率較高。因此，於本實施形態中，採用使用刃之厚度不同之2片旋轉刃，藉由2次切削而切斷半導體晶圓101之階段式切割方式。
詳細而言，於階段式切割方式中，切割刀片110其刃之厚度具有單軸旋轉刃(未圖示)與刃之厚度較單軸旋轉刃更薄之2軸旋轉刃(未圖示)。單軸旋轉刃係於第1次切削中切斷GaN系半導體膜2。又，2軸旋 轉刃係於第2次切削中切斷矽系基板1，且切斷半導體晶圓101。其結果，如圖1(b)之第7步驟所示，形成單軸切割區域7與2軸切割區域8。藉由上述構成，與1次切斷基板之全切方式相比，階段式切割方式可減輕切割刀片110之負擔。其結果，與上述全切方式相比，階段式切割方式可於半導體晶圓101之切斷時進而減少產生於矽系基板1與GaN系半導體膜2之界面附近之表面崩缺或層間龜裂、及膜剝落。又，因藉由階段式切割方式，可減輕切割刀片110之負擔，故藉由抑制刀片切割之堵塞，可進而減少表面崩缺20或層間龜裂21。
(表面崩缺及層間龜裂)
其次，對本實施形態之半導體晶片111之製造方法與先前之半導體晶片之製造方法之、切割後所產生之表面崩缺20及層間龜裂21之不同，基於圖5至圖8進行說明。表面崩缺20係表示半導體晶圓101之表面之缺陷，層間龜裂21係表示矽系基板1與GaN系半導體膜2之界面附近之裂紋。表面崩缺20或層間龜裂21會致使半導體晶片111之成品率降低。
圖5係顯示先前之半導體晶片之製造方法中切割後之半導體晶圓101之表面狀態之圖。先前之半導體晶片之製造方法係表示不蝕刻切割區域11中的介電質膜3，而對半導體晶圓101進行刀片切割之製造方法。於先前之半導體晶片之製造方法中，如圖5所示，於切割後之半導體晶圓101產生有表面崩缺20及層間龜裂21。所產生之表面崩缺20及層間龜裂21係與密封環4接觸。又，亦可見侵入於密封環4內、即元件區域10中之層間龜裂21。
圖6係顯示先前之半導體晶片之製造方法中切割後之半導體晶圓101之剖面狀態之圖，且係產生有層間龜裂21之部分之剖面圖。層間龜裂21係如圖6所示，產生於矽系基板1與GaN系半導體膜2之附近。再者，層間龜裂21產生於GaN系半導體膜2下。因此，以形成於GaN 系半導體膜2上之密封環4，無法防止層間龜裂21侵入於元件區域10內。其結果，存在層間龜裂21侵入於元件區域10內之可能性。
對此，於本實施形態之半導體晶片111之製造方法中，藉由去除GaN系半導體膜2上之介電質膜3及保護膜5，可減少矽系基板1與GaN系半導體膜2之層間應力。其結果，發揮可減少表面崩缺20或層間龜裂21之效果。關於上述效果，基於圖7及圖8，於下文中進行說明。
圖7係顯示本實施形態之半導體晶片111之製造方法中切割後之半導體晶圓101之表面狀態之圖。可見表面崩缺20及層間龜裂21與圖5比較減少及縮小。
圖8係顯示針對切割後之半導體晶圓101中表面崩缺20及層間龜裂21之產生量，比較本實施形態之半導體晶片111之製造方法與先前之半導體晶片之製造方法之圖表。於圖8中，不去除介電質膜係表示先前之半導體晶片之製造方法，去除介電質膜係表示本實施形態之半導體晶片111之製造方法。又，X軸表示所產生之表面崩缺20及層間龜裂21自槽側面向元件區域10內部延伸之寬度(對槽側面之距離)，Y軸表示產生表面崩缺20及層間龜裂21之數量。
表面崩缺20及層間龜裂21係如圖8所示，與先前之半導體元件之製造方法比較，本實施形態之半導體晶片111之製造方法其產生數較為減少。再者，表面崩缺20及層間龜裂21自槽側面向元件區域10內部延伸之寬度亦變小，侵入於元件區域10內之表面崩缺20及層間龜裂21亦減少。又，其結果，亦可抑制由表面崩缺所引起之膜剝落之產生數。
如圖7及圖8所示，可知根據本實施形態之半導體晶片111之製造方法，可減少表面崩缺20或層間龜裂21。
如上所述，若利用本實施形態之半導體晶片111之製造方法，則可減少表面崩缺20或層間龜裂21。因此，可改善半導體晶片111之成 品率，且與先前之半導體晶片之製造方法比較，可抑制製造成本。
〔實施形態2〕
關於本發明之實施形態2之半導體晶片111之製造方法，基於圖9至圖12進行說明。另，為便於說明，對具有與實施形態1所說明之構件相同功能之構件附記相同符號且省略其說明。
實施形態2與實施形態1於下述方面有所不同。
於實施形態1中，在第4步驟形成槽6時，區劃區域9內之介電質膜3及保護膜5係完全去除。與此相對，於實施形態2中，區劃區域9內之介電質膜3及保護膜5不完全去除。即，於實施形態2中，切割區域11係以於區劃區域9之兩側部殘留有介電質膜3及保護膜5之狀態形成(參照圖9(b))。
根據上述構成，與實施形態1即不於區劃區域9之兩側部殘留介電質膜3而形成切割區域11之半導體晶片111之製造方法比較，可進而減少切割時產生之表面崩缺20、層間龜裂21、及膜剝落。於下文中進行詳細說明。
(半導體晶片111之各製造步驟中的半導體晶圓101)
首先，關於半導體晶片111之各製造步驟中的半導體晶圓101，基於圖9(a)、(b)進行說明。圖9(a)、(b)係用以說明本實施形態之半導體晶片111之製造方法之圖。詳細而言，圖9(a)係放大顯示半導體晶圓101之一部分之俯視圖。又，圖9(b)係半導體晶片111之各製造步驟中圖9(a)所示之半導體晶圓101之C-C線箭頭向視剖面圖。又，第1步驟至第3步驟、及第5步驟至第7步驟係與實施形態1相同。
於第4步驟(切割區域形成步驟)中，於區劃區域9內，以蝕刻去除介電質膜3及保護膜5，而形成槽6a、即切割區域11。此時，於區劃區域9中以距密封環4特定距離之範圍內殘留有介電質膜3及保護膜5之狀態形成槽6a。詳細而言，於半導體晶圓101中，在元件區域10、及區 劃區域9中距密封環4特定距離之範圍內，配置遮罩(未圖示)。其後，以去除介電質膜3及保護膜5之方式進行蝕刻(例如濕蝕刻)。此時，可抑制配置有遮罩之元件區域10及區劃區域9中上述範圍之腐蝕。其結果，殘留元件區域10及區劃區域9中之上述範圍，且去除未遮蔽之區劃區域9中之介電質膜3及保護膜5，並形成槽6a即切割區域11。換言之，切割區域11係以於區劃區域9之兩側部殘留有介電質膜3及保護膜5之狀態形成。
根據上述構成，與實施形態1相比，可進而減少切割時產生之表面崩缺20、層間龜裂21、及膜剝落。另，區劃區域9及槽6a之寬度等係適當設定，於本實施形態中，將區劃區域9之寬度設為90μm，將區劃區域9中自密封環4殘留介電質膜3之寬度設為15μm，及將槽6a之寬度設為60μm。
(表面崩缺及層間龜裂)
其次，對本實施形態之半導體晶片111之製造方法與實施形態1之半導體晶片111之製造方法之、切割後所產生之表面崩缺20及層間龜裂21之不同，基於圖10至圖12進行說明。
圖10係顯示本實施形態之半導體晶片111之製造方法中切割後之半導體晶圓101之表面狀態之圖。於實施形態1之半導體晶片111之製造方法中，與先前之半導體晶片之製造方法相比，可減少半導體晶圓101之表面崩缺20或層間龜裂21之產生數，但難以防止表面崩缺20或層間龜裂21接觸於密封環4、及侵入於元件區域10內。
然而，本實施形態中，表面崩缺20及層間龜裂21係如圖10所示，納入已去除介電質膜3之槽6a之範圍內。又，比較圖7所示之實施形態1之半導體晶片111之製造方法中切割後之半導體晶圓101之表面狀態與圖10，亦可以說，於本實施形態中，表面崩缺20及層間龜裂21之大小較小，半導體晶圓101之狀態良好。關於上述半導體晶圓101之 狀態良好之理由，於下文中進行說明。
於本實施形態中，將第4步驟中形成於GaN系半導體膜2上之介電質膜3殘留於區劃區域9之兩側部。藉此，區劃區域9之兩側部之GaN系半導體膜2係被介電質膜3覆蓋。與此相對，位於已去除介電質膜3之槽6a之GaN系半導體膜2係未被介電質膜3覆蓋。因此，於切割區域11中產生之應力係不朝向被介電質膜3覆蓋之GaN系半導體膜2與矽系基板1之界面，而於元件區域10之近前側向上(保護膜5側)傳遞。因此，藉由切割區域11之切割而產生之層間龜裂21係如圖11所示，在侵入於元件區域10之前向槽6a之端部6b方向向上發展。圖11係顯示藉由實施形態2之半導體晶片111之製造方法切割後之半導體晶圓101之狀態之剖面圖。
如此，在形成槽6a時，藉由於區劃區域9之兩側部殘留介電質膜3，可抑制層間龜裂21侵入於元件區域10內之GaN系半導體膜2與矽系基板1之界面。又，因區劃區域9之兩側部係以介電質膜3覆蓋GaN系半導體膜2之表面，故可抑制表面崩缺20侵入於元件區域10。因此，切割後之半導體晶圓101之狀態良好。
圖12係顯示關於切割後之半導體晶圓101中表面崩缺20及層間龜裂21之產生量，比較本實施形態之半導體晶片111之製造方法與實施形態1之半導體晶片111之製造方法之圖表。於圖12中，全去除介電質膜係表示實施形態1之半導體晶片111之製造方法，殘留部分介電質膜係表示本實施形態之半導體晶片111之製造方法。又，X軸係表示所產生之表面崩缺20及層間龜裂21自槽側面向元件區域10內部延伸之寬度(距槽側面之距離)，Y軸係表示產生表面崩缺20及層間龜裂21之數量。
根據本實施形態之半導體晶片111之製造方法，表面崩缺20及層間龜裂21係如圖12所示，與實施形態1之半導體晶片111之製造方法比 較，產生數進而減少，且自表面崩缺20及層間龜裂21之槽側面朝向內部延伸之寬度進而變小。又，未出現與密封環4接觸、或侵入於密封環4內之表面崩缺20及層間龜裂21。
如上所述，根據本實施形態之半導體晶片111之製造方法，因可減少表面崩缺20或層間龜裂21，故可改善半導體晶片111之成品率，與實施形態1之半導體晶片111之製造方法比較，可進而提高生產率。
〔總結〕
本發明之態樣1之半導體元件(半導體晶片111)之製造方法包含：半導體元件形成步驟，其係藉由於形成於基板上(矽系基板1)之GaN系半導體膜(2)上形成介電質膜(3)而形成複數個半導體元件(元件區域10)；切割區域形成步驟(第4步驟)，其係藉由去除區劃上述複數個半導體元件之區劃區域(9)中的上述介電質膜而形成槽形狀之切割區域(11)；及切割步驟(第7步驟)，其係藉由切割上述切割區域，而切出上述複數個半導體元件。
根據上述構成，介電質膜係藉由切割區域而區劃成複數個半導體元件，因而藉由對切割區域進行切割，可切出複數個半導體元件(半導體晶片)。又，藉由在去除切割區域之介電質膜後進行切割，可減少切割時產生於基板與GaN系半導體膜之界面附近之層間龜裂、表面崩缺、及膜剝落。因此，可不使用雷射切割而減少上述層間龜裂等，故而可抑制半導體元件之製造成本。又，因可不對GaN系半導體膜進行乾蝕刻而減少上述層間龜裂等，故可縮短半導體元件之製造時間。其結果，可謀求改善半導體元件之製造之成品率及提高生產率。
本發明之態樣2之半導體元件(半導體晶片111)之製造方法亦可於上述態樣1中的上述切割區域形成步驟(第4步驟)中，於上述區劃區域(9)之兩側部殘留上述介電質膜(3)。
根據上述構成，於區劃區域之兩側部殘留介電質膜且形成切割 區域。因此，與不於區劃區域之兩側部殘留上述介電質膜而形成切割區域之情形相比，可進而減少切割時產生於基板與GaN系半導體膜之界面附近之龜裂、表面崩缺、及膜剝落。
本發明之態樣3之半導體元件(半導體晶片111)之製造方法亦可於上述態樣1或2中的上述切割步驟(第7步驟)中，使用切割刀片(110)。
根據上述構成，因使用切割刀片而並非雷射切割對基板進行切割，故可抑制半導體元件之製造成本。
本發明之態樣4之半導體元件(半導體晶片111)之製造方法係於上述態樣3中，上述切割刀片(110)可至少具有切斷上述GaN系半導體膜(2)之單軸旋轉刃、及切斷上述基板(矽系基板1)之2軸旋轉刃，且於上述切割步驟(第7步驟)中，藉由階段式切割方式進行切割。
根據上述構成，切割刀片具有切斷GaN系半導體膜之單軸旋轉刃、及切斷上述基板之2軸旋轉刃，且使用切割刀片藉由階段式切割方式切斷半導體晶圓。因此，與1次切斷半導體晶圓之全切方式比較，可減輕刀片之負擔。又，與上述全切方式比較，可進而減少於半導體晶圓之切斷時產生於基板與GaN系半導體膜之界面附近之龜裂、表面崩缺、及膜剝落。
發明之態樣5之半導體元件(半導體晶片111)係自具有形成於基板(矽系基板1)上之GaN系半導體膜(2)、與形成於上述GaN系半導體膜上之介電質膜(3)之半導體晶圓(101)切出之半導體元件，上述半導體元件係藉由切割已去除上述介電質膜之切割區域(11)而自上述半導體晶圓切出。
根據上述構成，而發揮與態樣1相同之效果。
本發明並非限定於上述之各實施形態，可於技術方案所示之範圍內進行多種變更，適當組合不同實施形態中分別揭示之技術性步驟而獲得之實施形態亦包含於本發明之技術性範圍內。再者，藉由組合 各實施形態中分別揭示之技術性步驟，可形成新的技術性特徵。
[產業上之可利用性]
本發明之半導體元件之製造方法係可較好地利用於製造半導體元件之領域。

Claims (4)

  1. 一種半導體元件之製造方法，其特徵在於包含：半導體元件形成步驟，其係藉由於形成於基板上之GaN系半導體膜上形成介電質膜，而形成複數個半導體元件；切割區域形成步驟，其係藉由利用蝕刻去除區劃上述複數個半導體元件之區劃區域中的上述介電質膜而形成槽形狀之切割區域；及切割步驟，其係藉由切割上述切割區域，而切出上述複數個半導體元件，於上述切割區域形成步驟中，於上述區劃區域之兩側部殘留上述介電質膜。
  2. 如請求項1之半導體元件之製造方法，其中於上述切割步驟中，使用切割刀片。
  3. 如請求項2之半導體元件之製造方法，其中上述切割刀片至少具有切斷上述GaN系半導體膜之單軸旋轉刃、及切斷上述基板之2軸旋轉刃；且於上述切割步驟中，藉由階段式切割方式進行切割。
  4. 一種半導體元件，其特徵在於，其係藉由切割而自半導體晶圓切出者，該半導體晶圓包含：GaN系半導體膜，其形成於基板上；及介電質膜，其形成於上述GaN系半導體膜上；且上述半導體元件具有已利用蝕刻去除上述介電質膜之切割區域，上述介電質膜殘留於上述切割區域的兩側。
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