201126648 六、發明說明： 【發明所屬之技術領域】 本發明總體上涉及電子器件，更具體地說是涉及了形成 半導體的方法》 【先前技術】 在過去’半導體工業利用各種不同的方法和裝置來從半 導體晶圓分割個別半導體晶片，從其上製造了晶片。典型 地’一種被稱作劃片（scribing)或者切塊的技術被用來使用 金剛石切削輪或者晶圓錯（wafer saw)沿著在個別晶片之間 的、BB圓上所形成的劃片柵格部分地或者完全地貫穿晶圓 進行切削。為了顧及切削工具的對齊和寬度，每個劃片柵 格通常具有大的寬度，一般在大約一百五十（150)微米左 右，其消耗了半導體晶圓中很大的一部分。另外，在整個 半導體晶圓上，為所有的劃片柵格進行劃片所需要的時間 可能會超過一個小時。這一時間降低了製造領域中的產量 和製造能力。 另一種分割個別半導體晶>1的方法是，使⑽射沿著劃 片栅格貫穿晶圓進行切削。然而，鐳射劃片難以控制，並 會因此導致不均勻的分離。鐳射劃片還需要昂貴的鐳射裝 置以及操作人員使用的保護裝置。而且，有報導稱鐳射劃 片會降低晶片的強度，這是因為在分割期間，錐射炫 沿晶片周緣的晶體結構。 :應地’可取的是有一種能夠從半導體晶圓分割晶片的 方法，其可增加晶圓上半導體晶片的數量；提供更加均句 151883.doc 201126648 的分割；減少執行分割的時間 【實施方式】 :並且具有更窄的劃片線。 為了容易和清楚地說明’在圖中的元件不必是成比例 的’並且在不同圖中相同的參考標記指示相同的元件。另 卜欣出於易於&述的目的省略了公知步驟和元件的描述和 =°為了使附圖清楚’將設備結構中的摻雜區域示出為 般-有直線的周緣和角度精確的棱角。然而，本領域中 的技術人員要理解的是，由於摻雜物的擴散和活化，換雜 £域的周緣可能_般不是直線的，並且其棱角可能沒有精 確角度豸由本領域中的技術人員領會到的是，使用單詞 近〇地」《大致上」意味著，預計有參數的元件值非 节接近叹疋值或設定位置。然而，正如在本領域中公知 的一樣’總是會有輕微的差異，其阻止所述值或位置不會 嚴格地與設定值相同。在本領域中，相對於和描述一樣的 理想目標’可接受多達至少百分之十〇〇%)(以及關於半導 體摻雜濃度多達半分之二十(20%))的差異作為合理差異。 圖1是圖解說明了半導體晶圓10的簡化平面視圖，所述 半導體晶圓10具有複數個半導體晶片，諸如晶片12、14、 和16，其形成在該半導體晶圓10上。晶片12、14、和16在 晶圓10上相互間隔開，這在間隔中形成分割線，諸如分割 線13和15。正如本領域中所公知的一樣，複數個半導體晶 片中的全部一般在所有側面上都相互分離，這通過按區域 形成分割線，諸如線13和15。 圖2示出沿截線2_2取得的、圖！中晶圓1〇的放大的橫截 151883.doc 201126648 面部分。出於使附圖及其描述清楚的目的，所示截線2_2 僅橫截晶片12和晶片14和16的一些部分。晶片12、14、和 16可以是任何類型的半導體晶片，其包括二極體、縱向電 晶體、橫向電晶體、或者包括各種不同類型半導體器件的 積體電路。半導體晶片12、14、和16—般包括半導體基底 18’其可具有形成在基底18内的摻雜區域，以便形成半導 體晶片的主動部分和被動部分。在圖2中示出的橫截面部 分沿每個晶片12、14、和16的接觸墊24取得。接觸墊24 — 般是金屬的，其形成在半導體晶片上，以便提供在半導體 晶片與半導體晶片外部元件之間的電接觸。例如，接觸墊 24可被形成以接收可被隨後連接到墊24上的焊線，或者可 被形成以接收可被隨後連接到墊24上的焊球或者其他類型 的互連結構。基底18包括塊基底19,其具有形成在塊基底 19表面上的外延層2〇 ^ 一部分外延層2〇可被摻雜以形成 摻雜區域21 ’該區域則被用來形成半導體晶片丨2、丨4、或 16的主動部分和被動部分。層20和/或區域21可在一些實 施方式中被省略，或者可處於晶片12、14、或16的其他區 域中。典型地，介電質23在基底18的頂面上形成，以便將 墊24從個別半導體晶片的其他部分隔離，並且將每個墊 從相鄰半導體晶片絕緣。介電質23通常為在基底18的表面 上形成的二氧化矽薄層。接觸墊24—般是金屬的，其中接 觸墊24的一部分與基底18電接觸，並且其另一部分在介電 質23的邻分上形成。在形成了包括金屬接觸和相關中間 層介電質（未顯示）的晶片12、14、和16之後，典型地，在 151883.doc 201126648 全部複數個半導體晶片上形成介電質26，以作用為關於晶 圓1〇,以及關於每個個別半導體晶片12、14、和16的鈍化 層。介電質26通常在晶圓10的整個表面上形成，諸如藉由 毯覆性介電質沉澱的方式，並且在一些實施方式中可^接 觸墊24下面形成。介電質26的厚度一般大於介電質”的厚 度0 圖3示出在從晶圓10分割晶片12、14、和16的過程中一 個隨後階段上，圖2中晶圓10的橫截面部分。在形成介電 質26的鈍化層之後’由虛線示出的遮罩32可被應用到基底 18的表面，並且被圖案化以形成開口，該開口暴露了覆蓋 在每個塾24以及覆蓋在晶圓1()的_些部分上的介電質^的 -些部分，所述晶圓1G的—些部分上形成了分割線諸如 分割線13和15。之後，穿過遮罩32中的開口蝕刻介電質％ 和23以暴露在其下面的墊24和基底18的表面。在形成分割 線諸如線13和15的區域中形成貫穿介電質的開口， 其作用為分割開口 28和29。穿過覆蓋在塾24上的介電質％ 形成的開口作用為接觸開口。較佳地使用選擇性地蝕刻介 電質比蝕刻金屬要快的工藝來執行蝕刻過程。所述蝕刻過 程钱刻介電質一般比其姓刻金屬至少快十⑽倍。用於基 底㈣材料較佳為石夕，而用於介電質26的材料較佳為二氧 匕夕或氮化^^ 電質26的材料還可以是其他介電質材 料’其能夠被㈣但同時不會钮刻墊24的材料，諸如聚醯 亞胺墊24的金屬作用為蝕刻停止層，其防止墊μ的暴露 部分因㈣而被移除。在較佳的實施方式中，使用氣基的 151883.doc 201126648 各向異性的反應離子蝕刻過程。 在形成了貫穿介電質26的開口之後，遮罩32被移除，並 且使基底18變薄以從基底18的底面17移除材料，並且減小 基底18的厚度。一般來說，將基底18變薄至不大於大約一 百到二百（100到200)微米的厚度。對本領域中的技術人員 而5，這種變薄程式是公知的。在使晶圓丨〇變薄之後，包 括了基底18的底面π的晶圓1〇的底面可用金屬層27來金屬 化。在一些實施方式中，可省略這種金屬化步驟。隨後， 晶圓1〇通常被連接到輸送帶或者承載帶3〇上，其有助於在 分割了複數個晶片之後支撐所述複數個晶片。對本領域中 的技術人員而言，這種承載帶是公知的。 圖4示出在從晶圓1〇中分割半導體晶片I〗、14、和16的 過程中一個隨後階段上的晶圓10。穿過在介電質26中形成 的分割開口 28和29蝕刻基底18。該蝕刻過程使分割開口 28 和29從基底18頂面開始延伸，並完全貫穿基底18。該蝕刻 過程通常使用化學作用來執行，所述化學作用以遠高於蝕 刻介電質或金屬的速率來選擇性地蝕刻矽。該蝕刻過程蝕 刻石夕一般比其蝕刻介電質或金屬至少快五十（5〇)倍，且較 佳為快一百（100)倍。典型地，使用各向同性和各向異性的 蝕刻條件的組合的深反應離子蝕刻系統被用來蝕刻從基底 18的頂面開始完全貫穿基底18的底面的開口 28和29。在較 佳的實施方式中’使用一種通常被稱為Bosch過程的過 程’以便各向異性地蝕刻貫穿基底18的分割開口 28和29。 在一個示例中，晶圓10在Alcatel深反應離子蝕刻系統中使 151883.doc 201126648 用Bosch過程進行蝕刻。 分割開口28和29的寬度—般為五到十（5,微米。這樣 -個寬度；i以確保能夠形成完全貫穿基㈣的開口邮 29,並且該寬度還要^夠窄，以便能夠在短時關隔内形 成開口。典型地，能夠在近十五到三十（15到3())分鐘的時 間間隔内形成貫穿基底i 8的開口 2 8和2 9。因為晶圓i 〇的所 有分割線是同時形成的，所以能夠在近十五到三十〇5到 30)分鐘的相同時間間隔内形成跨越晶圓1〇的所有分割 線。之後’晶圓10由承載帶3〇支撐，同時該晶圓ι〇被帶到 -個選擇和放置裝置35上，利用該裝置可從晶圓ι〇移除每 個個別的晶片。典型地，裝 朝上推動每個被分割的晶片 置35具有基座或其他工具，其 ’諸如晶片12，以便將其從承 載帶30釋放，並一 該分割的晶片移除 直上升到達真空撿拾器（未顯示），其將 。在選擇和放置過程期間，位於開口 2 8 和29下面的薄金屬底層27的一部分斷裂，並被留在帶儿 圖5不出半導體晶片42、44、和46的放大橫截面部分， 所述半導體晶片在晶圓1〇上形成並且是圖丨_4的描述中所 說明的晶片12、14、和16的可供選擇的實施方式。在基底 18的頂面上形成介電質23之後並且在形成墊24之前的製造 狀態上（圖1)示出晶片42、44、和46。除了晶片42、44 '和 46每個都具有各自的隔離溝槽5〇、54、和58之外，這些晶 片42、44、和46類似於晶片12、14、和16，所述隔離溝槽 圍繞晶片並且將其從相鄰的晶片隔離。溝槽5〇、54、和Μ 151883.doc 201126648 一般是靠近每個晶片的外側周緣形成的《溝槽5〇、54、和 58被形成從基底18的頂面延伸第一距離進入塊基底19。每 個溝槽50、54、和58—般被形成為進入基底19的開口，該 開口具有在開口側壁上形成的介電質，並且一般用介電質 或其他材料，諸如石夕或多晶石夕來填充。例如，溝槽5 〇可包 括在溝槽開口側壁上的二氧化矽介電質5 i，並可用多晶碎 52填充《相類似地，溝槽54和58各自包括在溝槽開口側壁 上的二氧化矽介電質55和59，並可用多晶矽56和60填充。 分割線43在溝槽50與54之間形成，並且分割線45在溝槽5〇 與58之間形成。溝槽50和54鄰近分割線43形成，並且溝槽 50和58鄰近分割線45形成。對於本領域中的技術人員而 5 ’形成溝槽50、54、和58的方法是公知的。應當注意的 是，溝槽50和54僅用作說明目的，並且能夠是任何數量 的、各種形狀、大小的隔離槽區（tub)或溝槽，或其組合。 圖ό根據本發明示出從晶圓丨0分割半導體晶片42、44、 和46的過程中一個隨後階段上的晶圓1〇。在形成溝槽5〇、 54、和58之後’形成晶片42、44、和46的其他部分，包 括：形成接觸墊24 ’以及形成覆蓋晶片42、44、和46的介 電質26。介電質26 —般還覆蓋晶圓1〇的其他部分，其中包 括要形成为割線43和45的基底18的部分。之後，應用並圖 案化遮罩32以暴露位於下面的、要形成分割線和接觸開口 處的介電質26。穿過遮罩32中的開口蝕刻介電質26，以暴 露在下面的墊24和基底18的表面。被形成貫穿要形成分割 線（諸如線43和45)的區域中的介電質26的開口作用為分割 151883.doc •10· 201126648 開口 47和48。用來形成貫穿介電質23和26的開口 47和48的 姓刻過程與用來开）成介電質23和26中的開口28和29(圖3)的 過程大致相同。較佳地形成開口 47和48，使得在相應溝槽 50、54、和58的側壁上的介電質51、55、和59不位於開口 47和48的下面，使得這些介電質在隨後形成分割線“和仏 的操作中不會被影響。 在形成貫穿介電質26的開口 47和48之後，遮罩32被移 除，並且基底18被變薄，以及用金屬層27金屬化，正如此 前在圖3的描述中所說明的一樣。在一些實施方式中，這 種金屬化的步驟可被省略。而在金屬化之後，晶圓1〇通常 被連接到承載帶30。 圖7示出晶圓10中分割半導體晶片42、44、和46的過程 中一個隨後階段上的晶圓10。穿過在介電質26中形成的分 割開口47和48蝕刻基底18。該蝕刻過程使分割開口 47和48 延伸，即從基底18的頂面開始完全貫穿基底18。開口47和 48通常離介電質51 ' 55 '和59至少Q 5微米。㈣過程通 常是各向同性㈣刻’其以遠高於㈣介電質或金屬的速 率選擇性祕㈣，該速率-般比_介電#或金屬的速 率至少要快五十（50)倍，而較佳為快__百（⑽)倍。因為溝 槽側壁上的介電質保護基底18的石夕，所以能夠使用各向同 性的蝕刻。與使用Bosch過程或有限使用B〇seh過程所獲得 的蝕刻量相比，所述各向同性的蝕刻的蝕刻量要高得=^ 然而，該各向同性的蝕刻典型地從下部切削位於溝槽M、 54、和58下面的基底19的一些部分 典型地，使用氟化學 151883.doc -11 - 201126648 作用的下游蝕刻被用來從基底18的頂面開始完全貫穿基底 18的底面钮刻開口 28和29 ’並且暴露位於開口 28和29下面 的層27的一部分。在一個示例中，以使用了完全各向同性 蝕刻的深反應離子蝕刻系統來蝕刻晶圓1 〇，所述深反應離 子蝕刻系統可向各個不同的製造商購買，其中所包括一種 系統 FL 33716 可向位於 10050 16th Street North St_ Petersburg的PlasmaTherm, LLC購買。在另一些實施方式 中’各向同性的蝕刻可被用於大多數的蝕刻，而各向異性 的蝕刻則可用於蝕刻的另一個部分（B〇sch過程）。例如，可 使用各向同性的触刻’直到開口 28和29的延伸深度大體上 與溝槽50、54、和58深度相同為止，並且之後可使用各向 異性的蝕刻以防止從下部切削溝槽5 〇、5 4、和5 8。 分割開口 47和48的寬度一般大約和開口 28和29的寬度相 同。可用類似於移除晶片12、14、和16的方式，從帶30移 除晶片42、44、和46。 在另一個實施方式中’可以用第一距離將溝槽50和58間 隔開’所述距離足以允許標準的劃片工具或晶圓鋸延伸貫 穿開口 48。因此’位於開口 48下面的層27的部分可藉由劃 片工具或晶圓鋸割斷；或者為了使開口 47和48以下的晶圓 1〇斷裂藉由在滾筒上彎曲而沿開口 47和48進行分離；或者 用其他技術諸如鐳射劃片，等等進行移除。溝槽5〇和54可 具有相類似的間隔’其有助於以相類似的方式割斷位於下 面的層27的部分。對於使用劃片工具對層27進行劃片的方 法而言’層27可沿劃片工具的路徑斷裂以完成分離。之 151883.doc •12· 201126648 後，可藉由標準的選擇和放置技術從帶3〇移除晶片a、 44、和46。這些方法有助於分離和分割晶片42、44、 46 » 口 彳供選擇地，當開口47和48的深度達到溝㈣、Μ、和 58的底部或者剛好經過溝槽的底部時，可終止各向同性的° 蝕刻。之後，基底19的暴露部分可用劃片工具劃片或者 用晶圓鑛鑛切，以便完成晶片的分離或者用其他技術諸如 錯射切削，等等將晶片移除。鑛切技術可被延長以貫穿金 属層27進行鑛切。當基底19的材料沿著由劃片工具形成的 路徑斷裂時’劃片技術將使層27斷裂。 本領域中的技術人員將領會到的是，使用溝槽5〇、… 和58來分割晶片會產生具有光滑側壁的晶片42、料、和 46’其藉由溝槽的介電質側壁與晶片的外部元件絕緣。所 述介電質形成晶片側壁上的介電質材料。由溝槽介電質所 提供的絕緣能夠降低晶片和外部元件之間的漏電流。該結 構還能夠提高晶片的擊穿電壓。相比於鐘射分割晶片^ 法’使用溝槽50、54、和58還能夠提高晶片的強度。 再次參考用來使開口 47和48延伸進入基底19的飯刻技 術，本領域中的技術人員將領會到的是，各向同性的姓刻 的触刻速度比各向異性的钱刻快，因此，使用各向同性姓 刻以快速移除開口的材料，直到開口 47和48的延伸深度與 溝槽50、54、和58 一樣深為止。隨後，使用各向異性的餘 刻防止從下部切削溝槽50、54、和58。因此，緊接使用各 向同性的触刻之後的各向異性的敍刻提供了高的產量和好 151883.doc 13 201126648 的橫向控制，甚至是對於比溝槽5〇、54、和58深的開口叨 和48的部分也是如此。 圖8不出分割在半導體晶圓1〇上形成的半導體晶片η、 72、和73的另一個可供選擇的方法的示例實施方式中的一 個階段。圖8在基底18的頂面上形成介電質23之後和在形 成墊24之前的製造狀態上（圖2)示出晶片7173的放大橫截 面部分。除了晶片71-73具有圍繞晶圓1〇上的每個晶片的 單個隔離溝槽79之外，這些晶片71_73類似於晶片42、 44、和 46。 正如將在下文中看到的一樣，一個從晶圓1〇分割半導體 晶片的方法的例子包括：提供半導體曰曰曰目，諸如晶圓ι〇， 其具有半導體基底，例如基底18，並且還具有在半導體基 底上形成的複數個半導體晶片，其中半導體晶片藉由半導 體晶圓的一些部分被相互分離，並且其中所述半導體晶圓 的些部分在要形成分割線，諸如線13和15的位置上；在 所述半導體晶圓的一些部分上形成溝槽諸如溝槽79，其中 所述溝槽@繞複數個半導體晶片中每__個的周邊，包括在 溝槽側壁上形成介電質層，和在溝槽内形成填充材料，並 且填充材料毗連側壁上的介電質層；形成覆蓋複數個半導 體晶片一些部分的鈍化層，諸如層26;蝕刻貫穿鈍化層以 及任何位於下面的層的第一開口，例如開口82,以便至少 暴露溝槽的填充材料；並且蝕刻第二開口諸如開口Μ，其 貫穿填充材料並且貫穿位於填充材料下面的半導體基底中 任何部分，使得第二開口從半導體晶圓的表面開始延伸完 151883.doc 201126648 全貫穿半導體基底’其中第二開口的蝕刻是穿過第一開口 執行的。 所述方法的另一個實施方式還包括形成溝槽開口，其從 半導體基底表面開始延伸第一距離進入半導體基底其中 半導體基底的第一部分位於溝槽開口下面，並且其中所述 溝槽開口具有側壁和底部；在溝槽開口侧壁上以及溝槽開 口底部上形成介電質層，並且在側壁之間留出溝槽開口中 一部分作為未使用空間；移除溝槽開口底部上的介電質； 並且毗連在溝槽側壁上的介電質層用填充材料來填充溝槽 開口的未使用空間。 除了溝槽79延伸圍繞晶片71-73中每—個的周邊以及 在晶圓ίο上形成的任何其他晶片的周邊之外，溝槽79的形 成類似於溝槽50、54、或58中的任一個，其在圖5_7的描 述中已說明過了。形成溝槽79以包括介電f襯墊8〇，諸如 二氧化矽，其在溝槽79的側壁和底部上。在較佳的實施方 式中，移除介電質襯墊80的底部，使得溝槽79的底部打 開，正如以虛線84示出的一樣。移除襯墊8〇底部的一個實 例方法包括：應用具有暴露了溝槽79的開口的遮罩85，以 及實施各向異性的蝕刻，諸如墊塊蝕刻（spacer以仏），該 蝕刻貫穿襯墊80的底部。可選擇性地蝕刻矽上的介電質， 以便防止破壞位於溝槽79下面的基底18部分。一般來說， 在移除襯墊80的底部之後移除遮罩85。在移除溝槽79的底 部之後，用填充材料81填充溝槽79的剩餘開口。填充材料 8 1 一般是矽基材料，諸如多晶矽，以便促進隨後過程步 151883.doc 15 201126648 驟，正如此後將看到的一樣》 本領域中的技術人員將領會的是，晶片71_73中的任何 一個還可具有在晶片内部的其他溝槽，諸如溝槽78，並且 形成這些溝槽時可使用的過程操作與形成溝槽79時所使用 的相類似。依賴於將要提供的功能，溝槽78可保持底部氧 化物’或者使底部氧化物被移除。例如，可用捧雜的多曰 矽填充溝槽78，並且提供諸如到金屬層27(未顯示在圖8中） 或者到基底18底部或背面上的另一個觸點的低阻抗基底觸 點或背面觸點。然而，溝槽78的較佳實施方式不具有被移 除的底部’並且溝槽78較佳在晶片内部且不圍繞晶片的外 側周邊。因此’溝槽79可與溝槽78,或其他相類似溝槽同 時形成，由此降低製造成本。正如本領域中的技術人員可 理解的一樣，晶片71-73可具有在基底18上或者其以内形 成的各種不同的主動或被動元件。 溝槽79在分割線76和77内形成，並且較佳是在這些分割 線的中部’使得溝槽79的中部近似為分割線的中部。正如 此後將看到的一樣，將近似穿過溝槽7 9中部發生分割。 圖9示出從晶圓1 〇中分割半導體晶片71 _73的示例方法中 一個隨後階段上的晶圓1 〇。在形成溝槽79之後’形成晶片 71-73的其他部分’包括：形成接觸墊24和形成覆蓋晶片 71-73的介電質26。介電質26—般還覆蓋晶圓1〇的其他部 分’其包括要形成分割線77和76的基底1 8的部分。之後， 應用並圖案化遮罩87以暴露位於下面的、要形成分割線76 和77 ’以及接觸開口處的介電質26。遮罩87類似於圖3中 131883.doc -16 - 201126648 示出的遮罩32;然而，遮罩87的位置通常猶有不同。遮罩 中要形成刀割線76和77的開口也在溝槽79以上。穿過遮 罩中的開口钱刻介電質26以暴露位於下面的溝槽79内的 真充材料81纟型地’所述钱刻還暴露位於下面的塾μ。 被形成貫穿要形成分割線’諸如線76和77的區域中的介電 質26的開口作用為分割開口 82和83。用來穿過介電質卿 成開口 82和83㈣刻過程與用來在介電質23和26中形成開 口 28和29(圖3)的過程大體相同。典型地形成開口 82和83， 使得相應溝槽79側壁上的介電質襯墊8〇位於開口 “和“的 下面然而，只要暴露了材料81，就不必再暴露介電質襯 墊80 了。典型地’因為是橫截面視圖，所以儘管開口以和 83是圍繞晶片71-73的單個開口的兩部分’但仍被示出為 兩個開口。 在形成貫穿介電質26的開口 82和83之後，遮罩87被移 除，正如藉由虛線所示出的一樣，並且基底丨8被變薄正 如虛線86所示出的一樣。所述變薄移除位於溝槽79下面的 基底18中的大部分。基底18一般不會被一直向上變薄至溝 槽79的底部，這是因為介電質襯墊8〇的介電質材料可能破 壞用來變薄晶圓10的工具，或者可能導致刮花晶圓1〇。較 佳地，基底1 8被變薄’直到溝槽79距基底18的底部大約二 到五（2-5)微米為止《在一些實施方式中，基底18可被變 薄’直到暴露溝槽79的底部為止。之後，基底18的底面用 金屬層27金屬化，正如此前在圖3的描述中所說明的一 樣。在一些實施方式中可省略這種金屬化步驟。隨後，晶 151883.doc • 17· 201126648 圓10通常被連接到共用承載基底或者共用載體，諸如承載 帶3 0。 圖10示出從晶圓10中分割晶片71_73的方法的實施方式 的例子中一個隨後階段上的晶圓10。形成貫穿填充材料81 的第二開口以形成貫穿基底18的分割線76和77。與圖4的 描述中所說明的银刻相類似，較佳地，使用介電質％作為 遮罩穿過分割開口 82和83蝕刻基底18 ^蝕刻過程形成貫穿 材料81的開口。典型地，蝕刻大致上移除所有的材料81， 以延伸分割線76和77，其從基底18的頂面開始完全貫穿溝 槽79的填充材料81。蝕刻過程通常是各向同性的蝕刻，其 以遠高於蝕刻介電質或金屬的速率選擇性地蝕刻矽，該速 率一般比蝕刻介電質或金屬的速率至少要快五十（5〇)倍， 而較佳為快一百（100)倍。因為對介電質上的矽而言，所述 蝕刻步驟是選擇性的，因此，填充材料81被移除，而不會 蝕刻溝槽79側壁上的介電質襯墊8(^因此，溝槽79側壁上 的介電質襯墊80保護基底丨8的矽不受各向同性的蝕刻。與 使用Bosch過程或有限使用]5〇3(；11過程所獲得的蝕刻量相 比，所述各向同性的蝕刻的蝕刻量要高得多。該各向同性 的蝕刻過程蝕刻貫穿填充材料81和位於溝槽79下面的基底 1 8的任何部分。因此，各向同性的蝕刻快速蝕刻貫穿溝槽 79和任何位於其下面的基底18的部分，由此分割晶片71_ 73。快速的蝕刻改善了產量並降低了製造成本。本領域中 的技術人員將領會到的是’填充材料81中的矽基材料還降 低了介電質襯墊80和基底19的材料上的應力。 151883.doc 201126648 沿貫穿溝槽79的分割線76和77分割晶片71-73導致分割 線僅佔用了半導體晶圓上很小的空間。例如，包括填充材 料81的溝槽79的寬度典型為僅大約三（3)微米寬。因此，分 割線76和77可僅為大約三微米寬，而不是在其他晶片分割 方法’諸如劃片或晶圓鋸方法中的一百微米寬。對於本領 域中的技術人員而言很明顯的是，可省略使晶圓丨〇變薄的 步驟，並且可繼續對材料81的触刻直到開口 82和83延伸貫 穿晶圓1 0為止。 正如圖4的描述_所說明的 τ氷 :¾评π双直 來使位於開口 82和83下面的金屬層27的任何部分斷裂以 便完成晶片71-73的分割。本領域中的技術人員將領會到 的是，還可使用其他方法來割斷分割線76和77内的金屬層 27。例如’可在應用帶3〇之前，可沿著層27的底側對金二 層27進行劃片，因此當執行選擇和放置動作時，將沿著這 條線割斷層27。可供選擇地，可在應用帶3〇之前二層二 的背面韻刻位於分割線76和77下面的㈣的部分。所述層 27的姓刻分割層27。割斷層27的另—種方法是向位於晶圓 1〇下面的帶3G的部分上吹送Μ射流。空氣將導致帶30向 上伸展並割斷層27，即在㈣分割線76和77下 部分中割斷。另外，环肱 ,^ 3 甩 ％ 另外了將-未破顯示出的第二承載帶 晶圓1〇的正面。然後，可將帶30移除。移除帶30的步驟將 割斷層^即在位於分割線76和77下面的層抑部分㈣ 斷。k些割斷層27的可供選擇的方法中的任 此處所描述的分割方法中的任何—個。 固可用於 15i883.doc -19- 201126648 晶片圖:;示出已在，，述中說明過了的分割半導體 、和1 6的另一個可供選擇的方法的 式中的一個階段。 丨貫施方 二以下將要看到的一樣’從半導體晶圓分割半導體晶 的-種方法的例子包括：提供具有半導體基底的半導體 晶圓，所述半導體基底具有第一厚度、頂面、底面、以及 複數料導體W，所料㈣W在半導錄底上形 成，並且藉由在要形成分割線處的半導體晶圓的部分相互 分離開；形成覆蓋複數個半導體晶片的分割遮罩層，諸如 A1N 93，形成貫穿分割遮罩層的開口 ；形成貫穿位於下面 的層的開口並暴露半導體基底表面中一部分；以及使用分 割遮罩層中的開口作為遮罩，同時触刻第一開口使其從半 導體基底表面的暴露部分延伸，並完全貫穿半導體晶圓。 所述方法的另一個實施方式還包括：先於使用分割遮罩 層中的開口作為遮罩的步驟，將半導體晶圓連接到承載 帶；並且還包括使用選擇和放置裝置以分離承載帶，並且 從複數個半導體晶片的其他晶片中分離複數個半導體晶片 的一個半導體晶片。 所述方法的另一個實施方式包括：形成分割遮罩層，其 為材料是金屬化合物、氮化鋁、氮化欽、金屬-矽化合 物、矽化鈦、矽化鋁、聚合物、或聚醯亞胺中一種的層。 在如圖2的描述中所說明的，在基底18的頂面形成介電 質23之後並隨後形成墊24和介電質26的製造狀態上示出晶 片12、14、和16。在形成介電質26之後，形成分割遮罩以 151883.doc -20- 201126648 促進形成貫穿基底18的開口而不會钱刻位於下面的層，諸 如介電質26的部分。在較佳的實施方式中，用氮化鋁 (A1N)形成分割遮罩。在該較佳實施方式中，八…層”至少 要形成在介電質26上。一般來說，要應用層91以覆蓋所有 的晶圓10。 圖12示出圖11中晶圓10的橫截面部分，其在從晶圓1〇分 割晶片12、14、和16的方法的一個較佳實施方式的例子中 的隨後階段上。在形成A1N層91之後，遮罩32可被應用到 基底18的表面，並且被圖案化以形成開口，其暴露介電質 26的一些部分，這些部分覆蓋每個墊24，並且還覆蓋要形 成分割線，諸如分割線13和15處的晶圓1〇的一些部分。 為了形成遮罩32，在晶圓1〇上應用攝影遮罩材料，並隨 後將晶圓1 0暴露在光，諸如紫外光中以改變所述遮罩材料 被暴露部分的化學成分，以便形成具有開口的遮罩32，所 述開口覆蓋在要形成分割線以及要形成墊24的位置上。然 後使用顯影劑移除遮罩材料的未暴露部分，由此留下帶有 開口 28和29的遮罩32，所述開口28和29覆蓋在要形成各自 分割線13和15的位置上。已經發現的是，可使用一種基於 氫氧化銨的顯影劑也可產生移除A1N層91位於遮罩材料的 未暴露部分以下的一部分的顯影劑。以虛線92示出層…的 被移除部分，並且將層91的剩餘部分識別為AiN %。正如 下文中將要看到的一樣，A1N 93作用為分割遮罩。 圖13示出圖丨2中晶圓10的橫截面部分’其在從晶圓1〇分 割晶片12、M、和16的方法的一個可供選擇實施方式的例 151883.doc •21 · 201126648 子中的另一個隨後階段上。穿過遮罩32和A1N 93中的開口 來蝕刻介電質26和23，以便暴露位於下面的墊24和基底丄8 的表面。在要形成分割線，諸如線13和15的區域中形成貫 穿A1N 93和介電質26和23的開口作用為分割開口 28和29。 所述被形成貫穿了覆盖塾24的介電質26的開口作用為接觸 開口。較佳地執行蝕刻過程，其中使用的過程選擇性地比 钱刻金屬快地蝕刻矽基介電質諸如二氧化矽或氮化梦。所 述蝕刻過程蝕刻矽基介電質一般比其蝕刻金屬至少快十 (10)倍。塾24的金屬作用為蚀刻停止層，其防止墊24的暴 露部分因蝕刻而被移除。在較佳的實施方式中，正如上文 中所說明的，使用氟基的各向異性的反應離子蝕刻。 在形成了貫穿介電質26和23的開口之後，如虛線所示出 的，通常移除遮罩32。正如通過虛線86示出的，基底18一 般被變薄以從基底18的底面移除材料，並且減少基底18的 居度。一般來說’將基底18變薄至不大於大約為二十五到 四百（25到400)微米的厚度，並且較佳為在大約五十到二百 五十（50-250)微米之間。對於本領域中的技術人員而言， 這種變薄程式是公知的。在晶圓1 0被變薄之後，可用金屬 層27來金屬化晶圓1〇的背面。在一些實施方式中，可省略 這種金屬化步驟。隨後，晶圓丨〇通常被連接到輸送帶或者 承載帶30上’其有助於在分割了複數個晶片之後支撐所述 複數個晶片。 圖14示出從晶圓1〇分割半導體晶片I]、14、和16的可供 選擇的方法的示例實施方式中的一個隨後階段上的晶圓 15I883.doc •22· 201126648 10。使用AIN 93作為遮罩，以钮刻貫穿分割開口 28和29的 基底18。A1N 93保護介電質26不受蝕刻的影響β A1N 93可 具有大約五十到三百（50-300)埃的厚度，並且仍然保護介 電質26。較佳地，A1N 93厚度為大約二百（2〇〇)埃。蝕刻過 程使分割開口 28和29從基底18的頂面開始延伸，並完全貫 穿基底18。如圖4的描述中所說明的Bosch過程一樣，所述 蝕刻過程通常使用化學作用來執行，所述化學作用以遠高 於蝕刻介電質或金屬的速率來選擇性地蝕刻矽。之後如圖 4的描述中所說明的一樣，可從帶3〇移除晶片12、14、和 16 ° 因為A1N 93是介電質，其可被留在晶片12、14、和16 上》在另一些實施方式中，可在貫穿基底18，諸如藉由使 用顯影劑進行蝕刻之後移除A1N 93 ;然而，這需要額外的 處理步驟。使用光遮罩顯影劑來移除層91的被暴露部分節 省了處理步驟，由此降低了製造成本。使用A1N %作為遮 罩，保護介電質26不受由蝕刻操作造成的影響。 本領域中的技術人員將領會到的是’可在此處所描述的 分割方法的任何一個中使用A1N 93作為分割遮罩以保護介 電質26，所述分割方法包括圖5-7的描述中所說明的方 法’諸如圖15中tf出的方法’並且A1N 93還可被用於圖8_ 10的描述中所說明的方法。 、在另一些實施方式中，可用除了 A1N之外的其他材料形 成分割遮罩°這些用於分割遮罩的其他材料是那些大致上 不會被用來蝕刻基底1 8的矽的過程蝕刻的材料。因為用來 151883.doc •23- 201126648 钱刻基底1 8的钱刻程式钮刻石夕比飯刻金屬快，所以可使用 金屬化合物作為形成分割遮罩的材料。這種金屬化合物的 例子包括· A1N、氮化鈦、氧化鈦、氮氧化鈦、以及其他 金屬化合物。在使用除A1N以外的金屬化合物的例子中， 可類似於層91來應用金屬化合物層。然後，可使用遮罩3 2 來圖案化金屬化合物層，以便形成在該金屬化合物中的開 口。之後，可移除遮罩32，並且所述金屬化合物的剩餘部 为此夠在钱刻基底1 8期間保護位於下面的層，諸如介電質 26。所述金屬化合物可被留在隨後要分割的晶片上，或者 可在完成分割之前，諸如在從帶3〇分離晶片之前被移除。 另外，還可使用矽-金屬化合物來形成分割遮罩，這是 因為金屬-矽化合物中的金屬會防止蝕刻繼續進入金屬-矽 材料中。矽-金屬化合物的一些例子包括金屬矽化物，諸 如矽化鈦和矽化鈷。對於矽·金屬化合物的實施方式而 吕，可類似於金屬化合物的例子，形成並且圖案化矽-金 屬化合物層。然而，金屬·矽化合物一般為導體，因此必 須將其從晶片移除，諸如在完成從帶3〇分割晶片之前移除 金屬-梦化合物。 而且，可將聚合物用於分割遮罩。一種適合的聚合物的 例子是聚醯亞胺。也可使用其他公知的聚合物。類似於金 屬化合物，可圖案化所述聚合物，並可隨後將其移除或留 在晶片上。 圖16示出已在圖的描述中進行了說明的分割半導 體晶片12、14、和16的$ 一個可供選擇的方法的示例實施 15I883.doc -24· 201126648 方式中的一個階段。 正如下文中將要看到的—樣，-個從半導體晶圓分割半 導體晶片的方法的例子包括：提供具有半導體基底並且具 有複數個半導體晶片的半導體晶圓’所述複數個半導體晶 片在半導體基底上形成，並且藉由要形成分割線處的半導 體基底的—些部分來相互分冑；以錢刻貫通I導體基底 中-些部分的分割線開口 中從半導體基底的第一表面 形成所述分割線開口，由此產生在複數個半導體晶片之間 的間隔，所述蝕刻形成半導體晶片的側壁，其中半導體晶 片的頂面具有比半導體晶片的底面大的寬度。 在另一個實施方式中，所述方法還包括：蝕刻所述分割 線開口包括形成晶片的頂面寬度比底面寬度大差不多二到 十（2-10)微米。 另一個可供選擇的方法包括使用各向異性的蝕刻，以便 触刻以第一距離進入半導體基底的分割線開口；並且使用 各向同性的蝕刻來蝕刻分割線開口，以便將分割線開口延 伸至第二距離，同時還提高了分割線開口的寬度。 正如下文中將要看到的一樣，所述分割方法形成關於晶 片12、14、和16有角度的側壁，使得所述晶片的橫向寬度 在晶片頂部大於晶片底部。在蝕刻貫穿介電質26和23以暴 露基底18和墊24之後的製造狀態上示出晶圓10和晶片12、 14和16 ’正如圖3的描述中說明的一樣。選擇性地，可 使用A1N 93作為遮罩用於隨後的操作，正如在圖“-丨斗的 描述中說明的一樣。 151883.doc -25- 201126648 隨後’為了暴露基底18的表面，用各向同性的姓刻過程 來儀刻基底18和任何被暴露的塾24，所述各向同性的㈣ 過程以比蝕刻介電質或金屬高得多的速率選擇性地蝕刻 矽，蝕刻矽的速率一般比蝕刻介電質或金屬的速率至少快 五十（50)倍，且較佳為至少快一百（1〇〇)倍，正如在圖了的 描述中說明的一樣。執行蝕刻過程以使開口 28和29延伸進 基底18至疋’木度，化樣做橫向地延伸了開口的寬度， 同時也延伸了其深度以形成基底〗8中的開口 1 〇〇。因為所 述過程被用來形成關於晶片12、14、和16有角度的侧壁， 將使用複數個各向同性的蝕刻將開口 28和29的陸續增加寬 度，同時開口的深度延伸入基底18。在開口 1〇〇的寬度大 於介電質23和26中的開口 28和29的寬度之後，終止所述各 向同性的蝕刻。之後，將碳基聚合物1〇1應用到被暴露在 開口 100中的基底18的部分。 圖π示出圖16的描述中所說明階段的一個隨後階段。使 用各向異性的蝕刻來移除在開口 1〇〇底部上的聚合物1〇1的 部分’同時留下在開口 100側壁上的聚合物1 〇〗的部分。 圖18示出圓17的描述中所說明階段的一個隨後階段β使 用各向同性的蝕刻過程來蝕刻被暴露在開口 1〇〇内基底18 的表面’以及任何被暴露的墊24，這類似於圖16的說明中 的一個描述。所述各向同性的蝕刻再次橫向地延伸分割開 口 28和29的寬度，同時還延伸了其深度以形成基底18中的 開口 104。在開口 104的寬度大於開口 ι〇〇的寬度之後，通 常會終止各向同性的蝕刻，以便使開口的寬度隨著深度的 151883.doc •26· 201126648 增加而變寬《被留在開口 100的側壁上的聚合物l〇i的部分 保護了開口 100的側壁，以防止開口 1〇4的蝕刻影響開口 1〇〇寬度。在蝕刻開口 104期間，大致上所有的聚合物 都被從開口 1 〇〇的侧壁上移除。 之後，將類似於聚合物101的碳基聚合物1〇5應用到被暴 露在開口 104中的基底18的部分上。在形成聚合物1〇5期 間，操作通常再一次在開口 1〇〇的側壁上形成聚合物ι〇ι。 圖19不出圖18的描述中所說明階段的另一個隨後階段。 使用另一個各向異性的蝕刻來移除開口 1〇4底部上的聚合 物105的部分，同時在開口 1〇4的側壁上留下一部分聚合物 105。該過程步驟類似於圖17的描述中所解釋的步驟。 圖20不出可重複蝕刻序列，直到分割線13和15完全貫穿 基底1 8為止。可重複各向異性蝕刻以形成開口（諸如開口 108和112)、在開口側壁上形成聚合物、並且從開口底部 移除聚合物同時在側壁上留下聚合物的一部分（諸如聚合 物109和113)的操作序列，直到開口 28和29延伸貫穿基底 W以形成完全貫穿基底18的分割線13和15為止。在最後的 各向同性蝕刻，諸如為形成開口丨12的蝕刻之後，通常不 會沉澱所述聚合物，這是因為在隨後的操作中一般不需要 保遵基底18。雖然將聚合物i 〇 1 ' 1 〇5、和1 〇9示出在其各 自開口 100、104、和1〇8的側壁上，但是在完成所有操作 之後，本領域中的技術人員將領會到的是，用來形成開口 112的最後的各向同性蝕刻步驟實質上從其相應開口的側 壁上移除了這些聚合物。因此，這些聚合物是出於清楚解 151883.doc -27· 201126648 釋的目的被顯示的。 正如能夠從圖20中看到的一樣，晶片12、14、和i 6的側 壁從頂部向底部朝内傾斜，使得每個晶片底部的晶片寬度 小於在晶片頂部的晶片寬度。因此，在基底18頂部的晶片 的外側周緣超出基底18頂部的晶片的外側周緣一定距離 116’因此晶片13的頂面超出距離116而懸於底面17之上。 在一個實施方式中，有角度的側壁有助於在晶片的選擇和 放置操作期間内最小化損壞。對於這樣一種實施方式而 言’要確信的是，距離116應為晶片12、14、和16厚度的 百分之五到百分之十（54〇%)。在一個示例實施方式中， 距離116近似為一到二十（1_2〇)微米，因此在基底18底部的 晶片12的底部寬度可以比在表面^的晶片12的頂部寬度小 近似二到四十（2_40)微米。在另一個實施方式中，要確信 的疋，側壁應形成近似十五到四十度（丨5。_4〇。）的角丨丨8， 該角118在側壁和垂線，諸如垂直於基底18頂面的直線之 間。因此，開口 29的寬度每次被蝕刻延伸的量應當足以形 成角118。一般來說，分割線15_16的頂部比分割線的底部 乍大約一到四十（2_4〇)微米。本領域中的技術人員將領會 到的是，多次各向同性的蝕刻操作形成了每個晶片12、 14、和丨6的粗糙側壁，使得所述側壁具有沿著側壁參差不 齊的周緣。然而出於清楚說明的目的，上述周緣的參差程 度在圖16-21的圖解說明中有所誇大。這些側壁一般被視 為大致光滑的側壁。 圖21示出在選擇和放置操作期間帶有向内傾斜的側壁的 151883.doc -28· 201126648 晶片12、14、和16。正如能夠看到的，晶片12、I*、和16 的傾斜側壁允許沖杆35向上移動晶片中的一個，諸如晶片 12 ’而不會碰撞其他晶片，諸如晶片14和16。這有助於在 選擇和放置操作期間，減少破裂以及對晶片12' 14、和16 的其他損傷。 圖22示出沒有傾斜侧壁的其他晶片，以及在選擇操作期 間匕們可能會如何發生相互碰撞。這種配置有可能在選擇 和放置操作期間，導致對所述晶片的損傷，諸如對晶片周 緣的損傷6 圖23示出在圖16·22的描述中所說明的分割半導體晶片 12、14、和16並且形成有角度的或傾斜的側壁的另一個可 供選擇方法的實施方式例子中的一個階段。本領域中的技 術人員將領會到的是，也可以使用其他分割技術，諸如在 圖1-15的描述中所說明的技術，以從晶圓分割晶片並在晶 片上形成有角度的和傾斜的側壁。例如，在圖丨4的描述中 所說明的各向異性的蝕刻可被用來形成進入基底18内的開 口 28和29，其與基底is頂面相距第一距離no。因此，在 所述側壁的第一距離範圍内，側壁實質上是筆直的。然 後，可使用在圖16-22的描述中所說明的分割方法來完成 • 分割。第一距離的深度依賴於晶片的厚度，但典型地 將會多達晶片厚度的大約百分之五十（5〇%)。之後，蝕刻 以形成開口（諸如開口 1〇8和112)，在開口側壁上形成聚合 物，並且從開口底部移除聚合物同時在側壁上留下聚合Z 的一部分（諸如聚合物1〇9和113)，可重複以上這種各2異 151883.doc •29· 201126648 性的蝕刻序列，直到開口 28和29延伸貫穿基底18以形成完 全貫穿基底18的分割線13和15為止》 分割半導體晶片12、14、和16的另一個可供選擇方法的 貫施方式例子包括：使用各向異性的蝕刻，諸如圖丨4的描 述中所說明的一種各向異性的蝕刻，以便形成進入基底18 内的開口 28和29，其與基底丨8的頂面相距第一距離12〇。 因此，在所述側壁的第一距離範圍内，側壁實質上是筆直 的。隨後，可使用如圖16-22的描述中所說明的各向同性 的蝕刻，以便將分割線13和15的深度延伸至第二距離，該 第二距離大於距離12〇但尚未完全貫穿基底18。在延伸所 述深度的同時，各向同性的蝕刻還增加了線13和15的寬 度。延伸該寬度，使其寬於介電質26上的開口 28和29的寬 度。所述方法的最終部分可以使用各向異性的蝕刻以便在 靠近分割線底部位置上提供實質上為筆直的側壁。則此處 的分割線將會比中部寬。然後，能夠使用這種方法或者其 他方法的組合，以提供被改進的功能性，諸如鎖定在晶片 12、14、和16側壁或者周緣斜坡上的晶片模，使得晶7底 部寬於晶片頂部，或者晶片中部寬於晶片頂部。 圖24-圖28示出從晶圓10分割半導體晶片的另—個可供 選擇的實施方式例子巾各種不同階段上的晶圓_橫截面 視圖。圖24-圖28示出的晶圓10的橫截面視圖是沿著圖！* 的截線24-24提取的。圖24_圖28示出的可供選擇方法的示 例實施方式還包括一種減小晶圓丨〇厚度成 汗反4有變薄晶圓10的 可供選擇的方法。晶圓10包括半導體晶片12、i 16, 151883.doc •30- 201126648 以及分割線13和15，其被描述在圖丨_4 '圖8·2〇、和圖幻的 描述中。儘管出於使附圖和描述清楚的目的，未被顯示在 圖24-28中’晶圓1〇還能夠包括在圖5_7的描述中所說明的 以及分割開口 面部分大於圖2- 沿著分割線43和45的晶片42、44、和46， 47-48。因為在圖24中示出的晶圓1〇的橫載 23中不出的晶圓1〇的部分，所以圖24沿著額外的分割線示 出在晶圓10的頂面上形成的額外晶片，所述額外的分割線 包括分割線11、17、137 '和138，其類似於在圖2_23中任 一個的描述中所說明的分割線13和15或者43和45中的任何 一個。另外，圖24示出基底18，其具有在基底18的頂面與 基底18的底面或背面之間的厚度66。在基底18的頂面上形 成了半導體晶片’諸如晶片12、Μ、16、、和i4s之 後，變薄晶圓ίο以減少基底18的厚度66。在圖25·28示出 了減少厚度66的一個實施方式的例子。 關於圖25，在基底18的頂面上形成了半導體晶片之後， 晶圓ίο可被倒置，並連接到支撑帶或者支樓設備34，使得 基底18的頂面面向設備34。設備34可以是任何公知的設 備，其能夠被用來在變薄操作，諸如從背面研磨帶或者其 他設備的操作期間為晶圓提供支撐。 圖26示出從晶圓10分割晶片的方法的示例實施方式中的 一個隨後階段上的晶圓10。典型地，變薄晶圓1〇的整個底 面以便減少晶圓10的厚度，即從厚度66到厚度67，該厚度 67小於厚度66。可利用各種不同的公知方法來將晶圓1〇的 厚度減少至厚度67，諸如對本領域中的技術人員而言公知 151883.doc -31 - 201126648 f背面研磨、化學機械拋光（CMp)或者其他技術。在一些 實施方式中，該步驟在所述方法中可被省略。 一 隨後’將晶圓ίο底面的内部部分125進一步減少至厚度 68，其小於厚度66和67。用虛線示以形成内部部分125 期間被移除的晶圓10的底面部分。内部部分125的厚度並 型地藉由使内部部分125受到研磨操作來減少，或者藉由、 ,、他“。的技術來減少厚度。減少部分⑵的厚度會留下 外側輪緣127 ’其與晶圓1〇的外側周緣並列。因此，外側 輪緣127典型地維持厚度67。外側輪緣a?的厚度則足以提 供為處理或運輸餘下的晶圓1〇提供支樓。對本領域中的技 ，人員而言’用於減少内部部分125的厚度的工具和方法 :么知的。這些工具和方法的一個例子被包括在公開編號 為鹰6/〇244G96的美國專利中’其發明人為^職s吻a， 並於2006年11月2日公開。 圖出從曰曰圓1〇分割晶片的另一個隨後步驟。可從晶 圓卿除支揮設備34,並且將保護層135應用到晶圓_ 底面，特別是應用到内部部分125中的晶圓1〇的底面。設 備34可具有紫外線釋放機制，諸如當暴露在紫外光中時釋 放’或者其他公知的釋放機制。因為用於形成層135的方 法通常包括可能損傷設備34的高溫’所以移除設㈣。而 對於不包括這種高潘&音α 的實施方式，或者對於能抵抗這種溫 度的支撐設備而言’可保留設備34。儘管如此，設備34通 常還是必須在隨後的操作之前被移除。層135中的-部分 還可以被應用到外側輪緣127的底面，如保護層部分133示 151883.doc •32· 201126648 二在一些實施方式中，可掩蓋外側輪緣in以 遮罩；遵：刀133。例如’可形成層135的操作期間應用光 =1覆ά輪緣127，或者可使用陰罩，以便防 分 133。 Λ ' 圖28示出在另—個隨後製造階段上的晶圓Η)。在形成層 ⑴之後，通常會將晶圓1〇再次翻轉至直立狀態。將承載 ㈣應用到晶_的底面。在_些實施方式中，帶3〇連接 到溥膜框架62,以便為帶職供支I對於本領域中的技 術人員而t，這種薄膜框架和承載帶是公知的。應用帶％ 作為用來處理和支樓晶圓1〇的承載工具。對於使用不同的 栽體來處理晶圓1〇的實施方式而言，可使用不同的載體， 並且可省略帶30。應用帶3〇作為用來處理和支撐晶圓⑺的 承f工具。對於使用不同的載體來處理晶圓10的實施方式 而。，可使用不同的載體，並且可省略帶3〇。典型地，使 :真空吸盤來保持晶圓1G ’並使帶3G與晶圓1〇的底面形狀 —致’使得帶3G為晶圓1G提供—定支撑。之後，形成分割 開口 28、29、140、和141 ’其從晶圓1〇的頂面進入基底以 並達到層135而終止，其使用的方法與此前在圖2-圖23的 描述中所說明的、開口28和29或者開口47和48等在層27上 、冬止的開口的形成方式相類似。本領域中的技術人員將領 會到的疋，其他的分割開口通常與開口 28和29同時形成， 以便分割晶圓1〇的其他晶片。以不會被乾式蝕刻方法蝕刻 的材料形成層135，所述乾式蝕刻方法被用來形成分割開 28、29、140、和141。在一個實施方式中，保護層1 35 151883.doc •33- 201126648 是金屬或金屬化合物，並且所選擇的乾式蝕刻過程是一種 以比蝕刻金屬快得多的速率物的過程。這種過程已在 此前有所說明。在另一些實施方式中，保護層135可以是 一種此前說明過的氮化銘，或__種此前說明過的石夕-金屬 化合物。層135還可為與此前所說明的金屬層27的材料相 同的材料。此外1可隨分割開口28和2卜起形成分割開 口 140和141。以類似于形成開σ 28和29(或者開口 47和48) 的方式，形成貫穿基底1 8的分割開口丨4〇和丨4丨，以便形成 刀。1J線137和138。形成分割線137和138以便從餘下的晶圓 10上分離外側輪緣127。因此，被形成的分割線丨37和 通常上覆於内部部分125，並且位於外側輪緣Η?與任何半 導體明片之間，所述半導體晶片位於鄰近輪緣〗27處，諸 如半導體晶片144和145 ^例如，分割線137和138可以是一 (1)條連續不斷的分割線，其圍繞内部部分125的外側周緣 延伸，例如正好在形成了外側輪緣127的内緣處的晶體ι〇 的部分内延伸。 本領域中的技術人員將領會到的是，使用晶圓鋸或其他 類型的切削工具來從具有這樣一個内部部分125和輪緣127 的晶圓上分割晶片，將使内部部分125受到很大的機械應 力並且有可能使内部部分125内的晶圓1〇斷裂。另外，以 鐳射劃片移除輪緣127可能導致鄰近輪緣127的晶片重新結 晶。使用此處所說明的乾式蝕刻方法來移除輪緣127，將 最小化内部部分125上的機械應力’並且在移除輪緣127的 同時’或在從晶圓1〇分割晶片的同時減少破壞晶圓的可能 151883.doc -34- 201126648 性。 在某些情況下可取的是，從晶圓10移除輪緣127而不分 割在晶圓1〇上形成的晶片。對於這樣一種可供選擇的實施 方式，可形成分割線137和138以從晶圓1〇移除輪緣127， 而不形成用來分割晶圓10的晶片的分割線，諸如分割線 11、13、15、和17。在移除輪緣127之後，類似於帶30的 另一個帶可被應用到部分125的底面，諸如直接應用到層 13 5，並隨後可如此處所描述的一樣來分割晶片。在另一 些實施方式中，可保持帶30以支撐餘下的晶圓10。在分割 晶片之前移除輪緣127允許一快速且乾淨的方法，其減少 刮花晶片的可能和機械應力，由此改進收益和產量。 圖29-圖3 1示出從晶圓1 〇分割晶片的方法例子的另一個 可供選擇的實施方式中的各種不同階段。圖29示出正好在 圖26的描述中所說明階段之後的階段上的晶圓丨〇。從支撑 設備34移除晶圓1 〇，並且在内部部分丨25的底面上形成保 護層13 5。 參考圖30，可將承載帶63應用到晶圓1〇，以便為晶圓1〇 提供支撐。將承載帶63應用到晶圓1〇的頂部，使得基底18 的頂面面向帶63。典型地，帶63類似於此前所描述的帶 30。在一些實施方式中，帶63被連接到薄膜框架以，其類 似於框架62。應帛帶63作為用來處理和支樓晶圓1〇的承載 工具。對於使用不同的載體來處理晶圓10的實施方式而 。可使用不同的载體’並且可省略帶63。正如通過關於 部分133的虛線所示出的，移除在外側輪緣127的底面上形 151883.doc •35· 201126648 成的保護層135的任何部分。例如，外側輪緣127的底面可 受到研磨處理，且時間足以移除如虛線所示出的保護層部 分133，或者可掩蓋層135並且可從輪緣127上將部分η]蝕 刻下來。正如此前所說明的，在一些實施方式中，不會在 外側輪緣127上形成保護層部分133。 可利用乾式蝕刻過程將外側輪緣127的厚度減少至厚度 69。利用乾式蝕刻過程以減少外側輪緣127的厚度，所述 過程能夠是此處所描述的乾式蝕刻過程中的任何一個，諸 如那些用來形成分割開口，諸如分割開口 28和29的過程。 厚度69小於外側輪緣127的先前厚度67。厚度的的值通常 被選擇成使得外側輪緣127的底面接近厚度68，以至於承 載帶30(見圖31)可為晶圓1〇提供更好的支撐。在較佳的實 施方式中，厚度69形成輪緣127的底面，其大致上平行於 保護層135的外側表面。移除部分133允許乾式蝕刻減少輪 緣127的厚度。只要是在減少輪緣127的厚度之前移除部分 133的話’就可在所述方法的不同階段上移除部分133 ^在 些實施方式中’厚度68不大於大約五十（5〇)微米，並且 可以是二十五（25)微米或更少。本領域中的技術人員將領 會到的是，在這種厚度下，晶圓1〇可能變得易碎。與其他 厚度減少方法’諸如背面研磨或CMP相比，使用乾式钱刻 過程來減少輪緣127的厚度可最小化晶圓1〇上的機械應 力。 圖3 1示出隨後階段上的晶圓10。在減少了外側輪緣127 的厚度之後，晶圓1 〇通常被翻轉，並置於此前所說明的承 151883.doc •36- 201126648 載帶30上》形成分割開口 28和29，其從基底18的頂面開 始’貫穿基底18並到達在保護層135而終止。另外，還形 成分割開口 140和141，其典型地隨著開口 28和29—起形 成’以便從晶圓10的半導體晶片分離外側輪緣丨27。本領 域中的技術人員將領會到的是，通常與開口 28和29同時形 成分割開口，以便分割晶圓10的其他晶片。因為晶圓1〇的 厚度較小，使用乾式蝕刻來分割晶片將最小化晶圓1〇上的 機械應力，並減少破壞晶圓的可能性和其他損傷。 圖32-圖33示出從晶圓〖〇分割晶片的另一個可供選擇的 方法的示例實施方式中的各種不同階段。圖32示出正好在 圖26中所描述的階段之後的一個階段上的晶圓1〇。如此前 所說明的，-般可從晶圓10移除設備34,並且在内部部分 125的底面上形成保護層135。可圖案化保護層η，，使其 具有貫穿保護層135的開口，該開口大致上對齊要形成晶 圓ίο的分割線，諸如分割線u、13、15、17、137、和I” 處的晶圓H)的部分。本領域中的技術人員將領會到的是， 可利用各種不同的背面對齊技術，用來確保在層135上形 成的開〇奴位，以對齊要形成分割線，諸如分割線& 15、137、和138處的基底18的部分。 參考圖33’可使用保護層135作為遮罩以保護基底Η， 同時利用乾式餘刻過程以形成分割開口以、29' Μ。、和 141 ’其從基底18的底面開始延伸， ^ 10 , 70王頁穿基底18並從 的頂面穿出。被說明用於形成分割開 47和™刻方法中的任何-個’還可被用來形= 151883.doc •37- 201126648 割開口 140和141，以及貫穿基底18的任何其他的分割開 口。與形成分割開口同時，所述過程還蝕刻外側輪緣 127，由此將外側輪緣127的厚度減少至厚度69。正如此前 在圖30的描述中所說明的，在減少輪緣127的厚度並蝕刻 所述分割開口之前移除保護層133中的任何部分。連同形 成分割開口減少部分127的厚度減少了處理步驟，由此減 少了製造成本’並且減少所述厚度還最小化了曰曰曰圓1〇上的 機械應力，由此改進收益並減少成本。減少的輪緣127的 厚度使得更容易處理晶圓1 〇，並且在分割晶片之後更容易 移除這些晶片。在另一些實施方式中，可掩蓋輪 7, 並且在形成開口28、29、14〇、和141的同時不姓刻該輪緣 127。在形成分割開口之後’可將另一個承載帶(未顯示）， 諸如承載帶30’應用到晶_的底面’諸如應用到内部部 分125的底面，並且可翻轉晶圓1〇,或者内部部分125。之 後，可藉由此前所描述的選擇和放置技術或者其他技術來 移除半導體晶片。 熟練的技術人員能夠理解的是’形成半導體晶片的方法 的-個例子包括：提供具有半導體基底的半導體晶圓，所 述半導體基底具有第-厚度、頂面、底面、以及複數個半 導體晶片’諸如晶片12、14、或16，所述半導體晶片在半 導體基底的頂面上形成’並且藉由在要形成分割線，諸如 線！3和15處的半導體晶圓部分相互分離開；翻轉所述半導 體晶圓；將半導體晶圓底面的内部部分，諸如部分⑵的 厚度減少至第二厚度，其小於第_厚度，i留下有第一厚 151883.doc •38· 201126648 度的+導體晶圓的外側輪緣，例如輪緣127,其中外側輪 緣與半導體晶圓的外側周緣並列，並且其中所述内部部分 1立t複數個半導體晶片的τ面；在半導體晶圓底面的内部 部分上形成保護層，其中 '中所迹保濩層是金屬或者金屬化合 =金屬-石夕化合物中的一個；以及使用乾式姓刻以 ㈣夕卜側輪緣的第一厚度減少至第三厚度，所述第三厚度 、於-厚度’其中保護層保護内部部分不被乾式蝕刻， 使得所述第二厚度保持大致恒定。 本領域中的技術人員將理解的是，所述方法還可包括圖 二化保護層以暴露在要形成分割線處的半導體基底的部 2，並且使用乾式_來_分割線，其從半導體基底的 -面開始’貫穿半導體基底到達半導體基底的頂面。 形成半導體晶片的另—個方法的例子包括：提供具有半 導體基底的半導體晶圓，所述半導體基底具有第—厚度、 頂面、底©、以及複數個半導體晶片，諸如晶片 12/14/16 ’所述半導體晶片在半導體基底上形成，並且藉 由在要形成分割線處的半導體晶圓部分，諸如部分ip。 相互分離開；將半導體晶圓底面的内部部分，諸如部八 125一的广度減少至第二厚度，其小於第-厚度，並留；： 第一厚度的半導體晶圓的外側輪緣，例如輪緣a?，其 外側輪緣與半導體晶圓的周緣並列，並且其中所述内 分位於複數個半導體晶片的下面；在晶圓底面的内部部； 上形成保護層，其中所述保護層是金屬或者金屬化合物i 者金屬矽化合物中的一個·以及使用乾式蝕刻在要形1 151883.doc -39- 201126648 刀割線處形成分割開口包括：形成貫穿半導體基底的分割 開其中在外側輪緣與鄰近該外側輪緣的任何半導體晶 片之間形成至少一個分割開口。 ’’、練的技術人員還將領會到的是，所述方法還可包括使 用乾式蝕刻形成分割開口，其從半導體晶圓的頂面貫穿半 導體基底。 所述方法還可包括圖案化保護層以暴露要形成分割線處 的半導體晶圓底面的部分；並且使用乾式姓刻形成分割開 口的步驟可包括使用保護層作為遮罩同時使用乾式飯刻 來蝕刻刀割開口，其從半導體晶圓的底面開始，貫穿半導 體基底達到半導體基底的頂面，以及使用乾式钱刻來敍刻 外側輪緣，和將該外側輪緣的第一厚度減少至第三厚度， 所述第三厚度小於第一厚度。 考慮到以上全部内容，很顯然是公開了一種新穎的設備 和方法。除其他功能之外’主要包括使用乾式钱刻程式來 钱刻完全貫穿半導體晶圓的分割開口。這種乾式蝕刻過程 一般被稱為等離子蝕刻或者反應離子蝕刻（RIE)。從一個 側面蝕刻開口有助於確保分割開口具有非常直的側壁，由 此提供沿每個半導體晶片的每個側面的均勻分割線。蝕刻 完全貫穿半導體晶圓的分割開口促進窄分割線的形成，由 此允許在給定尺寸的晶圓上有更多空間用於形成半導體晶 片。所有的分割線一般是同時形成的。所述蝕刻過程快於 劃片或晶圓雜切過程，由此增加了製造領域中的產量。 形成貫穿溝槽填充材料的分割線促進窄分割線的形成， 151883.doc -40- 201126648 由此增加了晶圓利用率並減少成本。使用分割遮罩，有助 於在形成貫穿基底的分割線的同時，保護晶片的内部部 分。形成有角度的側壁’則減少了裝配操作期間的損傷， 由此減少了成本。在一些實施方式中，有角度的側壁一般 同時在所有晶片上形成。 雖然本發明的主題以具體的較佳實施方式進行了描述， 但很明顯的是，對於半導體領域中的技術人員而言本發 明可有很多備選方案和變體。例如，可從基底! 8上省略層 20牙/或21 一選地，可在形成覆蓋塾的接觸開口之 前或之後形成分割開口。而且，可在變薄晶圓1〇之前形成 所述分割開口，例如割開口可被形成部分地穿過基底 18 ’並且變薄過程可被用來暴露分割開口的底部。 【圖式簡單說明】 — —個半導體晶圓的實施方式的簡化 圖1根據本發明示出 平面圖； 圖2根據本發明示出 其為在從晶圓分割晶片 體晶圓的一部分； 一個實施方式的放大橫載面視圖 的過程中一個階段上的圖1中半 導 圖3根據本發明示出從 個隨後狀態； 圖4根據本發明示出從 一個隨後階段； 圖1的晶圓中分割 圖1的晶圓中分割 晶片 晶片 的過程中一 的過程中另 圖5示出半導體晶片的 片形成在圖1-4的晶圓上 並且疋圖1-4的插述中所^ 151883.doc 201126648 晶片的可供選擇的實施方式； 圖6根據本發明示出分割圖5中的晶片的過程中/個隨後 階段； 圖7根據本發明示出分割圖6中的晶片的過程中另一個隨 後階段； 圖8-圖1G根據本發明示出從圖！的半導體晶时分割晶 片的另一個方法的示例實施方式中的步驟； 曰圖11-圖14根據本發明示出從圖0的半導體晶圓中分割 晶片的另一個方法的示例實施方式t的步驟； 圖15根據本發明示出從圖14中的半導體晶圓中分割晶片 的另一個方法的示例實施方式； 圖16 -圖2 0根據本發明示出從圖1中的半導體晶圓中分割 晶片的另一個方法的示例實施方式中的步驟； 圖叫艮據本發明示出從圖4的半導體晶圓中分割晶片 的另-個方法的示例實施方式中的另一個階段； 圖22示出另一個分割方法； 圖23根據本發明示出從圖1巾 國1甲的+導體晶圓中分割晶片 的另一個方法的示例實摊 方式中的一個階段，該實施方式 為圖16-圖20中方法的—個可 j供選擇的實施方式； 圖24·圖：28根據本發明示出尬固，占 曰u 丁出從圖1中的半導體晶圓中分割 日曰片的另一個方法的示 視圖； 】實施方式中的不同階段的橫載面 圖29-圖31根據本發明示出 a μ ^ 出從圖1中的半導體晶圓中分割 的另個可供選擇的實施方式中的不同 151883.doc •42. 201126648 階段的橫截面視圖；及 圖32-圖33根據本發明示出從圖1中的半導體晶圓中分割 晶片的另一個可供選擇的方法的示例實施方式的不同階段 的橫截面視圖。 【主要元件符號說明】 10 半導體晶圓 11 分割線 12 半導體晶片 13 分割線 14 半導體晶片 15 分割線 16 半導體晶片 17 分割線 18 基底 19 塊基底 20 外延層 21 外延層 23 介電質 24 接觸墊 26 介電質 27 金屬層 28 分割開口 29 分割開口 30 承載帶 151883.doc • 43· 201126648 32 遮罩 35 選擇和放置裝置/沖杆 42 半導體晶片 43 分割線 44 半導體晶片 45 分割線 46 半導體晶片 47 分割開口 48 分割開口 50 隔離溝槽 51 介電質 52 多晶矽 54 隔離溝槽 55 介電質 56 多晶矽 58 隔離溝槽 59 介電質 60 多晶矽 62 框架 63 承載帶 64 薄膜框架 66 厚度 67 厚度 68 厚度 151883.doc 44- 201126648 71 半導體晶片 72 半導體晶片 73 半導體晶片 76 分割線 77 分割線 78 溝槽 79 溝槽 80 介電質襯墊 81 填充材料 82 開口 83 開口 84 虛線 85 遮罩 86 虛線 87 遮罩 91 A1N層 92 虛線 93 A1N 100 開口 101 碳基聚合物 104 開口 105 碳基聚合物 108 開口 109 聚合物 15I883.doc •45 201126648 112 開口 113 聚合物 116 距離 118 角 120 第一距離 125 内部部分 127 外側輪緣 133 保護層部分 135 保護層 137 分割線 138 分割線 140 分割開口 141 分割開口 144 半導體晶片 145 半導體晶片 151883.doc ·46·BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to electronic devices, and more particularly to a method of forming a semiconductor. [Prior Art] In the past, the semiconductor industry utilized various methods and devices. Individual semiconductor wafers are separated from a semiconductor wafer from which wafers are fabricated. Typically, a technique known as scribing or dicing is used to use a diamond cutting wheel or wafer saw along a scribe circle formed between BB circles between individual wafers. The grid is cut partially or completely through the wafer. To account for the alignment and width of the cutting tool, each dicing grid typically has a large width, typically about one hundred and fifty (150) microns, which consumes a significant portion of the semiconductor wafer. In addition, it can take more than an hour to scribe all of the scribe grids across the entire semiconductor wafer. This time reduces production and manufacturing capacity in the manufacturing sector. Another method of dividing individual semiconductor crystals > 1 is to cause (10) shots to be cut across the wafer along the scribe grid. However, laser dicing is difficult to control and can result in uneven separation. Laser scribing also requires expensive laser equipment and protective equipment used by the operator. Moreover, it has been reported that laser scribes reduce the strength of the wafer because during the singulation, the cone scatters the crystal structure along the periphery of the wafer. It is desirable to have a method of dividing a wafer from a semiconductor wafer, which can increase the number of semiconductor wafers on the wafer; providing a more uniform sentence 151883. Doc 201126648 segmentation; reducing the time to perform segmentation [embodiment]: and has a narrower scribe line. For the sake of brevity and clarity, the elements in the figures are not necessarily to scale, and the same reference numerals are used in the different figures. In addition, the description of well-known steps and elements is omitted for ease of <Desc/Clms Page number>>>""" . However, it will be understood by those skilled in the art that due to the diffusion and activation of the dopant, the perimeter of the modified domain may not be generally straight, and its angularity may not be precise, as will be appreciated by those skilled in the art. It is said that the use of the word near the ground "substantially" means that the component value of the parameter is expected to be close to the sigh value or the set position. However, as is well known in the art, there will always be a slight difference that prevents the value or position from being strictly the same as the set value. In the art, the difference between the ideal goal of the same as described is 'acceptable by at least 10% )% (and as much as half of the semiconductor doping concentration is 20% (20%)) as a reasonable difference. . 1 is a simplified plan view illustrating a semiconductor wafer 10 having a plurality of semiconductor wafers, such as wafers 12, 14, and 16, formed on the semiconductor wafer 10. The wafers 12, 14, and 16 are spaced apart from each other on the wafer 10, which form dividing lines, such as the dividing lines 13 and 15, in the interval. As is known in the art, all of the plurality of semiconductor wafers are generally separated from each other on all sides by forming dividing lines, such as lines 13 and 15, by regions. Figure 2 shows the figure taken along the line 2_2! An enlarged cross section of the wafer 1〇 151883. Doc 201126648 face part. For purposes of clarity of the drawings and the description thereof, the illustrated stub 2_2 only crosses portions of the wafer 12 and wafers 14 and 16. The wafers 12, 14, and 16 can be any type of semiconductor wafer including a diode, a longitudinal transistor, a lateral transistor, or an integrated circuit including various different types of semiconductor devices. Semiconductor wafers 12, 14, and 16 generally include a semiconductor substrate 18' which may have doped regions formed within substrate 18 to form active and passive portions of the semiconductor wafer. The cross-sectional face shown in Figure 2 is taken along the contact pads 24 of each of the wafers 12, 14, and 16. Contact pads 24 are typically metallic, formed on a semiconductor wafer to provide electrical contact between the semiconductor wafer and external components of the semiconductor wafer. For example, the contact pads 24 can be formed to receive bond wires that can be subsequently attached to the pads 24, or can be formed to receive solder balls or other types of interconnect structures that can be subsequently attached to the pads 24. The substrate 18 includes a block substrate 19 having an epitaxial layer formed on the surface of the block substrate 19. A portion of the epitaxial layer 2 can be doped to form a doped region 21' which is used to form a semiconductor wafer.主动 4, or 16 active and passive parts. Layer 20 and/or region 21 may be omitted in some implementations or may be in other regions of wafer 12, 14, or 16. Typically, a dielectric 23 is formed on the top surface of the substrate 18 to isolate the pads 24 from other portions of the individual semiconductor wafers and to insulate each pad from adjacent semiconductor wafers. The dielectric 23 is typically a thin layer of ruthenium dioxide formed on the surface of the substrate 18. Contact pad 24 is generally metallic, with a portion of contact pad 24 in electrical contact with substrate 18 and another portion of which is formed on the adjacent portion of dielectric 23. After forming wafers 12, 14, and 16 including metal contacts and associated interlayer dielectrics (not shown), typically, at 151883. Doc 201126648 Forms a dielectric 26 on all of the plurality of semiconductor wafers to act as a passivation layer with respect to the wafer 1 and with respect to each individual semiconductor wafer 12, 14, and 16. Dielectric 26 is typically formed over the entire surface of wafer 10, such as by blanket dielectric precipitation, and in some embodiments can be formed under contact pads 24. The thickness of the dielectric 26 is generally greater than the thickness of the dielectric. FIG. 3 illustrates the cross-sectional portion of the wafer 10 of FIG. 2 at a subsequent stage in the process of dividing the wafers 12, 14, and 16 from the wafer 10. After forming a passivation layer of dielectric 26, a mask 32, shown by dashed lines, can be applied to the surface of substrate 18 and patterned to form openings that are exposed to cover each of the crucibles 24 and Some portions of the dielectric on the portions of the wafer 1(), on portions of the wafer 1G, are formed with dividing lines such as dividing lines 13 and 15. Thereafter, passing through the mask 32 The openings are etched with dielectrics % and 23 to expose the pads 24 and the surface of the substrate 18 thereunder. Openings through the dielectric are formed in regions forming the dividing lines such as lines 13 and 15, which function to divide openings 28 and 29 The opening formed by the dielectric % overlying the crucible 24 acts as a contact opening. The etching process is preferably performed using a process that selectively etches the dielectric faster than etching the metal. The dielectric is generally at least ten (10) times faster than its surnamed metal. The material is preferably Shi Xi, and the material used for the dielectric 26 is preferably dioxin or nitriding. The material of the dielectric 26 may also be other dielectric materials 'which can be (four) but not at the same time The material of the button pad 24, such as the metal of the polyimide film 24, functions as an etch stop layer that prevents the exposed portion of the pad μ from being removed by (d). In a preferred embodiment, a gas based 151883 is used. Doc 201126648 Anisotropic reactive ion etching process. After the opening through the dielectric 26 is formed, the mask 32 is removed and the substrate 18 is thinned to remove material from the bottom surface 17 of the substrate 18 and reduce the thickness of the substrate 18. Generally, substrate 18 is thinned to a thickness of no greater than about one hundred to two hundred (100 to 200) microns. Such thinning programs are well known to those skilled in the art. After the wafer crucible is thinned, the bottom surface of the wafer 1 including the bottom surface π of the substrate 18 can be metallized with the metal layer 27. In some embodiments, this metallization step can be omitted. Subsequently, the wafer 1 is typically attached to a conveyor belt or carrier tape 3 which assists in supporting the plurality of wafers after dividing the plurality of wafers. Such carrier tapes are well known to those skilled in the art. Fig. 4 shows the wafer 10 on a subsequent stage in the process of dividing the semiconductor wafers I, 14, and 16 from the wafer 1 . The substrate 18 is etched through the split openings 28 and 29 formed in the dielectric 26. The etching process extends the split openings 28 and 29 from the top surface of the substrate 18 and completely through the substrate 18. The etching process is typically performed using a chemical action that selectively etches germanium at a much higher rate than the dielectric or metal. The etching process is generally at least fifty (5) times faster than the etched dielectric or metal, and preferably one hundred (100) times faster. Typically, a deep reactive ion etching system using a combination of isotropic and anisotropic etching conditions is used to etch openings 28 and 29 that completely penetrate the bottom surface of substrate 18 from the top surface of substrate 18. In a preferred embodiment, a process commonly referred to as a Bosch process is used to anisotropically etch the split openings 28 and 29 through the substrate 18. In one example, wafer 10 is 151883 in an Alcatel deep reactive ion etching system. Doc 201126648 Etching using the Bosch process. The widths of the split openings 28 and 29 are generally five to ten (5, micrometers. - such a width; i to ensure that the opening 29 can be formed completely through the base (four), and the width is further narrow enough to be able to be short An opening is formed in the closed compartment. Typically, openings 28 and 29 can be formed through the substrate i 8 in a time interval of approximately fifteen to thirty (15 to 3 () minutes. Because of the wafer i The dividing lines are formed at the same time, so that all the dividing lines spanning the wafer 1 形成 can be formed in the same time interval of approximately fifteen to thirty 〇 5 to 30) minutes. Thereafter, the wafer 10 is supported by the carrier tape 3 while the wafer is carried to a selection and placement device 35 by which each individual wafer can be removed from the wafer. Typically, the upwardly pushing each divided wafer set 35 has a pedestal or other tool, such as a wafer 12, to release it from the carrier tape 30, and a split wafer is removed straight up to a vacuum pick up (not shown), it will. During the selection and placement process, a portion of the thin metal underlayer 27 underlying the openings 28 and 29 breaks and remains in the enlarged cross-sectional portion of the semiconductor wafers 42, 44, and 46 of the semiconductor. The wafer is formed on wafer 1 and is an alternative embodiment of wafers 12, 14, and 16 illustrated in the description of FIG. Wafers 42, 44, and 46 are shown after the formation of dielectric 23 on the top surface of substrate 18 and in the fabrication state prior to formation of pad 24 (Fig. 1). These wafers 42, 44, and 46 are similar to wafers 12, 14, and 16 except that the wafers 42, 44' and 46 each have respective isolation trenches 5, 54, and 58 that are similar to the wafers 12, 14, and 16. The wafer is wrapped around it and isolated from adjacent wafers. Grooves 5〇, 54, and Μ 151883. Doc 201126648 is generally formed near the outer periphery of each wafer. The grooves 5, 54, and 58 are formed to extend a first distance from the top surface of the substrate 18 into the block substrate 19. Each of the trenches 50, 54, and 58 is generally formed as an opening into the substrate 19 having a dielectric formed on the sidewalls of the opening, and is typically formed of a dielectric or other material such as a stone or polycrystalline Shi Xilai filled. For example, the trenches 5 〇 may include a cerium oxide dielectric 5 i on the sidewalls of the trench openings and may be filled with polycrystalline dies 52. Similarly, the trenches 54 and 58 are each included on the sidewalls of the trench opening. The cerium oxide dielectrics 55 and 59 are filled with polycrystalline germanium 56 and 60. A dividing line 43 is formed between the grooves 50 and 54, and a dividing line 45 is formed between the grooves 5A and 58. The grooves 50 and 54 are formed adjacent to the dividing line 43, and the grooves 50 and 58 are formed adjacent to the dividing line 45. Methods for forming trenches 50, 54, and 58 are well known to those skilled in the art. It should be noted that the trenches 50 and 54 are for illustrative purposes only and can be any number of isolated trenches or trenches of various shapes and sizes, or a combination thereof. The wafer 1 一个 on a subsequent stage in the process of singulating the semiconductor wafers 42, 44, and 46 from the wafer 丨 0 is shown in accordance with the present invention. The other portions of the wafers 42, 44, and 46 are formed after the trenches 5, 54, and 58 are formed, including: forming the contact pads 24' and forming the dielectrics 26 covering the wafers 42, 44, and 46. Dielectric 26 also typically covers other portions of wafer 1 including portions of substrate 18 to be formed as secants 43 and 45. Thereafter, the mask 32 is applied and patterned to expose the underlying dielectric 26 to be formed at the dividing line and the contact opening. Dielectric 26 is etched through openings in mask 32 to expose the underlying pads 24 and the surface of substrate 18. The opening formed through the dielectric 26 in the region where the dividing lines (such as lines 43 and 45) are to be formed functions as a segmentation 151883. Doc •10· 201126648 Openings 47 and 48. The process of forming the openings 47 and 48 through the dielectrics 23 and 26 is substantially the same as the process for opening the openings 28 and 29 (Fig. 3) in the dielectrics 23 and 26. Openings 47 and 48 are preferably formed such that dielectrics 51, 55, and 59 on the sidewalls of respective trenches 50, 54, and 58 are not located under openings 47 and 48 such that these dielectrics are subsequently formed The dividing line "and the operation of the crucible will not be affected. After forming the openings 47 and 48 through the dielectric 26, the mask 32 is removed, and the substrate 18 is thinned and metallized with the metal layer 27, as This has been previously described in the description of Figure 3. In some embodiments, this step of metallization can be omitted. After metallization, wafer 1 is typically attached to carrier tape 30. Figure 7 shows The wafer 10 on a subsequent stage in the process of dividing the semiconductor wafers 42, 44, and 46 in the wafer 10. The substrate 18 is etched through the split openings 47 and 48 formed in the dielectric 26. The etching process allows the split opening The extensions 47 and 48 extend completely through the substrate 18 from the top surface of the substrate 18. The openings 47 and 48 are typically at least Q 5 microns from the dielectric 51 '55' and 59. (d) The process is generally isotropic (four) engraved 'before Higher than (iv) dielectric selectivity of the dielectric or metal (4), the rate - Generally, the rate of _ dielectric # or metal is at least fifty (50) times faster, and preferably faster than __ hundred (10) times. Because the dielectric on the sidewalls of the trench protects the substrate 18, It is possible to use an isotropic etch. The amount of etching of the isotropic etch is high compared to the amount of etch obtained using the Bosch process or the limited use of the B〇seh process. However, the isotropic etch Typically, some portions of the substrate 19 located below the trenches M, 54, and 58 are cut from the lower portion, typically using fluorine chemistry 151883. Doc -11 - 201126648 The downstream etching of the effect is used to completely penetrate the openings 28 and 29' from the top surface of the substrate 18 from the top surface of the substrate 18 and expose a portion of the layer 27 under the openings 28 and 29. In one example, the wafer 1 is etched using a deep reactive ion etching system that uses a fully isotropic etch, which can be purchased from a variety of different manufacturers, including a system FL 33716 Purchased from PlasmaTherm, LLC at 10050 16th Street North St_ Petersburg. In other embodiments, an isotropic etch can be used for most etches, while an anisotropic etch can be used for another portion of the etch (B〇sch process). For example, isotropic lithography can be used until the depths of openings 28 and 29 are substantially the same depth as trenches 50, 54, and 58, and anisotropic etching can then be used to prevent trenches from being cut from the lower portion. 5 〇, 5 4, and 5 8. The width of the split openings 47 and 48 is generally about the same as the width of the openings 28 and 29. The wafers 42, 44, and 46 can be removed from the tape 30 in a manner similar to the removal of the wafers 12, 14, and 16. In another embodiment, the grooves 50 and 58 may be separated by a first distance that is sufficient to allow a standard dicing tool or saw to extend through the opening 48. Thus, the portion of layer 27 located below opening 48 can be severed by a dicing tool or wafer saw; or the wafer 1 以下 below the openings 47 and 48 can be broken along the openings 47 and 48 by bending on the drum. Separate; or remove with other techniques such as laser scribing, and the like. The grooves 5A and 54 may have similar intervals' which help to cut a portion of the underlying layer 27 in a similar manner. For the method of dicing layer 27 using a dicing tool, layer 27 can be broken along the path of the dicing tool to complete the separation. 151883. Doc •12· 201126648, wafers a, 44, and 46 can be removed from strip 3 by standard selection and placement techniques. These methods facilitate separation and singulation of the wafers 42, 44, 46. Alternatively, when the depths of the openings 47 and 48 reach the bottom of the trenches (4), Μ, and 58 or just past the bottom of the trench, each can be terminated. Etching to the same degree °. Thereafter, the exposed portion of the substrate 19 may be diced with a dicing tool or cut with wafer ore to complete the separation of the wafer or other techniques such as mis-cutting, etc., to remove the wafer. The metal cutting technique can be extended to perform metal cutting through the metal layer 27. The dicing technique will break the layer 27 as the material of the substrate 19 breaks along the path formed by the dicing tool. Those skilled in the art will appreciate that the use of trenches 5, ..., and 58 to divide the wafer will result in wafers 42 having smooth sidewalls, material, and 46' dielectric sidewalls and wafers through the trenches. The external components are insulated. The dielectric forms a dielectric material on the sidewalls of the wafer. The insulation provided by the trench dielectric can reduce leakage current between the wafer and external components. This structure also increases the breakdown voltage of the wafer. The use of the trenches 50, 54, and 58 can also increase the strength of the wafer compared to the clock-split wafer. Referring again to the cooking technique used to extend the openings 47 and 48 into the substrate 19, those skilled in the art will appreciate that isotropic moments are faster than anisotropic The isotropic surname is used to quickly remove the material of the opening until the openings 47 and 48 extend as deep as the grooves 50, 54, and 58. Subsequently, the anisotropic residual is used to prevent the grooves 50, 54, and 58 from being cut from the lower portion. Therefore, the anisotropic characterization immediately after the use of isotropic tentacles provides high yield and good 151883. The lateral control of doc 13 201126648 is even true for the openings 48 and 48 that are deeper than the grooves 5〇, 54, and 58. Figure 8 illustrates a stage in an exemplary embodiment of another alternative method of segmenting semiconductor wafers η, 72, and 73 formed on a semiconductor wafer. Figure 8 shows an enlarged cross-sectional portion of the wafer 7173 after the formation of the dielectric 23 on the top surface of the substrate 18 and in the manufacturing state prior to the formation of the pad 24 (Figure 2). These wafers 71-73 are similar to wafers 42, 44, and 46 except that the wafers 71-73 have a single isolation trench 79 surrounding each wafer on the wafer. As will be seen hereinafter, an example of a method of singulating a semiconductor wafer from a wafer includes: providing a semiconductor item, such as a wafer, having a semiconductor substrate, such as substrate 18, and having a plurality of semiconductor wafers formed on a semiconductor substrate, wherein the semiconductor wafers are separated from one another by portions of the semiconductor wafer, and wherein portions of the semiconductor wafer are at locations where division lines, such as lines 13 and 15, are to be formed; Forming trenches, such as trenches 79, on portions of the semiconductor wafer, wherein the trenches w around each of a plurality of semiconductor wafers, including forming a dielectric layer on sidewalls of the trenches, and Forming a fill material within the trench, and the fill material abuts a dielectric layer on the sidewall; forming a passivation layer covering portions of the plurality of semiconductor wafers, such as layer 26; etching through the passivation layer and any first opening of the underlying layer , for example, an opening 82 to expose at least the filling material of the trench; and etching a second opening such as an opening Μ that penetrates the filling material and Through the semiconductor substrate positioned below the filling material is any part such that the second opening extends from the surface of the semiconductor wafer of the Ends 151,883. Doc 201126648 Full penetration through the semiconductor substrate 'where the etching of the second opening is performed through the first opening. Another embodiment of the method further includes forming a trench opening that extends a first distance from a surface of the semiconductor substrate into the semiconductor substrate with a first portion of the semiconductor substrate underlying the trench opening, and wherein the trench opening has sidewalls and a bottom portion; a dielectric layer is formed on the sidewall of the trench opening and the bottom of the trench opening, and a portion of the trench opening is left between the sidewalls as an unused space; and the dielectric on the bottom of the trench opening is removed; And the dielectric layer adjoining the sidewalls of the trench fills the unused space of the trench opening with a filling material. The formation of the trench 79 is similar to that of the trench 50, 54, or 58 except that the trench 79 extends around the perimeter of each of the wafers 71-73 and the perimeter of any other wafer formed on the wafer ίο. One, which has been described in the description of Figure 5-7. The trench 79 is formed to include a dielectric f pad 8 such as cerium oxide on the sidewalls and bottom of the trench 79. In the preferred embodiment, the bottom of dielectric liner 80 is removed such that the bottom of trench 79 is opened, as shown by dashed line 84. One example method of removing the bottom of the liner 8 includes applying a mask 85 having an opening that exposes the trench 79, and performing an anisotropic etch, such as spacer etching (spacer 仏), the etch through liner The bottom of the 80. The dielectric on the crucible can be selectively etched to prevent damage to portions of the substrate 18 that are located under the trenches 79. Generally, the mask 85 is removed after the bottom of the pad 80 is removed. After the bottom of the trench 79 is removed, the remaining opening of the trench 79 is filled with a fill material 81. Filler material 8 1 is typically a germanium based material such as polysilicon to facilitate subsequent process steps 151883. Doc 15 201126648, as will be seen later, will be appreciated by those skilled in the art, any of the wafers 71-73 may also have other trenches inside the wafer, such as trenches 78, and form these The process operations that can be used with the trenches are similar to those used to form the trenches 79. Depending on the function to be provided, the trenches 78 may hold the bottom oxide ' or cause the bottom oxide to be removed. For example, the trenches 78 may be filled with a plurality of turns and provided with a low impedance substrate contact or back such as to the metal layer 27 (not shown in Figure 8) or to another contact on the bottom or back side of the substrate 18. Contact. However, the preferred embodiment of trench 78 does not have a removed bottom' and trench 78 is preferably internal to the wafer and does not surround the outer perimeter of the wafer. Thus, the trenches 79 can be formed simultaneously with the trenches 78, or other similar trenches, thereby reducing manufacturing costs. As will be appreciated by those skilled in the art, wafers 71-73 can have a variety of different active or passive components formed on or within substrate 18. The grooves 79 are formed in the dividing lines 76 and 77, and preferably in the middle of the dividing lines such that the middle of the grooves 79 is approximately the middle of the dividing line. As will be seen later, the segmentation occurs approximately through the middle of the groove 7.9. Figure 9 shows wafer 1 一个 on a subsequent stage in an exemplary method of singulating semiconductor wafers 71-73 from wafer 1 . The "forming other portions of the wafers 71-73" after forming the trenches 79 include forming the contact pads 24 and forming the dielectrics 26 covering the wafers 71-73. The dielectric 26 also covers the other portions of the wafer 1 'which includes portions of the substrate 18 from which the dividing lines 77 and 76 are to be formed. Thereafter, a mask 87 is applied and patterned to expose the underlying dielectric 26 to be formed at the dividing lines 76 and 77' and the contact openings. The mask 87 is similar to 131883 in Figure 3. Doc -16 - 201126648 The illustrated mask 32; however, the position of the mask 87 is usually different. The openings in the mask where the secant lines 76 and 77 are to be formed are also above the grooves 79. The dielectric 26 is etched through the opening in the mask to expose the true charge material 81 in the underlying trench 79. The money also exposes the underlying 塾μ. The openings formed through the dielectric 26 in the region where the dividing lines ' such as the lines 76 and 77 are to be formed function as the split openings 82 and 83. The process used to pass through the dielectric openings 82 and 83 (four) is substantially the same as the process used to form openings 28 and 29 (Fig. 3) in dielectrics 23 and 26. The openings 82 and 83 are typically formed such that the dielectric liner 8 on the sidewalls of the respective trench 79 is located below the openings "and". However, as long as the material 81 is exposed, the dielectric liner 80 need not be exposed. Typically, because it is a cross-sectional view, the openings are shown as two openings, although the openings 83 are two portions of a single opening around the wafers 71-73. After forming the openings 82 and 83 through the dielectric 26, the mask 87 is removed, as shown by the dashed lines, and the substrate 8 is thinned as shown by the dashed line 86. The thinning removes most of the substrate 18 under the trenches 79. The substrate 18 is generally not thinned all the way up to the bottom of the trench 79 because the dielectric material of the dielectric liner 8 may damage the tool used to thin the wafer 10 or may cause scratching Round 1〇. Preferably, substrate 18 is thinned 'until trench 79 is about two to five (2-5) microns from the bottom of substrate 18. "In some embodiments, substrate 18 can be thinned" until trenches 79 are exposed. The bottom of the bottom. Thereafter, the bottom surface of the substrate 18 is metallized with a metal layer 27, as previously explained in the description of FIG. This metallization step can be omitted in some embodiments. Subsequently, crystal 151883. Doc • 17· 201126648 The circle 10 is typically connected to a common carrier substrate or a common carrier, such as carrier tape 30. Figure 10 shows wafer 10 on a subsequent stage in an example of an embodiment of a method of dividing wafer 71_73 from wafer 10. A second opening is formed through the fill material 81 to form dividing lines 76 and 77 through the substrate 18. Similar to the silver engraving described in the description of Fig. 4, preferably, the dielectric is used as a mask to etch the substrate 18 through the split openings 82 and 83. The etching process forms an opening through the material 81. Typically, the etch removes substantially all of the material 81 to extend the dividing lines 76 and 77 which extend completely through the fill material 81 of the trench 79 from the top surface of the substrate 18. The etching process is typically an isotropic etch that selectively etches germanium at a much higher rate than the etched dielectric or metal, which is typically at least fifty (5) times faster than the rate of etching the dielectric or metal. And preferably one hundred (100) times faster. Since the etching step is selective for the germanium on the dielectric, the filling material 81 is removed without etching the dielectric liner 8 on the sidewalls of the trench 79 (^, therefore, the trench The dielectric liner 80 on the sidewalls of the trenches 79 protects the turns of the substrate 8 from isotropic etching. Compared to the amount of etching obtained using the Bosch process or the limited use of 5〇3 (11 process) The isotropic etch is much more etched. The isotropic etch process etches through the fill material 81 and any portion of the substrate 18 underlying the trench 79. Thus, isotropic etch quickly etches through the trench The groove 79 and any portion of the substrate 18 underneath it, thereby dividing the wafer 71-73. Rapid etching improves throughput and reduces manufacturing costs. Those skilled in the art will appreciate the '矽 in the fill material 81' The base material also reduces stress on the material of the dielectric liner 80 and the substrate 19. 151883. Doc 201126648 Dividing the wafers 71-73 along the dividing lines 76 and 77 of the through-groove 79 results in the dividing line occupying only a small space on the semiconductor wafer. For example, the width of the trenches 79 comprising the filler material 81 is typically only about three (3) microns wide. Thus, the scribe lines 76 and 77 can be only about three microns wide, rather than one hundred microns wide in other wafer singulation methods such as dicing or wafer sawing methods. It will be apparent to those skilled in the art that the step of thinning the wafer crucible can be omitted and the etch of material 81 can continue until openings 82 and 83 extend through wafer 10. As illustrated in the description of Fig. 4, τ ice: 3⁄4 evaluates π double straight to break any portion of the metal layer 27 under the openings 82 and 83 to complete the division of the wafers 71-73. Those skilled in the art will appreciate that other methods can be used to sever the metal layer 27 within the dividing lines 76 and 77. For example, the gold layer 27 can be diced along the bottom side of the layer 27 before the strip is applied, so that when the pick and place action is performed, the layer 27 will be severed along this line. Alternatively, the back side of the second layer 2 may be located at the portion of (4) below the dividing lines 76 and 77 before the application of the tape. The last name of the layer 27 is divided into layers 27. Another method of cutting the layer 27 is to blow a jet stream onto a portion of the strip 3G located below the wafer. The air will cause the belt 30 to extend upward and cut the layer 27, i.e., cut in the lower portion of the (four) dividing lines 76 and 77. In addition, the ring 肱 , ^ 3 甩 % is the front side of the second carrier tape wafer that will be unbroken. The belt 30 can then be removed. The step of removing the strip 30 breaks the layer, i.e., the layer portion (four) located below the dividing lines 76 and 77. Any of the alternative methods described herein for any of the alternative methods of cutting the layer 27. Solid can be used for 15i883. Doc -19- 201126648 Wafer diagram: shows one of the stages in the method of dividing the semiconductor, and another alternative method of 16 which has been described. An example of a method of dividing a semiconductor crystal from a semiconductor wafer, as will be seen below, includes: providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom surface, And a plurality of material conductors W, wherein (4) W is formed on the semi-recorded bottom and separated from each other by portions of the semiconductor wafer at which the dividing lines are to be formed; forming a split mask layer covering a plurality of semiconductor wafers, such as A1N 93, forming an opening through the split mask layer; forming an opening through the underlying layer and exposing a portion of the surface of the semiconductor substrate; and using the opening in the split mask layer as a mask while simultaneously engraving the first opening to the semiconductor The exposed portion of the substrate surface extends and extends completely through the semiconductor wafer. Another embodiment of the method further includes: connecting the semiconductor wafer to the carrier tape prior to using the opening in the split mask layer as a mask; and further comprising using the selection and placement device to separate the carrier tape, and A semiconductor wafer of a plurality of semiconductor wafers is separated from other wafers of a plurality of semiconductor wafers. Another embodiment of the method includes: forming a split mask layer, the material being a metal compound, aluminum nitride, nitride, metal-antimony compound, titanium telluride, aluminum telluride, polymer, or polyimine One of the layers. As illustrated in the description of Fig. 2, the wafers 12, 14, and 16 are shown in a fabricated state after the dielectric 23 is formed on the top surface of the substrate 18 and then the pads 24 and the dielectric 26 are subsequently formed. After forming the dielectric 26, a split mask is formed to 151883. Doc -20- 201126648 promotes the formation of openings through the substrate 18 without the underlying layers, such as portions of the dielectric 26. In a preferred embodiment, the split mask is formed from aluminum nitride (A1N). In the preferred embodiment, the "layer" is formed at least on the dielectric 26. In general, the layer 91 is applied to cover all of the wafer 10. Figure 12 shows the cross-section of the wafer 10 of Figure 11. The cross-section portion is at a subsequent stage in the example of a preferred embodiment of the method of dividing the wafers 12, 14, and 16 from the wafer 1. After forming the A1N layer 91, the mask 32 can be applied to the substrate 18. The surface, and patterned to form openings that expose portions of the dielectric 26 that cover each of the pads 24 and also cover the formation of the dividing lines, such as the wafers at the dividing lines 13 and 15 Some portions. To form the mask 32, a photographic masking material is applied over the wafer 1 and subsequently exposed to light, such as ultraviolet light, to alter the chemical composition of the exposed portion of the masking material, To form a mask 32 having an opening that covers the location where the dividing line is to be formed and where the pad 24 is to be formed. The unexposed portion of the masking material is then removed using the developer, thereby leaving an opening 28 and a mask 32 of 29, the openings 28 and 29 are covered At positions where the respective dividing lines 13 and 15 are to be formed, it has been found that a developer based on ammonium hydroxide can also be used to produce a developer that removes a portion of the A1N layer 91 below the unexposed portion of the masking material. The removed portion of the layer ... is shown with a broken line 92, and the remaining portion of the layer 91 is identified as AiN %. As will be seen hereinafter, the A1N 93 acts as a split mask. Figure 13 shows Figure 2 A cross-sectional portion of the wafer 10 'an example of an alternative embodiment of the method of dividing the wafers 12, M, and 16 from the wafer 1 151883. Doc •21 · 201126648 Another sub-stage in the sub. Dielectrics 26 and 23 are etched through openings in mask 32 and A1N 93 to expose the underlying pads 24 and the surface of substrate 丄8. Openings penetrating the A1N 93 and the dielectrics 26 and 23 in the regions where the dividing lines are to be formed, such as the lines 13 and 15, function as the dividing openings 28 and 29. The opening formed through the dielectric 26 covering the crucible 24 acts as a contact opening. The etching process is preferably performed wherein the process used selectively etches a germanium based dielectric such as cerium oxide or nitriding faster than the metal. The etching process etches the germanium-based dielectric generally at least ten (10) times faster than the etched metal. The metal of the crucible 24 acts as an etch stop layer which prevents the exposed portion of the pad 24 from being removed by etching. In a preferred embodiment, an anisotropic reactive ion etching using a fluorine group is used as explained above. After the openings through the dielectrics 26 and 23 are formed, as shown by the dashed lines, the mask 32 is typically removed. As shown by dashed line 86, substrate 18 is generally thinned to remove material from the bottom surface of substrate 18 and reduce the occupancy of substrate 18. Generally, the substrate 18 is thinned to a thickness of no greater than about twenty-five to four hundred (25 to 400) microns, and preferably between about fifty and two hundred and fifty (50-250) microns. . Such thinning programs are well known to those skilled in the art. After the wafer 10 is thinned, the metal layer 27 can be used to metallize the back side of the wafer. In some embodiments, this metallization step can be omitted. Subsequently, the wafer cassette is typically attached to a conveyor belt or carrier tape 30 which facilitates supporting the plurality of wafers after the plurality of wafers have been divided. Figure 14 shows a wafer 15I883 on a subsequent stage in an exemplary embodiment of an alternative method of singulating semiconductor wafers I], 14, and 16 from a wafer. Doc •22· 201126648 10. The AIN 93 is used as a mask, and the base 18 of the split openings 28 and 29 is pierced with a button. The A1N 93 protects the dielectric 26 from etching. The β A1N 93 can have a thickness of about fifty to three hundred (50-300) angstroms and still protect the dielectric 26. Preferably, the A1N 93 has a thickness of about two hundred (2 angstroms) angstroms. The etching process causes the split openings 28 and 29 to extend from the top surface of the substrate 18 and completely penetrate the substrate 18. As with the Bosch process illustrated in the description of Figure 4, the etching process is typically performed using chemistry that selectively etches germanium at a much higher rate than the dielectric or metal. Thereafter, as illustrated in the description of FIG. 4, the wafers 12, 14, and 16° can be removed from the strip 3 because the A1N 93 is a dielectric which can be left on the wafers 12, 14, and 16. In other embodiments, A1N 93 may be removed after penetration through substrate 18, such as by etching with a developer; however, this requires additional processing steps. The use of a light masking developer to remove the exposed portions of layer 91 saves processing steps, thereby reducing manufacturing costs. Using A1N% as a mask protects the dielectric 26 from the effects of etching operations. Those skilled in the art will appreciate that 'A1N 93 can be used as a split mask to protect dielectric 26 in any of the segmentation methods described herein, including the description of Figures 5-7. The illustrated method 'such as the method of tf in Fig. 15' and A1N 93 can also be used for the method illustrated in the description of Fig. 8-10. In other embodiments, the split mask can be formed from materials other than A1N. These other materials used to separate the mask are those that are not substantially used to etch the germanium of the substrate 18. . Because it is used for 151883. Doc •23- 201126648 The money engraved base of the money engraved button is faster than the metal in the meal, so metal compounds can be used as the material for forming the split mask. Examples of such metal compounds include A1N, titanium nitride, titanium oxide, titanium oxynitride, and other metal compounds. In the example using a metal compound other than A1N, the metal compound layer can be applied similarly to the layer 91. The mask 3 2 can then be used to pattern the metal compound layer to form an opening in the metal compound. Thereafter, the mask 32 can be removed and the remainder of the metal compound is sufficient to protect the underlying layer, such as dielectric 26, during the engraving of the substrate 18. The metal compound may be left on the wafer to be subsequently divided, or may be removed before the division is completed, such as before the wafer is separated from the tape. Alternatively, a ruthenium-metal compound can be used to form the split mask because the metal in the metal-germanium compound prevents etching from continuing into the metal-germanium material. Some examples of ruthenium-metal compounds include metal halides such as titanium telluride and cobalt telluride. For the embodiment of the ruthenium metal compound, a ruthenium-metal compound layer can be formed and patterned similarly to the example of the metal compound. However, the metal ruthenium compound is generally a conductor and must therefore be removed from the wafer, such as to remove the metal-dream compound prior to completing the dicing of the wafer from the tape. Moreover, the polymer can be used to separate the mask. An example of a suitable polymer is polyimine. Other well known polymers can also be used. Similar to the metal compound, the polymer can be patterned and subsequently removed or left on the wafer. Figure 16 shows an example implementation of an alternative method of segmenting semiconductor wafers 12, 14, and 16 that has been illustrated in the description of the figure. Doc -24· 201126648 One stage in the way. As will be seen hereinafter, an example of a method of singulating a semiconductor wafer from a semiconductor wafer includes: providing a semiconductor wafer having a semiconductor substrate and having a plurality of semiconductor wafers on the semiconductor substrate Forming, and separating from each other by portions of the semiconductor substrate at which the dividing lines are to be formed; forming the dividing lines from the first surface of the semiconductor substrate in a dividing line opening that penetrates through portions of the I-conductor substrate Opening, thereby creating a space between a plurality of semiconductor wafers that form sidewalls of the semiconductor wafer, wherein the top surface of the semiconductor wafer has a greater width than the bottom surface of the semiconductor wafer. In another embodiment, the method further includes etching the split line opening to include forming a top surface width of the wafer that is about two to ten (2-10) microns larger than the bottom surface width. Another alternative method includes using an anisotropic etch to etch into the split line opening of the semiconductor substrate at a first distance; and etching the split line opening using an isotropic etch to extend the split line opening to The second distance also increases the width of the split line opening. As will be seen hereinafter, the segmentation method forms angled sidewalls with respect to wafers 12, 14, and 16, such that the lateral width of the wafer is greater at the top of the wafer than at the bottom of the wafer. Wafer 10 and wafers 12, 14 and 16' are shown in the fabrication state after etching through dielectrics 26 and 23 to expose substrate 18 and pad 24 as illustrated in the description of FIG. Alternatively, A1N 93 can be used as a mask for subsequent operations, as illustrated in the figure "-The description of the bucket. 151883. Doc -25- 201126648 Subsequently, in order to expose the surface of the substrate 18, the substrate 18 and any exposed germanium 24 are inscribed by an isotropic process of etch, which is compared to an etched dielectric or The metal selectively etches germanium at a much higher rate, typically at a rate that is at least fifty (50) times faster than etching the dielectric or metal, and preferably at least one hundred (1) times faster, As explained in the description of the figure. The etching process is performed to extend the openings 28 and 29 into the substrate 18 to the 疋' wood, and the sample extends laterally across the width of the opening while also extending its depth to form the opening 1 基底 in the substrate 8. Because the process is used to form angled sidewalls with respect to wafers 12, 14, and 16, a plurality of isotropic etches will be used to incrementally increase the width of openings 28 and 29 while the depth of the opening extends into substrate 18. The isotropic etch is terminated after the width of the opening 1 大 is greater than the width of the openings 28 and 29 in the dielectrics 23 and 26. Thereafter, the carbon-based polymer 1〇1 is applied to a portion of the substrate 18 that is exposed in the opening 100. Figure π shows a subsequent stage of the phase illustrated in the description of Figure 16. An anisotropic etch is used to remove the portion of the polymer 1〇1 on the bottom of the opening 1 while leaving the portion of the polymer 1 on the sidewalls of the opening 100. Figure 18 shows a subsequent stage of the stage illustrated in the description of circle 17 using an isotropic etching process to etch the surface exposed to the substrate 18 within the opening 1 and any exposed pads 24, similar to A description of the description of FIG. The isotropic etch again laterally extends the width of the split openings 28 and 29 while also extending its depth to form the opening 104 in the substrate 18. After the width of the opening 104 is greater than the width of the opening ι, the isotropic etching is typically terminated so that the width of the opening varies with depth 151883. Doc •26· 201126648 Adding and widening The portion of the polymer l〇i that is left on the side wall of the opening 100 protects the side walls of the opening 100 to prevent the etching of the opening 1〇4 from affecting the width of the opening 1〇〇. During etching of the opening 104, substantially all of the polymer is removed from the sidewalls of the opening 1 . Thereafter, a carbon-based polymer 1〇5 similar to the polymer 101 is applied to a portion of the substrate 18 exposed in the opening 104. During the formation of the polymer 1〇5, the operation usually once again forms a polymer ι〇 on the side wall of the opening 1〇〇. Figure 19 does not show another subsequent stage of the stage illustrated in the description of Figure 18. Another anisotropic etch is used to remove portions of the polymer 105 on the bottom of the opening 1〇4 while leaving a portion of the polymer 105 on the sidewalls of the opening 1〇4. This process step is similar to the steps explained in the description of FIG. Figure 20 shows a repeatable etch sequence until the dividing lines 13 and 15 are completely through the substrate 18. The anisotropic etch can be repeated to form openings, such as openings 108 and 112, to form a polymer on the sidewalls of the opening, and to remove polymer from the bottom of the opening while leaving a portion of the polymer on the sidewalls (such as polymers 109 and 113) The sequence of operations is until openings 28 and 29 extend through substrate W to form dividing lines 13 and 15 that extend completely through substrate 18. After the final isotropic etch, such as etching to form the opening 丨12, the polymer is typically not precipitated because the substrate 18 is generally not required for subsequent operations. Although the polymers i 〇 1 ' 1 〇 5, and 1 〇 9 are shown on the sidewalls of their respective openings 100, 104, and 1 〇 8, after all operations are completed, those skilled in the art will appreciate The final isotropic etching step used to form the opening 112 substantially removes these polymers from the sidewalls of their respective openings. Therefore, these polymers are for clarity 151883. The purpose of doc -27· 201126648 is shown. As can be seen from Figure 20, the side walls of wafers 12, 14, and i6 are sloped inwardly from top to bottom such that the wafer width at the bottom of each wafer is less than the wafer width at the top of the wafer. Thus, the outer peripheral edge of the wafer at the top of the substrate 18 extends beyond the outer peripheral edge of the wafer at the top of the substrate 18 by a distance 116' such that the top surface of the wafer 13 overhangs the bottom surface 17 beyond the distance 116. In one embodiment, the angled sidewalls help minimize damage during wafer selection and placement operations. For such an embodiment, it is believed that the distance 116 should be between five and ten percent (54%) of the thickness of the wafers 12, 14, and 16. In an exemplary embodiment, the distance 116 is approximately one to twenty (1_2 〇) microns, such that the bottom width of the wafer 12 at the bottom of the substrate 18 can be approximately two to forty degrees less than the top width of the wafer 12 at the surface ( 2_40) micron. In another embodiment, to be sure of the turns, the sidewalls should form an angle 丨丨8 of approximately fifteen to forty degrees (丨5. _4 〇.), the angle 118 being at the side walls and perpendicular, such as perpendicular to the top of the base 18 Between the straight lines of the face. Therefore, the width of the opening 29 should be etched each time by an amount sufficient to form the angle 118. In general, the top of the dividing line 15_16 is about one to forty (2_4 〇) microns larger than the bottom of the dividing line. Those skilled in the art will appreciate that multiple isotropic etching operations form the rough sidewalls of each of the wafers 12, 14, and 6 such that the sidewalls have a circumferentially uneven sidewall along the sidewalls. However, for the purpose of clarity of explanation, the degree of variation of the above-mentioned periphery is exaggerated in the illustration of Figures 16-21. These sidewalls are generally considered to be substantially smooth sidewalls. Figure 21 shows the 151883 with inwardly inclined side walls during the selection and placement operation. Doc -28· 201126648 Wafers 12, 14, and 16. As can be seen, the sloped sidewalls of wafers 12, I*, and 16 allow punch 35 to move one of the wafers upward, such as wafer 12' without colliding with other wafers, such as wafers 14 and 16. This helps reduce cracking and other damage to the wafers 12' 14, and 16 during the pick and place operation. Figure 22 shows other wafers without sloping sidewalls and how they might collide with each other during the selection operation. This configuration has the potential to cause damage to the wafer during selection and placement operations, such as damage to the periphery of the wafer. 6 Figure 23 shows the split semiconductor wafers 12, 14, and illustrated in the description of Figure 16.22. And a stage in an embodiment of another alternative method of forming an angled or angled sidewall. Those skilled in the art will appreciate that other segmentation techniques, such as those illustrated in the description of Figures 1-15, can be used to split the wafer from the wafer and form angled and oblique on the wafer. Side wall. For example, the anisotropic etch illustrated in the description of Fig. 4 can be used to form openings 28 and 29 into substrate 18 that are at a first distance no from the top surface of substrate i. Thus, the sidewall is substantially straight within the first distance of the sidewall. Then, the segmentation method described in the description of Figs. 16-22 can be used to perform the segmentation. The depth of the first distance depends on the thickness of the wafer, but will typically be as much as about fifty percent (5%) of the thickness of the wafer. Thereafter, etching to form openings (such as openings 1〇8 and 112), forming a polymer on the sidewalls of the opening, and removing the polymer from the bottom of the opening while leaving a portion of the polymerization Z on the sidewall (such as polymer 1〇9 and 113), can repeat the above two different 151883. Doc • 29· 201126648 Sex etching sequence until the openings 28 and 29 extend through the substrate 18 to form the dividing lines 13 and 15 completely through the substrate 18 ” another alternative method of dividing the semiconductor wafers 12, 14, and 16. Examples of embodiments include the use of an anisotropic etch, such as an anisotropic etch as illustrated in the description of Figure 4, to form openings 28 and 29 into substrate 18, which are aligned with the top surface of substrate 丨8. 12 degrees apart from the first distance. Thus, the sidewall is substantially straight within the first distance of the sidewall. Subsequently, an isotropic etch as illustrated in the description of FIGS. 16-22 can be used to extend the depth of the dividing lines 13 and 15 to a second distance that is greater than the distance 12 〇 but not yet completely through the substrate 18 . While extending the depth, isotropic etching also increases the width of lines 13 and 15. The width is extended to be wider than the width of the openings 28 and 29 on the dielectric 26. The final portion of the method may use an anisotropic etch to provide a substantially straight sidewall near the bottom of the dividing line. Then the dividing line here will be wider than the middle. This method or a combination of other methods can then be used to provide improved functionality, such as a wafer die that is locked to the sidewalls of the wafers 12, 14, and 16 or a peripheral ramp such that the bottom of the crystal 7 is wider than the top of the wafer, or The middle of the wafer is wider than the top of the wafer. Figures 24-28 illustrate wafer_cross-sectional views at various stages of an alternative embodiment of a semiconductor wafer from wafer 10. A cross-sectional view of the wafer 10 shown in Figures 24-28 is along the map! * The cut line is extracted 24-24. The exemplary embodiment of the alternative method illustrated in Figures 24-28 also includes an alternative method of reducing the wafer thickness to a thinner wafer 10. The wafer 10 includes a semiconductor wafer 12, i 16, 151883. Doc •30- 201126648 and the dividing lines 13 and 15, which are described in the description of Fig. _4 'Fig. 8·2〇, and Fig. Although not shown in Figures 24-28 for the purposes of clarity of the drawings and the description, the wafer 1 can also be included in the description of Figure 5-7 and the segmentation of the opening face is greater than Figure 2 - along the segmentation. Wafers 42, 44, and 46, 47-48 of lines 43 and 45. Because of the portion of the wafer 1〇 that is not present in the crossbar 23 of the wafer 1 shown in FIG. 24, FIG. 24 shows the additional wafer formed on the top surface of the wafer 10 along the additional dividing line. The additional dividing line includes dividing lines 11, 17, 137' and 138 which are similar to any of the dividing lines 13 and 15 or 43 and 45 illustrated in the description of any of Figs. In addition, Figure 24 illustrates a substrate 18 having a thickness 66 between the top surface of the substrate 18 and the bottom or back surface of the substrate 18. Subsequent to the formation of semiconductor wafers such as wafers 12, Μ, 16, and i4s on the top surface of substrate 18, the wafers are thinned to reduce the thickness 66 of substrate 18. An example of one embodiment of reducing the thickness 66 is shown in Figures 25·28. With respect to Figure 25, after a semiconductor wafer is formed on the top surface of substrate 18, wafer ίο can be inverted and attached to support strip or vial device 34 such that the top surface of substrate 18 faces device 34. Device 34 can be any known device that can be used to provide support for the wafer during thinning operations, such as from the operation of a backgrinding tape or other device. Figure 26 shows wafer 10 on a subsequent stage in an exemplary embodiment of a method of singulating wafers from wafer 10. Typically, the entire bottom surface of the wafer 1 is thinned to reduce the thickness of the wafer 10, i.e., from a thickness 66 to a thickness 67, which is less than the thickness 66. A variety of different well known methods can be utilized to reduce the thickness of the wafer 1 to a thickness of 67, such as is known to those skilled in the art 151883. Doc -31 - 201126648 f Back grinding, chemical mechanical polishing (CMp) or other techniques. In some embodiments, this step can be omitted in the method. Thereafter, the inner portion 125 of the bottom surface of the wafer ί is further reduced to a thickness 68 which is less than the thicknesses 66 and 67. The bottom surface portion of the wafer 10 that is removed during the formation of the inner portion 125 is shown in dashed lines. The thickness of the inner portion 125 is reduced in shape by subjecting the inner portion 125 to a grinding operation, or by a technique that reduces the thickness. The reduced thickness of the portion (2) leaves the outer rim 127' The outer peripheral edges of the wafers are juxtaposed. Thus, the outer rim 127 typically maintains a thickness 67. The thickness of the outer rim a? is sufficient to provide a support for processing or transporting the remaining wafers. , Personnel's tools and methods for reducing the thickness of the inner portion 125: an example of these tools and methods is included in the US patent numbered Eagle 6/〇244G96's inventor s kiss a, and published on November 2, 2006. Figure illustrates another subsequent step of dividing the wafer from the round. The wafer 34 can be removed from the wafer and the protective layer 135 applied to the wafer. The bottom surface, particularly the bottom surface of the wafer 1 应用 applied to the inner portion 125. The device 34 may have an ultraviolet release mechanism, such as release when exposed to ultraviolet light, or other known release mechanisms because of the layer 135 used to form Party The method generally includes the possibility of damaging the high temperature of the device 34. Therefore, the device (4) is removed. For embodiments that do not include such a high pan & sound alpha, or for a support device that is resistant to such temperatures, the device 34 can be retained. Nonetheless, the device 34 typically must be removed prior to subsequent operations. The portion of the layer 135 can also be applied to the underside of the outer rim 127, as the protective layer portion 133 shows 151883. Doc •32· 201126648 2 In some embodiments, the outer rim in can be masked as a mask; For example, the light =1 can be applied during the operation of the layer 135 to form the rim 127, or a shadow mask can be used to prevent the separation 133. Λ 'Figure 28 shows wafer defects on another subsequent manufacturing stage). After layer (1) is formed, wafer 1 is typically flipped again to an upright state. The bearing (4) is applied to the bottom surface of the crystal. In some embodiments, the straps 3 are attached to the aponeurosis frame 62 to provide support for those skilled in the art. Such film frames and carrier tapes are well known. The application band % is used as a carrier tool for handling and supporting the wafer. For embodiments in which different wafers are used to process the wafer, different carriers can be used and the tape 30 can be omitted. The application tape 3 is used as a tool for processing and supporting the wafer (7). Embodiments for processing wafer 10 using different carriers are used. Different carriers can be used, and the band 3 can be omitted. Typically, the vacuum chuck is used to hold the wafer 1G' and the strip 3G is aligned with the bottom surface of the wafer 1' such that the strip 3G provides a constant support for the wafer 1G. Thereafter, the split openings 28, 29, 140, and 141' are formed which terminate from the top surface of the wafer 1 into the substrate and reach the layer 135, the method of which is described in the previous description of FIGS. 2-23. The openings 28 and 29 or the openings 47 and 48 and the like are formed on the layer 27 in a manner similar to the opening of the winter end. Those skilled in the art will appreciate that other split openings are typically formed simultaneously with openings 28 and 29 to divide other wafers of wafer 1 . The layer 135 is formed of a material that is not etched by the dry etching method, and the dry etching method is used to form the divisions 28, 29, 140, and 141. In one embodiment, the protective layer 1 35 151883. Doc •33- 201126648 is a metal or metal compound, and the dry etching process chosen is a process that is much faster than etching metal. This process has been explained before. In other embodiments, the protective layer 135 can be a previously described nitriding, or a previously described lithium-metal compound. Layer 135 can also be the same material as the metal layer 27 previously described. In addition, the split openings 140 and 141 can be formed along with the split openings 28 and 2. The split openings 丨4〇 and 丨4丨 are formed through the substrate 18 in a manner similar to the formation of the openings σ 28 and 29 (or the openings 47 and 48) to form a knive. 1J lines 137 and 138. The dividing lines 137 and 138 are formed to separate the outer rim 127 from the remaining wafer 10. Thus, the formed dividing line 37 and generally overlying the inner portion 125 are located between the outer rim and any semiconductor wafer, the semiconductor wafer being located adjacent the rim 27, such as the semiconductor wafer 144 and 145 ^ For example, the dividing lines 137 and 138 may be one (1) continuous dividing line that extends around the outer circumference of the inner portion 125, such as crystal 〇 at the inner edge of the outer rim 127. Partially extended. Those skilled in the art will appreciate that using a wafer saw or other type of cutting tool to sing wafers from a wafer having such an inner portion 125 and rim 127 will subject the inner portion 125 to a large Mechanical stresses and the possibility of breaking the wafer 1 within the inner portion 125. Additionally, removing the rim 127 with a laser scribe may result in re-crystallization of the wafer adjacent the rim 127. Using the dry etch method described herein to remove the rim 127 will minimize the mechanical stress on the inner portion 125 and reduce the rupture of the crystal while removing the rim from the wafer 1 ' while removing the rim 127 Round possible 151883. Doc -34- 201126648 Sex. In some cases it may be desirable to remove the rim 127 from the wafer 10 without dividing the wafer formed on the wafer 1 . For such an alternative embodiment, the dividing lines 137 and 138 may be formed to remove the rim 127 from the wafer 1 without forming a dividing line for dividing the wafer of the wafer 10, such as the dividing lines 11, 13 , 15, and 17. After the rim 127 is removed, another strip similar to the strip 30 can be applied to the bottom surface of the portion 125, such as directly to the layer 135, and the wafer can then be singulated as described herein. In other embodiments, the tape 30 can be held to support the remaining wafer 10. Removing the rim 127 prior to singulation of the wafer allows for a quick and clean method that reduces the potential and mechanical stress of the scratched wafer, thereby improving yield and yield. Figures 29-31 illustrate various stages in another alternative embodiment of a method of dividing a wafer from wafer 1 . Figure 29 shows the wafer defect on the stage just after the stage illustrated in the description of Figure 26. The wafer 1 is removed from the support device 34, and a protective layer 13 5 is formed on the bottom surface of the inner portion 丨 25. Referring to Figure 30, a carrier tape 63 can be applied to the wafer 1 to provide support for the wafer 1 . A carrier tape 63 is applied to the top of the wafer 1 such that the top surface of the substrate 18 faces the strip 63. Typically, belt 63 is similar to belt 30 previously described. In some embodiments, the strap 63 is attached to the film frame, which is similar to the frame 62. The tape 63 is used as a load bearing tool for processing and supporting the wafer. Embodiments for processing wafer 10 using different carriers. Different carriers ' can be used' and the band 63 can be omitted. As shown by the dashed line on the portion 133, the removal is formed on the bottom surface of the outer rim 127 by 151883. Doc •35· 201126648 Any part of the protective layer 135. For example, the bottom surface of the outer rim 127 can be abraded for a time sufficient to remove the protective layer portion 133 as shown by the dashed lines, or the layer 135 can be masked and the portion η] can be etched from the rim 127. As previously explained, in some embodiments, the protective layer portion 133 is not formed on the outer rim 127. The thickness of the outer rim 127 can be reduced to a thickness 69 using a dry etch process. Using a dry etch process to reduce the thickness of the outer rim 127, the process can be any of the dry etch processes described herein, such as those used to form split openings, such as split openings 28 and 29. The thickness 69 is less than the previous thickness 67 of the outer rim 127. The value of the thickness is typically chosen such that the bottom surface of the outer rim 127 is close to the thickness 68 such that the carrier tape 30 (see Figure 31) provides better support for the wafer 1 。. In a preferred embodiment, the thickness 69 forms the bottom surface of the rim 127 that is substantially parallel to the outer side surface of the protective layer 135. The removal portion 133 allows dry etching to reduce the thickness of the rim 127. The portion 133 can be removed at different stages of the method as long as the portion 133 is removed prior to reducing the thickness of the rim 127. In some embodiments, the thickness 68 is no greater than about fifty (5 Å) microns. And it can be twenty five (25) microns or less. Those skilled in the art will appreciate that at this thickness, the wafer 1 may become brittle. The use of a dry-cut process to reduce the thickness of the rim 127 minimizes the mechanical stress on the wafer 1 compared to other thickness reduction methods such as back grinding or CMP. Figure 31 shows the wafer 10 on a subsequent stage. After reducing the thickness of the outer rim 127, the wafer 1 is typically flipped over and placed in the previously described 151883. Doc • 36- 201126648 The carrier tape 30 ′′ forms the split openings 28 and 29 which start from the top surface of the substrate 18 and penetrate through the substrate 18 and reach the protective layer 135 to terminate. In addition, split openings 140 and 141 are also formed which typically form with the openings 28 and 29 to separate the outer rim 27 from the semiconductor wafer of the wafer 10. Those skilled in the art will appreciate that the split openings are typically formed simultaneously with openings 28 and 29 to divide other wafers of wafer 10. Because of the small thickness of the wafer, the use of dry etching to divide the wafer minimizes mechanical stress on the wafer and reduces the likelihood of damage to the wafer and other damage. Figures 32-33 illustrate various stages in an example implementation of another alternative method of wafer singulation from a wafer. Figure 32 shows the wafer 1 at a stage just after the stage depicted in Figure 26. As previously explained, the device 34 can be removed from the wafer 10 and a protective layer 135 formed on the bottom surface of the inner portion 125. The protective layer η can be patterned to have openings through the protective layer 135 that are substantially aligned with the dividing lines to form the wafer ίο, such as at the dividing lines u, 13, 15, 17, 137, and I" Portions of Wafer H). It will be appreciated by those skilled in the art that a variety of different back alignment techniques can be utilized to ensure that the opening slaves formed on layer 135 are aligned to form a dividing line, such as Part of the substrate 18 at the dividing lines & 15, 137, and 138. Referring to Figure 33', a protective layer 135 can be used as a mask to protect the substrate Η while utilizing a dry residual process to form a split opening, 29' Μ. And 141 'extending from the bottom surface of the substrate 18, ^ 10, 70 king pages penetrate the substrate 18 and pass through from the top surface. It is illustrated that any of the methods of forming the split 47 and TM engraving may also be Was used to form = 151883. Doc •37- 201126648 Cut openings 140 and 141, and any other split openings through the base 18. The process also etches the outer rim 127 while forming the split opening, thereby reducing the thickness of the outer rim 127 to a thickness 69. As previously explained in the description of Fig. 30, any portion of the protective layer 133 is removed prior to reducing the thickness of the rim 127 and etching the split opening. Together with the formation of the thickness of the split opening reducing portion 127, the processing step is reduced, thereby reducing the manufacturing cost' and reducing the thickness also minimizes the mechanical stress on the rounded corner, thereby improving the yield and reducing the cost. The reduced thickness of the rim 127 makes it easier to handle the wafers 1 and makes it easier to remove the wafers after singulation. In other embodiments, the wheel 7 can be masked and the rim 127 is not surnamed while forming the openings 28, 29, 14A, and 141. After forming the split opening, another carrier tape (not shown), such as carrier tape 30', may be applied to the bottom surface of the wafer, such as to the bottom surface of the inner portion 125, and the wafer 1 may be flipped, or the inner portion 125 . Thereafter, the semiconductor wafer can be removed by the selection and placement techniques or other techniques previously described. One skilled in the art will appreciate that 'an example of a method of forming a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers, such as Wafers 12, 14, or 16, which form ' on the top surface of the semiconductor substrate and by forming a dividing line, such as a line! The semiconductor wafer portions at 3 and 15 are separated from each other; the semiconductor wafer is flipped; the thickness of the inner portion of the bottom surface of the semiconductor wafer, such as the portion (2), is reduced to a second thickness, which is less than the first thickness, i left The first thickness is 151883. Doc • 38·201126648 degrees of the outer rim of the +conductor wafer, such as rim 127, wherein the outer rim is juxtaposed with the outer circumference of the semiconductor wafer, and wherein the inner portion 1 is t-t the number of semiconductor wafers Forming a protective layer on the inner portion of the bottom surface of the semiconductor wafer, wherein the 'protective layer in the middle trace is one of metal or metallization=metal-stone compound; and the dry type is engraved with (four) side rim The first thickness is reduced to a third thickness, the third thickness, wherein the protective layer protects the inner portion from being dry etched such that the second thickness remains substantially constant. It will be understood by those skilled in the art that the method may further include disclosing the protective layer to expose the portion 2 of the semiconductor substrate at which the dividing line is to be formed, and using a dry-to-divide line from the semiconductor substrate The - face begins 'through the semiconductor substrate to the top surface of the semiconductor substrate. Another example of a method of forming a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom, and a plurality of semiconductor wafers, such as a wafer 12/14/16' The semiconductor wafer is formed on a semiconductor substrate and by a portion of the semiconductor wafer at which the dividing line is to be formed, such as a portion ip. Separating from each other; reducing the extent of the inner portion of the bottom surface of the semiconductor wafer, such as portion 825, to a second thickness that is less than the first thickness, and leaving;: the outer rim of the first thickness of the semiconductor wafer, such as a wheel a rim a?, the outer rim is juxtaposed with the periphery of the semiconductor wafer, and wherein the inner portion is located under the plurality of semiconductor wafers; a protective layer is formed on the inner portion of the bottom surface of the wafer; wherein the protective layer is a metal Or one of the metal ruthenium compounds of the metal compound i and the use of dry etching in the shape of 1 151883. Doc-39- 201126648 Forming the split opening at the secant line includes forming a split through the semiconductor substrate wherein at least one split opening is formed between the outer rim and any semiconductor wafer adjacent the outer rim. It will also be appreciated by those skilled in the art that the method can also include forming a split opening using dry etching that extends through the semiconductor substrate from the top surface of the semiconductor wafer. The method may further include patterning the protective layer to expose a portion of the bottom surface of the semiconductor wafer at which the dividing line is to be formed; and the step of forming the dividing opening using the dry pattern may include etching using the protective layer as a mask while using a dry rice etch Cutting the opening from the bottom surface of the semiconductor wafer, through the semiconductor substrate to the top surface of the semiconductor substrate, and using the dry-cut to engrave the outer rim, and reducing the first thickness of the outer rim to a third thickness The third thickness is less than the first thickness. In view of the above, it is apparent that a novel apparatus and method is disclosed. Among other things, the main purpose is to use a dry-money program to engrave the split openings that run completely through the semiconductor wafer. This dry etching process is generally referred to as plasma etching or reactive ion etching (RIE). Etching the opening from one side helps to ensure that the split opening has very straight sidewalls, thereby providing a uniform dividing line along each side of each semiconductor wafer. Etching The split openings that extend completely through the semiconductor wafer facilitate the formation of narrow dividing lines, thereby allowing more space on a given size of wafer for forming a semiconductor wafer. All dividing lines are generally formed at the same time. The etching process is faster than the dicing or wafer miscut process, thereby increasing throughput in the manufacturing field. Forming a dividing line through the trench filling material promotes the formation of a narrow dividing line, 151883. Doc -40- 201126648 This increases wafer utilization and reduces costs. The use of a split mask helps protect the inner portion of the wafer while forming the dividing line through the substrate. Forming the angled sidewalls reduces damage during the assembly operation, thereby reducing cost. In some embodiments, the angled sidewalls are typically formed simultaneously on all of the wafers. Although the subject matter of the present invention has been described in terms of specific preferred embodiments, it is apparent that many alternatives and modifications may be present in the present invention. For example, the layer 20 can be omitted from the substrate 8 or alternatively, the split opening can be formed before or after the contact opening covering the crucible is formed. Moreover, the split opening may be formed prior to thinning the wafer, for example, the cut opening may be formed partially through the substrate 18' and the thinning process may be used to expose the bottom of the split opening. BRIEF DESCRIPTION OF THE DRAWINGS - Simplified embodiment of a semiconductor wafer Figure 1 shows a plan view in accordance with the present invention; Figure 2 illustrates a portion of a wafer wafer wafer being waferd from a wafer in accordance with the present invention; The semi-conductor 3 of FIG. 1 at a stage in the process of enlarging the cross-sectional view is shown in a subsequent state in accordance with the present invention; FIG. 4 is shown in a subsequent stage in accordance with the present invention; In the process of dividing the wafer wafer in the wafer 1 , another FIG. 5 shows that the wafer of the semiconductor wafer is formed on the wafer of FIGS. 1-4 and is illustrated in the interpolation of FIGS. 1-4. Doc 201126648 Alternative embodiment of a wafer; FIG. 6 shows a process in the process of dividing the wafer of FIG. 5 in a subsequent stage according to the invention; FIG. 7 shows another process in the process of dividing the wafer in FIG. 6 according to the invention. Subsequent stages; Figures 8 - 1G are shown from the figure in accordance with the present invention! Steps in an exemplary embodiment of another method of semiconductor wafer time division of a wafer; FIGS. 11-14 illustrate steps of an exemplary embodiment t of another method of dividing a wafer from the semiconductor wafer of FIG. 0 in accordance with the present invention Figure 15 illustrates an exemplary embodiment of another method of dicing a wafer from the semiconductor wafer of Figure 14 in accordance with the present invention; Figure 16 - Figure 20 illustrates the dicing of a wafer from the semiconductor wafer of Figure 1 in accordance with the present invention. Steps in an exemplary embodiment of another method; FIG. 22 shows another stage in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 4 in accordance with the present invention; A segmentation method; FIG. 23 illustrates a stage in an exemplary implementation of another method of dividing a wafer from a +conductor wafer of FIG. 1 in accordance with the present invention, which is illustrated in FIGS. 16-20 An alternative embodiment of the method; FIG. 24 is a representation of another method of dicing the enthalpy from the semiconductor wafer of FIG. 1 in accordance with the present invention. View; 】 implementer Cross-Sectional Surfaces of Different Stages in the Formulas Figures 29-31 illustrate a different difference in another alternative embodiment from the semiconductor wafer of Figure 1 in accordance with the present invention. Doc •42. A cross-sectional view of the stage of 201126648; and Figures 32-33 are cross-sectional views showing different stages of an exemplary embodiment of another alternative method of splitting a wafer from the semiconductor wafer of Figure 1 in accordance with the present invention. [Description of main components] 10 semiconductor wafer 11 dividing line 12 semiconductor wafer 13 dividing line 14 semiconductor wafer 15 dividing line 16 semiconductor wafer 17 dividing line 18 substrate 19 block substrate 20 epitaxial layer 21 epitaxial layer 23 dielectric 24 contact pad 26 Dielectric 27 metal layer 28 split opening 29 split opening 30 carrier tape 151883. Doc • 43· 201126648 32 Mask 35 Selection and placement device/punch 42 Semiconductor wafer 43 Separation line 44 Semiconductor wafer 45 Separation line 46 Semiconductor wafer 47 Split opening 48 Split opening 50 Isolation trench 51 Dielectric 52 Polysilicon 54 Isolation trench Slot 55 Dielectric 56 Polysilicon 58 Isolation trench 59 Dielectric 60 Polysilicon 62 Frame 63 Carrier tape 64 Film frame 66 Thickness 67 Thickness 68 Thickness 151883. Doc 44- 201126648 71 semiconductor wafer 72 semiconductor wafer 73 semiconductor wafer 76 dividing line 77 dividing line 78 trench 79 trench 80 dielectric spacer 81 filling material 82 opening 83 opening 84 dotted line 85 mask 86 dotted line 87 mask 91 A1N Layer 92 dashed line 93 A1N 100 opening 101 carbon-based polymer 104 opening 105 carbon-based polymer 108 opening 109 polymer 15I883. Doc •45 201126648 112 opening 113 polymer 116 distance 118 angle 120 first distance 125 inner portion 127 outer rim 133 protective layer portion 135 protective layer 137 dividing line 138 dividing line 140 dividing opening 141 dividing opening 144 semiconductor wafer 145 semiconductor wafer 151883 . Doc ·46·