KR20190032319A - Semiconductor die singulation method - Google Patents

Abstract

The present invention relates to a semiconductor die singulation method, comprising: a step of providing a semiconductor wafer having a plurality of semiconductor dies; a step of positioning a first carrier tape adjacent to a metal layer; a step of generating a space between the plurality of semiconductor dies; and a step of leaving a part of the metal layer on the first carrier tape. According to the present invention, more uniform singulation can be provided.

Description

[0001] DESCRIPTION [0002] SEMICONDUCTOR DIE SINGULATION METHOD [

The present invention relates generally to electronic devices, and more particularly to methods of forming semiconductors.

BACKGROUND OF THE INVENTION In the past, the semiconductor industry used a variety of methods and equipment to singulate individual semiconductor die from a semiconductor wafer from which the die was fabricated. Typically, techniques referred to as scribing or dicing are performed along scribe grids that were formed on the wafer between individual dies using diamond cutting wheels or wafer saws ) To partially or totally cut the wafer. To allow for the width and alignment of the cutting tool, each scribe grid typically had a large width, typically about one hundred and fifty (150) microns, which consumed a large portion of the semiconductor wafer. Additionally, the time required to scribe all of the scribe grids on the entire semiconductor wafer may take more than an hour. This time reduced the throughput and manufacturing capacity of the manufacturing area.

Another method of singulating individual semiconductor die uses lasers to cut wafers along scribe grids. However, laser scribing was difficult to control and also resulted in non-uniform separation. Laser scribing also required protective equipment for operators as well as expensive laser equipment. Laser scribing is also reported to reduce die strength because the laser melts the crystalline structure along the edge of the die during singulation.

Accordingly, there is a need for a method of increasing the number of semiconductor dies on a wafer, providing a more uniform singulation, reducing the time to perform singulation, and having a narrower scribe line, Method.

It is an object of the present invention to provide a method of dicing singulation which increases the number of semiconductor dies on a wafer, provides more uniform singulation, reduces the time to perform singulation, and has a narrower scribe line.

According to the present invention there is provided a method of manufacturing a semiconductor device comprising the steps of: providing a semiconductor wafer having a semiconductor substrate and also having a plurality of semiconductor dies formed on the semiconductor substrate, the semiconductor die being separated from each other by portions of the semiconductor wafer, Wherein said portions of said semiconductor wafer are at locations where singulation lines are to be formed and said semiconductor wafer has an upper surface and a lower surface; Forming a trench enclosing a perimeter of each of the plurality of semiconductor dies in the portions of the semiconductor wafer, wherein forming a dielectric layer on the sidewalls of the trench, Forming a filler material in contact with the dielectric layer on the trench; Forming a dielectric layer overlying portions of the plurality of semiconductor dies; Etching a first opening through the dielectric layer over portions of the plurality of semiconductor dies and etching any underlying layers to expose at least the filler material of the trench; And a second opening through the filler material and any portion of the semiconductor substrate underlying the filler material so that the second opening extends completely through the semiconductor substrate from the upper surface of the semiconductor wafer Wherein etching of the second opening is performed through the first opening. ≪ RTI ID = 0.0 > A < / RTI >

The present invention provides a die singulation method that increases the number of semiconductor dies on a wafer, provides more uniform singulation, reduces the time to perform singulation, and has a narrower scribe line.

1 is a reduced plan view of an embodiment of a semiconductor wafer according to the present invention;
2 is an enlarged cross-sectional view of an embodiment of a portion of the semiconductor wafer of FIG. 1 at a stage of a process for singulating a die from a wafer according to the present invention.
Figure 3 illustrates the subsequent steps of a process for singulating die from the wafer of Figure 1 according to the present invention.
Figure 4 illustrates yet another subsequent step of a process for singulating die from the wafer of Figure 1 in accordance with the present invention;
FIG. 5 is an alternative embodiment of the dies described in the discussion of FIGS. 1-4 and showing enlarged cross-sectional portions of semiconductor dies formed on the wafer of FIGS. 1-4; FIG.
Figure 6 shows the subsequent steps of the process for singulating die of Figure 5 according to the present invention;
Figure 7 illustrates yet another subsequent step in the process of singulating the die of Figure 6 in accordance with the present invention;
Figures 8-10 illustrate steps in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1 in accordance with the present invention.
Figures 11-14 illustrate steps in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1 in accordance with the present invention.
15 illustrates an exemplary embodiment of another method for singulating die from the semiconductor wafer of Fig. 14 according to the present invention. Fig.
Figures 16-20 illustrate steps in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1 in accordance with the present invention.
Figure 21 illustrates yet another step in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1 according to the present invention.
22 illustrates another singulation method;
Figure 23 illustrates the steps in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1, an alternative embodiment of the method of Figures 16-20 in accordance with the present invention.
Figures 24-28 are cross-sectional views of various steps in an exemplary embodiment of another method for singulating die from the semiconductor wafer of Figure 1 according to the present invention.
29-31 are cross-sectional views of various steps in yet another alternative embodiment of an example of a method for singulating die from the semiconductor wafer of FIG. 1 according to the present invention.
32 and 33 are cross-sectional views of various steps in an exemplary embodiment of another alternative method for singulating die from the semiconductor wafer of FIG. 1 in accordance with the present invention;
In order to simplify and clarify the description, the elements in the figures are not necessarily drawn to scale, and in different drawings the same reference numerals denote the same elements. In addition, the descriptions and details of widely-known steps and elements are omitted for simplicity of illustration. For clarity of illustration, the doped regions of the device structures are generally shown with straight edges and corners of the correct angle. However, those skilled in the art understand that due to the diffusion and activation of the dopants, the edges of the doped regions may not be generally straight lines, and that the corners may not be exact angles. It will be appreciated by those skilled in the art that the use of the word " approximately " or " substantially " means that the value of the element has a parameter that is predicted to be very close to the stated value or position. However, as is well known in the art, there are always small deviations that prevent the values or positions from being accurately stated. It has been established in the art that deviations of up to at least ten percent (10%) (and up to twenty percent (20%) of the semiconductor doping concentrations) are reasonable deviations from the ideal goal as described precisely.

Figure 1 is a reduced plan view diagrammatically illustrating a semiconductor wafer 10 having a plurality of semiconductor dies, such as dies 12, 14, and 16 formed on a semiconductor wafer 10. Dies 12, 14, and 16 are spaced apart from one another on the wafer 10 by spaces in which singulation lines, such as the singulation lines 13 and 15, must be formed. As is well known in the art, all of the plurality of semiconductor dies are generally separated from each other at all sides by areas where singulation lines, such as lines 13 and 15, are to be formed.

Fig. 2 shows an enlarged cross-sectional view of the wafer 10 of Fig. 1 taken along a section line 2-2. For the sake of clarity of the drawings and description, this cutting line 2-2 is shown cutting the die 12 and only the parts of the die 14 and 16. Dies 12,14 and 16 may be any type of semiconductor die including integrated circuits including diodes, vertical transistors, lateral transistors, or various types of semiconductor elements. . Semiconductor dies 12, 14, and 16 generally comprise a semiconductor substrate 18 that may have doped regions formed in a substrate 18 to form active and passive portions of the semiconductor die. The cross-sectional portion shown in FIG. 2 is taken along the contact pads 24 of each of the dies 12, 14, and 16. The contact pad 24 is typically a metal formed on a semiconductor die to provide electrical contact between the semiconductor die and elements outside the semiconductor die. For example, the contact pad 24 may be formed to receive a bonding wire that may later be attached to the pad 24, or may be formed of a solder ball May also be configured to accommodate other types of interconnect structures. The substrate 18 includes a bulk substrate 19 and an epitaxial layer 20 is formed on the surface of the bulk substrate 19. Portions of epitaxial layer 20 may be doped to form doped regions 21 that are used to form active and passive portions of semiconductor die 12, 14, or 16. Layer 20 and / or region 21 may be omitted in some embodiments, or may be in different regions of dies 12, 14, or 16. Typically, the dielectric 23 is formed on the top surface of the substrate 18 to isolate the pads 24 from other portions of the respective semiconductor die and to isolate the respective pads 24 from adjacent semiconductor dies. The dielectric 23 is typically a thin layer of silicon dioxide formed on the surface of the substrate 18. [ The contact pad 24 is typically a metal in which a portion of the contact pad 24 is in electrical contact with the substrate 18 and another portion is formed on a portion of the dielectric 23. After the dies 12, 14, and 16 are formed that include metal contacts and any associated inter-layer dielectric (not shown), the dielectric 26 is typically deposited on the wafer 10, And a plurality of semiconductor dies to function as a passivation layer for each respective semiconductor die 12, 14, and 16. The dielectric 26 is typically formed on the entire surface of the wafer 10, such as by blanket dielectric deposition, and may, in some embodiments, be formed below the contact pad 24. The thickness of the dielectric 26 is generally greater than the thickness of the dielectric 23.

Figure 3 shows a cross-sectional view of the wafer 10 of Figure 2 in a subsequent stage of the process of singulating dies 12, 14, and 16 from the wafer 10. [ After the passivation layer of dielectric 26 is formed, a mask 32, shown with dashed lines, may be applied to the surface of substrate 18, overlying each pad 24, May be patterned to form openings that expose portions of the dielectric 26 overlying portions of the wafer 10 where the singulation lines, such as lines 13 and 15, should be formed. Dielectrics 26 and 23 are then etched through the openings in mask 32 to expose the underlying surfaces of pads 24 and substrate 18. The openings formed through the dielectrics 26 and 23 in the region where the singulation lines, such as lines 13 and 15, are to be formed serve as the singulation openings 28 and 29. The openings formed through the dielectric 26 overlying the pads 24 serve as contact openings. The etching process is preferably performed with a process that selectively etches the dielectrics faster than etching the metals. The etch process generally etches dielectrics at least ten to ten times faster than etching the metals. The material used for the substrate 18 is preferably silicon and the material used for the dielectric 26 is preferably silicon dioxide or silicon nitride. The material of the dielectric 26 may also be other dielectric materials that can be etched without etching the material of the pads 24, such as polyimide. The metal of the pads 24 serves as an etch stop to prevent the etching from removing the exposed portions of the pads 24. In a preferred embodiment, a fluorine based anisotropic reactive ion etch process is used.

After forming the openings through the dielectric 26 the mask 32 is removed and the substrate 18 is removed to remove material from the lower surface 17 of the substrate 18 and reduce the thickness of the substrate 18. [ ) Is thinned. In general, the substrate 18 is thinned to a thickness no greater than about one hundred to two hundred (200 to 200) microns. Such thinning procedures are well known to those skilled in the art. The lower surface of the wafer 10 including the lower surface 17 of the substrate 18 may be metallized with a metal layer 27 after the wafer 10 is thinned. This metallization step may be omitted in some embodiments. The wafer 10 is then attached to a carrier tape or carrier tape 30 that facilitates supporting a plurality of die typically after a plurality of dies have been singulated. Such carrier tapes are well known to those skilled in the art.

4 shows the wafer 10 at a subsequent stage of the process of singulating the semiconductor dies 12, 14, and 16 from the wafer 10. The substrate 18 is etched through the singulation openings 28 and 29 that were formed in the dielectric 26. The etching process extends the singulation openings 28 and 29 completely through the substrate 18 from the top surface of the substrate 18. [ The etching process is typically performed using a chemistry that selectively etches silicon at a much higher rate than the dielectrics or metals. The etching process generally etches the silicon at least fifty (50) times, preferably one hundred (100) times faster than etching the dielectrics or metals. Typically, a Deep Reactive Ion Etcher (DRIE) system using a combination of isotropic and anisotropic etch conditions is used to remove openings 28 and 29 from the top surface of substrate 18, Lt; RTI ID = 0.0 > through < / RTI > In the preferred embodiment, a process, referred to as the Bosch process, is used to anisotropically etch the singulation openings 28 and 29 through the substrate. In one example, the wafer 10 is etched into a Bosch process in an Alcatel deep reactive ion etch system.

The widths of the singulation openings 28 and 29 are generally between zero and ten (5 to 10) microns. This width is sufficient to ensure that the openings 28 and 29 can be formed completely through the substrate 18 and are sufficiently narrow to form openings at short time intervals. Typically, the openings 28 and 29 can be formed through the substrate 18 within a time interval of approximately fifteen to thirty-five (15 to 30) minutes. Because all of the singulation lines of the wafer 10 are formed simultaneously, all of the singulation lines can be formed across the wafer 10 within approximately the same time interval of 15 to 30 (15 to 30) . Thereafter, as the wafer 10 is moved from the wafer 10 to the pick-and-place equipment 35 used to remove each individual die, the wafer 10 is transferred to the carrier tape < RTI ID = (30). Typically the equipment 35 pushes each singulated die such as die 12 upwardly so that each singulated die is pulled from the carrier tape 30 and from the singulated die (Not shown) that removes the vacuum pump (not shown). During the pick-and-place process, a portion of the thin backing metal layer underlying the openings 28 and 29 is separated and remains on the tape 30.

5 is an alternative embodiment of the dies 12, 14, and 16 described in the description of Figs. 1-4 and includes an enlarged view of the semiconductor dies 42, 44, and 46 formed on the wafer 10 Fig. The dies 42,44 and 46 are shown in the manufacturing state after forming the dielectric 23 on the top surface of the substrate 18 and before forming the pads 24 (Figure 1). The dies 42,44 and 46 comprise respective insulating trenches 50,54 and 58 which surround the dies 42,44 and 46 respectively and insulate the dies from adjacent dies. 14, and 16, except that the die 12, 14, Trenches 50, 54, and 58 are typically formed adjacent the outer edge of each die. The trenches 50, 54, and 58 are formed to extend a first distance from the top surface of the substrate 18 to the bulk substrate 19. Each trench 50, 54, and 58 is generally formed as an opening into a substrate 19 having a dielectric formed on the sidewalls of the opening, and is typically filled with a dielectric, or other material such as silicon or polysilicon. For example, the trench 50 may include a silicon dioxide dielectric 51 on the sidewalls of the trench opening, and may be filled with polysilicon 52. Similarly, trenches 54 and 58 include respective silicon dioxide dielectrics 55 and 59 on the sidewalls of the trench opening, and may be filled with polysilicon 56 and 60. The singulation line 43 should be formed between the trenches 50 and 54 and the singulation line 45 should be formed between the trenches 50 and 58. Trenches 50 and 54 are formed adjacent to the singulation line 43 and trenches 50 and 58 are formed adjacent to the singulation line 45. [ Methods of forming the trenches 50, 54, and 58 are well known to those skilled in the art. It should be noted that the trenches 50 and 54 are used by way of example only and may be any number of shapes, sizes, or combinations of isolation tubs or trenches.

Figure 6 shows the wafer 10 at a later stage of the process of singulating the semiconductor dies 42, 44, and 46 from the wafer 10. After trenches 50,54 and 58 are formed, other portions of dies 42,44 and 46 are formed which form the contact pads 24 and form dice 42,44 , And 46). ≪ / RTI > The dielectric 26 generally covers other portions of the wafer 10, including portions of the substrate 18 on which the singulation lines 43 and 45 should be formed. A mask 32 is then applied and patterned to expose the underlying dielectric 26 where the singulation lines and contact openings should be formed. The dielectric 26 is etched through the openings in the mask 32 to expose the pads 24 and the underlying surface of the substrate 18. The openings formed through the dielectric 26 in the region where the singulation lines, such as lines 43 and 45, are to be formed serve as the singulation openings 47 and 48. The etch process used to form the openings 47 and 48 through the dielectrics 23 and 26 is similar to the process of forming the openings 28 and 29 (FIG. 3) in the dielectrics 23 and 26, same. The openings 47 and 48 are preferably such that the dielectrics 51,55 and 59 on the sidewalls of each of the trenches 50,54 and 58 are not located below the openings 47 and 48 So that the dielectrics will not be affected in subsequent operations to form the singulation lines 43 and 45.

After the openings 47 and 48 are formed through the dielectric 26, the mask 32 is removed, the substrate 18 is thinned and the metal layer 27 is removed, as described above in the description of FIG. . This metallization step may be omitted in some embodiments. After metallization, the wafer 10 is typically adhered to the carrier tape 30.

Figure 7 shows the wafer 10 at a subsequent stage of the process of singulating the semiconductor dies 42,44 and 46 from the wafer 10. [ The substrate 18 is etched through the singulation openings 47 and 48 that were formed in the dielectric 26. The etching process extends the singulation openings 47 and 48 completely through the substrate 18 from the top surface of the substrate 18. [ The openings 47 and 48 are typically at least 0.5 microns away from the dielectrics 51,55 and 59. The etch process is typically an isotropic etch that selectively etches silicon at a rate much higher than the dielectrics or metals, generally at least fifty (50) times, and preferably at least hundreds of times faster. Isotropic etch can be used because the dielectric on the sidewalls of the trenches protects the silicon of the substrate 18. [ The isotropic etch has a much higher etch throughput that can be achieved with the use of a Bosch process or with limited use of the Bosch process. However, isotropic etching typically undercuts portions of the substrate 19 underlying the trenches 50, 54, and 58. Typically, a down-stream etcher by a fluorochemical etches the openings 28 and 29 completely through the lower surface of the substrate 18 from the upper surface of the substrate 18, Lt; RTI ID = 0.0 > 28 < / RTI > In one example, the wafer 10 is etched in a deep reactive ion etch system using fully isotropic etching available from various products, including those available from Plasma Therm, LLC (10050 16th Street North St. Petersburg, FL 33716) do. In other embodiments, isotropic etching can be used for most of the etching and anisotropic etching can be used for another part of the etching (Bosch process). For example, an isotropic etch may be used until the openings 28 and 29 extend to a depth that is substantially the same as the depth of the trenches 50, 54, and 58, and then the trenches 50 and 54 , And 58 may be used to prevent undercutting.

The width of the singulation openings 47 and 48 is generally approximately equal to the width of the openings 28 and 29. The dies 42,44 and 46 may be removed from the tape 30 similar to the manner in which the dies 12,14 and 16 are removed.

In another embodiment, the trenches 50 and 58 may be spaced apart a sufficient distance to allow the standard scribing tool or wafer saw to extend through the opening 48. A portion of the layer 27 underlying the opening 48 can be used as a scribe tool or wafer saw to crack the wafer 10 below the openings 47 and 48 and separate along the openings 47 and 48. [ Or may be bent through the rollers, or may be removed by other techniques such as laser scribing or the like. Trenches 50 and 54 may have similar spacings to facilitate cutting a portion of underlying layer 27 in a similar manner. For a method of using a scribe tool to scribe layer 27, layer 27 may be broken along the path of the scribe tool to complete the separation. The dies 42, 44, and 46 may then be removed from the tape 30 by standard pick and place techniques. These methods facilitate separating and singulating the dies 42, 44, and 46.

Alternatively, the isotropic etch may be terminated when the depth of the openings 47 and 48 reaches the bottom of the trenches 50, 54, and 58, or when the bottoms of the trenches just overtake. The exposed portions of the substrate 19 may then be scribed or scoured with a scribe tool to complete the separation of the die or may be removed with other techniques such as laser cutting, have. The sawing technique can be extended to slack through the metal layer 27. The scribing technique will destroy the layer 27 when the material of the substrate 19 is broken along the path formed by the scribing tool.

Those skilled in the art will appreciate that the use of trenches 50, 54, and 58 to singulate a die is advantageous in that the die 42, 44, and 46 are insulated from the elements outside the die by dielectric sidewalls of the trenches, Lt; RTI ID = 0.0 > sidewalls. ≪ / RTI > The dielectric forms a dielectric material on the sidewalls of the die. The insulation provided by the dielectric of the trenches can reduce the leakage current between the die and the external device. The structure can also improve the breakdown voltage of the die. The use of trenches 50, 54, and 58 can also increase die strength through laser die singulation methods.

Referring again to the etch technique used to extend the openings 47 and 48 to the substrate 19, those skilled in the art will appreciate that the openings 47 and 48 are not etched faster than the trenches 50, 54, and 58), it is faster to remove the material of the openings. Then, using an anisotropic etch prevents undercutting trenches 50, 54, and 58. Thus, using an isotropic etch prior to the anisotropic etch also provides high throughput and good lateral control for portions of openings 47 and 48 that are deeper than trenches 50, 54, and 58.

Figure 8 shows the steps in an exemplary embodiment of another alternative method of singulating semiconductor dies 71, 72, and 73 formed on a semiconductor wafer 10. Figure 8 shows an enlarged section of dies 71 to 73 after forming dielectric 23 on the top surface of substrate 18 and in the manufacturing state prior to forming pads 24 (Figure 2) . ≪ / RTI > The dies 71 to 73 are formed by dies 42, 44, and 73, except that the dies 71 to 73 have a single insulating trench 79 surrounding each die on the wafer 10. [ And 46).

One example of a method for singulating a semiconductor die from a wafer 10, as will be additionally recognized below, is to: < RTI ID = 0.0 > Providing a semiconductor wafer, such as a wafer 10 also having a die, wherein the semiconductor die is separated from each other by portions of the semiconductor wafer, and wherein the portions of the semiconductor wafer are separated from the lines 13 and 15, Present in locations where the same singulation lines are to be formed; Forming a trench in the portions of the semiconductor wafer such as a trench (79) surrounding a perimeter of each of the plurality of semiconductor dies, forming a dielectric layer on the sidewalls of the trench, Forming a filler material in the trench and in contact with the dielectric layer on the sidewalls; Forming a passivation layer, such as a layer (26) overlying portions of the plurality of semiconductor die; Etching the first opening, e.g., opening 82, through the passivation layer and any underlying layers to expose at least the filler material of the trench; And etching a second opening, such as opening (81), through the filler material and any portion of the semiconductor substrate underlying the filler material, such that the second opening completely fills the semiconductor substrate from the surface of the semiconductor wafer Wherein the second opening is etched through the first opening.

Yet another embodiment of the method further comprises forming a trench opening extending from the surface of the semiconductor substrate to a first distance from the semiconductor substrate, wherein a first portion of the semiconductor substrate lies below the trench opening, The trench opening having sidewalls and a bottom; Forming the dielectric layer on the sidewalls of the trench opening and the lower portion of the trench opening and leaving a portion of the trench opening between the sidewalls as an empty space; Removing the dielectric on the bottom of the trench opening; And filling the void space of the trench opening with the filler material abutting the dielectric layer on the sidewalls of the trench.

The trenches 79 extend beyond the edges of the trenches 79 except that the trenches 79 extend to surround each of the dies 71 to 73 and the perimeter of any other die formed on the wafer 10. [ 54, or 58 that has been described in the description of FIG. The trench 79 is formed to include a dielectric liner 80, such as silicon dioxide, on the sidewalls and bottom of the self 79. In the preferred embodiment, the bottom of the dielectric liner 80 is removed and the bottom of the trench 79 is opened as shown by the dashed line 84. One exemplary method of removing the bottom of the liner 80 includes applying a mask 85 having openings that expose the trenches 79 and removing the spacer etch through the bottom of the liner 80 ). ≪ / RTI > The etch may be selective to dielectrics on the silicon to prevent damage to portions of the substrate 180 underlying the trenches 79. The mask 85 is generally removed after the bottom of the liner 80 has been removed. After removing the bottom of the trench 79, the remaining openings of the trench 79 are filled with the filler material 81. The filler material 81 is typically a silicon based material such as polysilicon to facilitate subsequent process steps, as will be additionally recognized below.

Those skilled in the art will appreciate that any one of the dies 71-73 may also have other trenches such as trench 78 in the interior of the die and that these trenches may be subjected to a process operation similar to the process operations used to form the trench 79 As will be appreciated by those skilled in the art. The trenches 78 may allow the lower oxide to be retained or the lower oxide to be removed, depending on the function it performs. For example, the trench 78 may be filled with doped polysilicon and may be deposited on the bottom or backside of the substrate 18 (not shown in FIG. 8) or the metal layer 27 Or a backside contact. However, in the preferred embodiment of the trench 78, the bottom is not removed, and the trench 78 is preferably inside the die and does not surround the outside perimeter of the die. Thus, the trenches 79 can be formed simultaneously with the trenches 78 or other similar trenches, thereby reducing manufacturing costs. As will be understood by those skilled in the art, the dies 71-73 may have a variety of active and / or passive elements formed on or in the substrate 18. [

Trench 79 is formed in the singulation lines 76 and 77, and preferably in the middle of the singulation lines, so that the middle of the trench 79 is roughly the middle of the singulation line. As will be additionally recognized below, the singulation will occur approximately through the middle of the trench 79.

Figure 9 shows the wafer 10 in a subsequent step of an exemplary method of singulating semiconductor dies 71-73 from the wafer 10. After the trenches 79 are formed, other parts of the dies 71 to 73 are formed which form the contact pads 24 and the dielectric 26 covering the dies 71 to 73 . The dielectric 26 generally covers other portions of the wafer 10, including portions of the substrate 18 on which the singulation lines 77 and 76 are to be formed. A mask 87 is then applied and patterned to expose underlying dielectric lines 26 where the singulation lines 76 and 77 and contact openings are to be formed. The mask 87 is similar to the mask 32 shown in Fig. 3, but the mask 87 typically has slightly different positions. The openings in the mask 87, in which the singulation lines 76 and 77 are to be formed, also lie on the trench 79. The dielectric 26 is etched through the openings in the mask 87 to expose the underlying filler material 81 in the trench 79. Etching also exposes pads 24 that are typically underneath. The openings formed through the dielectric 26 in the region where the singulation lines, such as lines 76 and 77, are to be formed serve as the singulation openings 82 and 83. The etch process used to form the openings 82 and 83 through the dielectric 26 is substantially the same as the process of forming the openings 28 and 29 (FIG. 3) in the dielectrics 23 and 26. The openings 82 and 83 are typically formed in the dielectric liner 80 on the sidewalls of the corresponding trench 79, although the dielectric liner 80 need not be exposed as long as the material 81 is exposed. Lt; RTI ID = 0.0 > 82 < / RTI > The openings 82 and 83 are typically two portions of a single opening surrounding the die 71-73, but are shown as two openings due to the cross-sectional view.

After forming the openings 82 and 83 through the dielectric 26, the mask 87 is removed, as shown by the dashed lines, and the substrate 18, as shown by the dashed line 86, Is thinned. Thinning removes most of the substrate 18 underlying the trenches 79. Because the dielectric material of the dielectric liner 80 can damage the tool used to thin the wafer 10 and allow it to scratch the wafer 10, ) Is not thinned down to the bottom. Preferably, the substrate 18 is thinned until the trenches 79 are about two to five microns from the bottom to the substrate 18. [ In some embodiments, the substrate 18 may be thinned until the bottom of the trench 19 is exposed. Thereafter, the lower surface of the substrate 18 is metallized with the metal layer 27, as described above in the description of Fig. This metallization step may be omitted in some embodiments. The wafer 10 is then typically affixed to a conventional carrier substrate, such as a carrier tape 30, or a conventional carrier.

Figure 10 shows the wafer 10 in a subsequent step of an example of an embodiment of a method for singulating die 71-73 from a wafer 10. A second opening is formed through the filler material 81 to penetrate the substrate 18 to form singulation lines 76 and 77. The substrate 18 is preferably etched through the singulation openings 82 and 83 using the dielectric 26 as a mask, similar to the etch described in the description of FIG. The etching process penetrates the material 81 to form an opening. Typically, the etch substantially removes all of the material 81 to extend the singulation lines 76 and 77 completely through the filler material 81 of the trench 79 from the top surface of the substrate 18 . The etch process is typically an isotropic etch that selectively etches silicon at a rate much higher than the dielectrics or metals, generally at least fifty (50) times, and preferably at least hundreds of times faster. The filler material 81 is removed without etching the dielectric liner 80 on the sidewalls of the trench 79, since the etching step is selective to silicon on the dielectrics. Thus, the dielectric liner 80 on the sidewalls of the trenches 79 protects the silicon of the substrate 18 from isotropic etches. The isotropic etch has a much higher etch throughput that can be achieved with the use of a Bosch process or with limited use of the Bosch process. The isotropic etch process etches through the filler material 81 and any portion of the substrate 18 underlying the trench 79. Thus, the die 71 to 73 are singulated by etching through the isotropic trench 79 and any underlying portion of the substrate 18. [ High-speed etching improves throughput and reduces manufacturing costs. Those skilled in the art will appreciate that the silicon-based material of the filler material 81 also reduces the stress on the material of the substrate 19 and the dielectric liner 80.

Singling the dies 71 to 73 along the singulation lines 76 and 77 through the trenches 79 occupies a very small space of the semiconductor wafer. For example, the width of the trench 79 including the filler material 81 is typically only about three (3) microns. Thus, the singulation lines 76 and 77 may be only about three microns wide instead of a hundred microns in other methods of singulating die such as scribing or wafer sawing. It will be apparent to those skilled in the art that the step of thinning the wafer 10 may be omitted and etching of the material 81 may continue until the openings 82 and 83 extend through the wafer 10 .

As described in the description of FIG. 4, the pick-and-place tool may include any portion of the metal layer 27 underlying the openings 82 and 83 to complete the singulation of the dies 71 to 73 Lt; / RTI > Those skilled in the art will appreciate that other methods may also be used to cut the metal layer 27 within the singulation lines 76 and 77. For example, the metal layer 27 may be scribed along the bottom surface of the layer 27 prior to applying the tape 30, so that the layer 27 may be scribed on the line 27 when the pick- Lt; / RTI > Alternatively, portions of the layer 27 underlying the singulation lines 76 and 77 may be etched from the backside of the layer 27 prior to application of the tape 30. Etching of the layer 27 singulates the layer 27. Another method of cutting the layer 27 is to blow a jet of air onto a portion of the tape 30 that lies beneath the wafer 10. The air will cause the tape 30 to be stretched upward and cut the layer 27 at a portion of the layer 27 lying below the singulation lines 76 and 77. In addition, a second carrier tape, not shown, may be placed on the front side of the wafer 10. Thereafter, the tape 30 can be removed. The step of removing the tape 30 will cut the layer 27 in a portion of the layer 27 underlying the singulation lines 76 and 77. Any of these alternative methods of cutting the layer 27 may be used in any of the singulation methods described herein.

FIG. 11 illustrates steps in an exemplary embodiment of another alternative method of singulating semiconductor dies 12, 14, and 16 as described in the discussion of FIGS. 1-4.

As will be additionally recognized below, an example of one method of singulating a semiconductor die from a semiconductor wafer includes: a semiconductor substrate having a first thickness, a top surface, a bottom surface, and a semiconductor substrate formed on the semiconductor substrate, Providing a semiconductor wafer having a plurality of semiconductor dies separated from one another by portions of the semiconductor wafer on which the lines should be formed; Forming a singulation mask layer, such as AlN (93), overlying the plurality of semiconductor die; Forming an opening through the singulation mask layer; Forming an opening through the underlying layers and exposing portions of the surface of the semiconductor substrate; And using the opening in the singulation mask layer as a mask while etching the first opening to extend completely through the semiconductor wafer from the exposed portion of the surface of the semiconductor substrate.

Yet another embodiment of the method comprises: attaching the semiconductor wafer to a carrier tape prior to using the opening in the singulation mask layer as a mask; And using the pick-and-place equipment to separate the carrier tape and separate one of the plurality of semiconductor dies from another of the plurality of semiconductor dies.

In another embodiment of the method, the singulation mask layer is formed of a metal compound, an aluminum nitride (AlN), a titanium nitride, a metal-silicon compound, a titanium silicide, an aluminum silicide, a polymer, or a layer that is one of polyimide.

The dies 12,14 and 16 may be formed after forming the dielectric 23 on the top surface of the substrate 18 as described in the description of Figure 2 and forming the pads 24 and dielectric 26 Lt; / RTI > is shown in the state of manufacture after the first. After forming the dielectric 26, a singulation mask is formed to facilitate forming the openings through the substrate 18 without etching underlying layers such as portions of the dielectric 26. In a preferred embodiment, the singulation mask is formed from aluminum nitride (AlN). In this preferred embodiment, an AlN layer 91 is formed at least on the dielectric 26. The layer 91 is generally applied to cover all of the wafers 10.

Figure 12 shows a cross-sectional portion of the wafer 10 of Figure 11 in a subsequent step of an example of a preferred embodiment of a method for singulating dies 12, 14, and 16 from a wafer 10. [ After the AlN layer 91 is formed, a mask 32 is applied to the surface of the substrate 18, and the alignment lines, such as the singulation lines 13 and 15, Are patterned to form openings that expose portions of the dielectric 26 overlying portions of the wafer 10 that are to be formed.

To form the mask 32, a photographic mask material is applied to the wafer 10 and then exposed to light, such as ultraviolet light, to change the chemical composition of the exposed portions of the mask material, Singulation lines should be formed and also form a mask 32 having openings that lie over the locations where the pads should be formed. Thereafter, a developer solution is used to remove unexposed portions of the mask material, thereby having openings 28 and 29 overlying the locations where the respective singulation lines 13 and 15 should be formed The mask 32 is left. It has also been found that the use of an ammonium hydroxide based developer solution also allows the developer to remove portions of the AlN layer 91 that lie beneath the unexposed portions of the mask material. The removed portion of layer 91 is shown as dashed lines 92 and the remaining portions of layer 91 are identified as AlN 93. The AlN 93 functions as a singulation mask, as will be additionally recognized below.

13 shows a cross-sectional portion of the wafer 10 of Fig. 12 in yet another subsequent stage of an example of an alternative embodiment of a method for singulating dies 12,14, and 16 from a wafer 10. Fig. The dielectrics 26 and 23 are etched through the openings in the mask 32 and the AlN 93 to expose the pads 24 and the underlying surface of the substrate 18. The openings formed through the AlN 93 and dielectrics 26 and 23 in the region where the singulation lines, such as lines 13 and 15, are to be formed, serve as the singulation openings 28 and 29 . The openings formed through the dielectric 26 overlying the pads 24 serve as contact openings. The etching process is preferably performed in a process that selectively etches silicon-based dielectrics such as silicon dioxide or silicon nitride faster than etching the metals. The etch process generally etches silicon-based dielectrics at least ten to ten times faster than etching the metals. The metal of the pads 24 serves as an etch stop to prevent etching from removing exposed portions of the pads 24. [ In a preferred embodiment, as described above, a fluorine-based anisotropic reactive ion etch process is used.

After forming the openings through the dielectrics 26 and 23, the mask 32 is typically removed, as shown by the dashed lines. The substrate 18 is generally thinned to remove material from the bottom surface of the substrate 18 and reduce the thickness of the substrate 18, In general, the substrate 18 is thinned to a thickness no greater than about twenty-five to four hundred (25 to 400) microns, and preferably between about fifty and twenty-five (50 to 250). Such thinning procedures are well known to those skilled in the art. After the wafer 10 is thinned, the backside of the wafer 10 can be metallized with the metal layer 27. [ This metallization step may be omitted in some embodiments. The wafer 10 is then typically affixed to a carrier tape or carrier tape that facilitates supporting a plurality of dies after the plurality of dies have been singulated.

Figure 14 shows a wafer 10 in a subsequent step of an exemplary embodiment of an alternative method of singulating semiconductor dies 12, 14, and 16 from a wafer 10. An AlN 93 is used as a mask in etching the substrate 18 through the singulation openings 28 and 29. The AlN 93 protects the dielectric 26 from being affected by etching. The AlN 93 may have a thickness of about fifty to three hundred (50 to 300) angstroms and still protect the dielectric 26. Preferably, the AlN 93 is about 200 angstroms thick. The etching process extends the singulation openings 28 and 29 completely through the substrate 18 from the top surface of the substrate 18. [ The etching process is typically performed using a chemical that selectively etches the silicon at a much higher rate than the dielectrics or metals, such as the Bosch process as described in the description of FIG. The dies 12, 14, and 16 may then be removed from the tape 30, as described in the description of FIG.

Because AlN 93 is a dielectric, the AlN can be left on dies 12, 14, and 16. In other embodiments, the AlN 93 may be removed after etching through the substrate 18, such as by using a developer, but this requires additional processing steps. The use of a photo mask developer to remove exposed portions of layer 91 saves processing steps, thereby reducing manufacturing costs. Using the AlN 93 as a mask protects the dielectric 26 from being affected by etching operations.

Those skilled in the art will appreciate that AlN 93 may be used to protect the dielectric 26 in any of the singulation methods described herein, including those described in the description of FIGS. 5 through 7, It will be appreciated that it can be used as a mask and can also be used in the methods described in the description of Figures 8-10.

In other embodiments, the singulation mask may be formed from other materials instead of AlN. Those other materials for the singulation mask are materials that are not substantially etched by the process used to etch the silicon of the substrate 18. [ Because the etch process used to etch the substrate 18 etches the silicon faster than the metals, a metal compound can be used as the material for forming the singulation mask. Examples of such metal compounds include AlN, titanium nitride, titanium oxide, titanium oxynitride, and other metal compounds. In the case of using a metal compound other than AlN, a layer of a metal compound can be applied similar to the layer 91. [ A mask 32 may then be used to pattern the metal compound layer to form openings in the metal compound. The mask 32 may then be removed and during etching of the substrate 18 the remaining portions of the metal compound may protect the underlying layers such as the dielectric 26. The metal compounds may be left on the die after singulation, or may be removed prior to completing the singulation, such as before separating the die from the tape 30.

Silicon-metal compounds can also be used to form the singulation masks because metals in the metal-silicon compound prevent the etch from migrating into the metal-silicon material. Some examples of silicon-metal compounds include silicide metals such as titanium silicide and cobalt silicide. For an embodiment of a silicon-metal compound, a layer of a silicon-metal compound may be formed and patterned similarly to the example of a metal compound. However, the metal-silicon compound is typically a conductor and will have to be removed from the die, such as removing the metal-silicon compound prior to completing the singulation of the die from the tape 30. [

Polymers may also be used in the singulation mask. One example of a suitable polymer is polyimide. Other widely known polymers may also be used. The polymer may be patterned, similar to a metal compound, and then removed or left on the die.

Figure 16 illustrates the steps in an exemplary embodiment of another alternative method for singulating semiconductor dies 12, 14, and 16 that was described in the discussion of Figures 1 and 2-4.

One example of a method of singulating a semiconductor die from a semiconductor wafer, as will be additionally recognized below, is to: < RTI ID = 0.0 > a < / RTI > semiconductor substrate having a semiconductor substrate, Providing a semiconductor wafer having a plurality of semiconductor dies separated from each other by a plurality of semiconductor dies; And etching the singulation line openings through the portions of the semiconductor substrate, wherein the singulation line openings are formed from a first side of the semiconductor substrate, thereby creating a space between the plurality of semiconductor dice , The etching step forms the sidewalls of the semiconductor die, and the top surface of the semiconductor die has a greater width than the bottom surface of the semiconductor die.

In yet another embodiment, the method includes etching the singulation aperture, wherein etching the singulation aperture comprises: providing a width of the upper surface of the die in a range of about a few tens of 2 to 10) microns larger.

Another alternative method includes using an anisotropic etch to etch the singulation line openings into a first distance into the semiconductor substrate; And etching the singulation line opening using an isotropic etch to extend the singulation line opening to a second distance while also increasing the width of the singulation line opening.

As is additionally recognized below, the singulation method forms angled sidewalls for the dies 12, 14, and 16 such that the lateral width of the die is greater at the top of the die than at the bottom of the die It is bigger. The wafer 10 and the dies 12,14 and 16 are etched through the dielectrics 26 and 23 to expose the substrate 18 and pads 24 as described in the description of FIG. Lt; / RTI > is shown in the state of manufacture after the first. Alternatively, the AlN 93 may be used as a mask for subsequent operations as described in the description of Figures 11-14.

After exposing the surface of the substrate 8, the substrate 18 and any exposed pads 24 are exposed at a much higher rate than the dielectrics or metals, as described in the description of FIG. 7, With an isotropic etch process that selectively etches silicon at least fifty (50) and preferably at least one hundred (100) times as fast. The etch process is performed to extend the openings 28 and 28 into the substrate 18 to a depth that laterally extends the width of the openings while also extending the depth to form the openings 100 in the substrate 18. [ do. Because the process is used to form the angled sidewalls for the dies 12,14 and 16 the width of the openings 28 and 29 can be changed continuously as the depth of the openings expands into the substrate 18. [ A number of isotropic teeth will be used. The width of the isotropic apertures 100 is greater than the width of the openings 28 and 29 in the dielectrics 23 and 26. [ Thereafter, a carbon-based polymer 101 is applied to a portion of the substrate 18 exposed in the opening 100.

FIG. 17 shows the subsequent steps of the steps described in the description of FIG. Anisotropic etch is used to remove portions of the polymer 101 on the lower portion of the opening 100 while leaving a portion of the polymer 101 on the sidewalls of the opening 100.

Fig. 18 shows the subsequent steps of the steps described in the description of Fig. The exposed surface of the substrate 18 in the openings 100 and any exposed pads 24 are etched in an isotropic etch process similar to that described in the description of FIG. The isotropic etch again laterally expands the width of the singulation openings 28 and 29, while also extending the depth to form the openings 104 in the substrate 18. The isotropic etch typically ends after the width of the openings 104 is greater than the width of the openings 100 to widen the width of the openings as the depth increases. The portion of the polymer 101 left on the sidewalls of the opening 100 protects the sidewalls of the opening 100 to prevent the etching of the openings 104 from affecting the width of the openings 100. Thereafter, all of the polymer 101 is removed from the sidewalls of the opening 100 during etching of the openings 104.

Thereafter, a carbon-based polymer 105 similar to the polymer 101 is applied to the portion of the substrate 18 exposed in the opening 104. During formation of the polymer 105, operation typically forms the polymer 101 on the sidewalls of the opening 100 again.

FIG. 19 shows another subsequent step of the steps described in the description of FIG. Another anisotropic etch is used to remove the portion of the polymer 105 on the lower portion of the opening 104 while leaving a portion of the polymer 105 on the sidewalls of the opening 104. This etch step is similar to the step described in the description of Fig.

Figure 20 shows that the sequence can be repeated until the singulation lines 13 and 15 have completely penetrated the substrate 18. [ (Such as openings 108 and 112), forming a polymer on the sidewalls of the opening, leaving a portion of the polymer (such as polymers 109 and 113) on the sidewalls, The sequence of anisotropic etching to remove the polymer from the bottom of the openings 28 and 29 extends through the substrate 18 and completely penetrates the substrate 18 to form the singulation lines 13 and 15 Can be repeated until. After the final isotropic etch, such as an etch to form the openings 112, the polymer is typically not deposited, since it would typically not be necessary to protect the substrate 18 during subsequent operations. Although polymers 101, 105, and 109 are shown on the sidewalls of each of the openings 100, 104, and 108, those skilled in the art, after completion of all operations, Lt; RTI ID = 0.0 > etch < / RTI > step substantially removes these polymers from the sidewalls of the corresponding openings. Thus, these polymers are shown for clarity of illustration.

As can be appreciated from Figure 20, the sidewalls of the dies 12, 14, and 16 are tapered inwardly from top to bottom such that the width of the die at the bottom of each die is greater than the width of the die at the top of the die Less than width. The outer edge of the die at the top of the substrate 18 is extended by a distance 116 beyond the outer edge of the die at the top of the substrate 18 so that the top surface of the die 13 is spaced apart by the distance 116 Is hooked on the lower surface (17). In one embodiment, the angled sidewalls facilitate minimizing die damage during the pick-and-place operation of the die. For such an embodiment, it is believed that the distance 116 should be approximately five to ten percent (5 to 10%) of the thickness of the die 12, 14, and 16. The width of the lower portion of the die 12 at the bottom of the substrate 18 is less than the width of the die 11 at the surface 11 since the distance 116 is approximately one to twenty (1-20) microns, in one exemplary embodiment. (2 to 40) microns less than the width at the top of the substrate 12. In another embodiment, the sidewalls need to form an angle 118 of approximately 15 to 40 degrees (15 to 40 degrees) between vertical lines, such as the line perpendicular to the sidewall and the top surface of the substrate 18 . Therefore, the amount by which each etch expands the width of the opening 29 should be sufficient to form the angle 118. In general, the top of the singulation lines 15-16 is about two to forty (2 to 40) microns narrower than the bottom of the singulation lines. Those skilled in the art will appreciate that a number of isotropic etch operations form the coarse sidewalls of each die 12, 14, and 16 such that the sidewalls have jagged edges along them. However, the degree of jagged edges is exaggerated in the Figures of FIGS. 16-21 for clarity of illustration. These sidewalls are generally considered to be substantially smooth sidewalls.

Figure 21 shows dies 12,14, and 16 having sloped side walls during pick-and-place operation. As can be appreciated the inclined sidewalls of the dies 12,14 and 16 allow the plunger to be positioned on the die 12 without collision with other dies such as the dies 14 or 16, To move one of the dies, such as die 12, upward. This helps to reduce chipping and other damage to the dies 12, 14, and 16 during the pick-and-place operation.

Figure 22 shows how other dies without sloped sidewalls and how they can collide with each other during a pick operation. This configuration may result in possible damage to the die, such as the edge of the die, during the pick-and-place operation.

Figure 23 shows the steps in an example embodiment of another alternative method of singulating semiconductor dies 12,14 and 16 and forming angled or sloping side walls as described in the description of Figures 16-22. Respectively. Those skilled in the art will appreciate that other die singulation techniques, such as those described in the discussion of FIGS. 1-15, may also be used to singulate the die from the wafer and to form angled or inclined sidewalls on the die . For example, the anisotropic etch described in the description of FIG. 14 may be used to form the openings 28 and 29 from the top surface of the substrate 18 into the substrate 18 at a first distance 120. Thus, this first distance of the sidewalls has substantially straight sidewalls. The singulation method described in the description of Figs. 16-22 can then be used to complete the singulation. The depth of the first distance 120 depends on the thickness of the die, but will typically be up to about fifty percent (50%) of the thickness of the die. Thereafter, an opening is formed (such as openings 108 and 112), a polymer is formed on the sidewalls of the opening, and a portion of the polymer (such as polymers 109 and 113) A plurality of sequences of anisotropic etches to remove polymer from the bottoms of the openings are formed by the openings 28 and 29 extending through the substrate 18 to completely penetrate the substrate 18 to form the singulation lines 13 and & 15). ≪ / RTI >

Another example of an embodiment of an alternative method of singulating semiconductor dies 12,14 and 16 includes opening 28 and 29 from a top surface of substrate 18 into substrate 18 at a first distance 120, Lt; RTI ID = 0.0 > 14 < / RTI > Thus, this first distance of the sidewalls has substantially straight sidewalls. The isotropic etchant as described in the description of Figures 16 to 22 is then used to etch the first and second portions of the second Can be used to extend the distance. The isotropic etch also increases the width of the lines 13 and 15, while also extending the depth. The width is wider than the width of the openings 28 and 29 in the dielectric 26. The final portion of the method may use anisotropic etch to provide substantially straight sidewalls near the bottoms of the singulation lines. Then, the singulation lines will be wider at the center. Thereafter, an improved function, such as an edge tilt or a die mold lock on the sidewalls of the die 12, 14, and 16, may be used such that the die is wider at the bottom than at the top, This combination or other combinations may be used to provide.

24-28 illustrate cross-sectional views of the wafer 10 at various stages of an example of another alternative embodiment of singulating a semiconductor die from a wafer 10. A cross-sectional view of the wafer 10 shown in FIGS. 24-28 is taken along section line 24-24 of FIG. The exemplary embodiment of the alternative method shown in Figs. 24-28 also includes an alternative method of reducing the thickness or thinning the wafer 10. The wafer 10 includes the semiconductor dies 12,14 and 16 as well as the singulation lines 13 and 15 which have been described in the description of Figures 1 to 4, 8 to 20 and 23 do. Although not shown in Figures 24-28 for clarity of illustration and description, the wafer 10 also includes the singulation lines 43 and 54 and the singulation apertures < RTI ID = 0.0 > 44, and 46 with the first and second ends 47 and 48, respectively. Since the cross-sectional portion of the wafer 10 shown in Fig. 24 is a larger portion of the wafer than that shown in Figs. 2 to 23, Fig. 24 is a cross- (Not shown) formed on the top surface of the wafer 10 with additional singulation lines including singulation lines 11, 17, 137, and 138 similar to either one of 13 and 15 or 43 and 45 Additional die is shown. 24 illustrates that the substrate 18 has a thickness 66 between the top surface of the substrate 18 and the bottom or back surface of the substrate 18. [ After the semiconductor die, such as the dies 12, 14, 16, 144 and 145, is formed on the upper surface of the substrate 18, the wafer 10 is moved to reduce the thickness 66 of the substrate 18 Thinned. An example of one embodiment for reducing thickness 66 is shown in Figs. 25-28.

25, after the semiconductor die is formed on the upper surface of the substrate 18, the wafer 10 is inverted such that the upper surface of the substrate 18 faces the device 34, Or may be attached to the support device 34. Device 34 can be any well known device that can be used to provide support for a wafer during a thinning operation, such as a backgrind tape or other device.

Figure 26 shows a wafer 10 in a subsequent stage of an exemplary embodiment of a method for singulating die from a wafer 10. The entire lower surface of the wafer 10 is thinned to reduce the thickness of the wafer 10 from the thickness 66 to a thickness 67 less than the thickness 66. [ Various widely known methods, such as backgrinding, chemical mechanical polishing (CMP), or other techniques widely known to those skilled in the art reduce the thickness of the wafer 10 to a thickness 67 . In some embodiments, this step in the method may be omitted.

The inner portion 125 of the lower surface of the wafer 10 is then further reduced to a thickness 68 less than the thicknesses 66 and 67. The portion of the lower surface of the wafer 10 that is removed during formation of the inner portion 125 is shown in dashed lines. The thickness of the inner portion 125 is typically reduced by subjecting the inner portion 125 to grinding operations or other well known techniques to reduce thickness. Reducing the thickness of the portion 125 leaves an outer rim 127 juxtaposed to the outer periphery of the wafer 10. Thus, the outer rim 127 typically maintains a thickness 67. [ The width of the outer rim 127 is sufficient to provide support for handling or transporting the remainder of the wafer 10. Tools and methods for reducing the thickness of the inner portion 125 are well known to those skilled in the art. One example of such a tool and method is disclosed in U.S. Patent Application No. 2006/0244096, Kazuma Sekiya, published November 2, 2006.

FIG. 27 shows another subsequent step of singulating die from the wafer 10. The support device 34 can be removed from the wafer 10 and a protective layer 135 is applied to the lower surface of the wafer 10 and especially to the lower surface of the wafer 10 in the interior portion 125. The device 34 may have an ultraviolet release mechanism, such as that released when exposed to ultraviolet light, or another widely known release mechanism. The device 34 is removed because the methods of forming the layer 135 typically involve high temperatures that can damage the device 34. For embodiments that do not include such high temperatures, or for support devices that can withstand these temperatures, the device 34 may be retained. However, device 34 typically must be removed prior to subsequent operations. A portion of the layer 135 may also be applied to the lower surface of the outer rim 127, as shown by the protective layer portion 133. [ However, in some embodiments, the outer rim 127 may be masked to prevent forming the portion 133. For example, a shadow mask may be used during operation to form the layer 135 to prevent forming the portion 133, or a photomask may be applied to cover the rim 127 .

Figure 28 shows the wafer 10 in yet another subsequent manufacturing step. After forming the layer 135, the wafer 10 is typically inverted into the upright state again. The carrier tape 30 is applied to the lower surface of the wafer 10. [ In some embodiments, a tape 30 is attached to a film frame 62 to provide support for the tape 30. Such film frames and carrier tapes are well known to those skilled in the art. The tape 30 is applied as a vehicle for handling and transporting the wafer 10. For embodiments that use different carriers to handle the wafer 10, different carriers may be used and the tape 30 may be omitted. Typically, a vacuum chuck (not shown) is provided to hold the wafer 10 and allow the tape 30 to conform to the shape of the lower surface of the wafer 10 so that the tape 30 provides some support for the wafer 10. [ vacuum chuck is used. It is then possible to terminate on layer 135 in a manner similar to openings 28 and 29 or openings 47 and 48 terminating on layer 27 as described in the description of Figures 2 to 23, The formation openings 28, 29, 140, and 141 are formed into the substrate 18 from the top surface of the wafer 10. Those skilled in the art will appreciate that other singulation apertures are typically formed simultaneously with the openings 28 and 29 to singulate the other die of the wafer 10. Layer 135 is formed from a material that is not etched by dry etch methods used to form singulation openings 28, 29, 140, and 141. In one embodiment, the protective layer 135 is a metal or metal compound, and the dry etch process is selected to be a process that etches silicon at a much higher rate than metals. Such processes have been described above. In other embodiments, the protective layer 135 may be aluminum nitride as described above or a silicon-metal compound as described above. The layer 135 may also be the same material as the material of the metal layer 27 described above. The singulation openings 140 and 141 may also be formed with the singulation openings 28 and 29. The singulation openings 140 and 141 are formed to penetrate the substrate 18 in the same manner as the openings 28 and 29 (or openings 47 and 48) to form the singulation lines 137 and 138 . Singulation lines 137 and 138 are formed to separate the outer rim 127 from the remainder of the wafer 10. As a result, the singulation lines 137 and 138 typically lie on the inner portion 125 and are spaced apart from the outer rim 127 and any of the semiconductor die 144 and 145, Are formed to be positioned between the semiconductor dies. For example, the singulation lines 137 and 138 may have one (1) extension extending around the outer edge of the inner portion 125, such as just inside the portion of the wafer 10 where the inner circumference of the outer rim 127 is formed. ) May be a continuous singulation line.

Those skilled in the art will appreciate that the use of a wafer saw or other type of cutting tool to singulate a die from a wafer having such inner portion 125 and rim 127 will cause the inner portion 125 to undergo many mechanical stresses, And will probably destroy the wafer 10 within the interior portion 125. In addition, laser scribing to remove rim 127 may result in re-crystallization of the die adjacent rim 127. [ Using the dry etch methods described herein to remove the rim 127 minimizes mechanical stresses on the inner portion 125 during removal of the rim 127 or while singulating the die from the wafer 10 , Thereby reducing wafer breakage.

There may be cases where it is desirable to remove the rim 127 from the wafer 10 without singulating the die formed on the wafer 10. For such an alternative embodiment, instead of forming the singulation lines for singulating the die of the wafer 10, such as the singulation lines 11, 13, 15, and 17, the singulation lines 137 And 138 may be formed to remove the rim 127 from the wafer 10. After removing the rim 127 another tape similar to the tape 30 may be applied to the lower surface of the portion 125, such as directly to the layer 135, after which the die is described herein Can be singulated as described above. In other embodiments, the tape 30 may be retained to support the remainder of the wafer 10. Removing the rim 127 prior to singulating the die allows for a fast and clean way to improve yield and throughput by reducing scratches and mechanical stresses.

29-31 illustrate various steps of yet another alternative embodiment of an example of a method for singulating die from a wafer 10. Fig. 29 shows the wafer 10 at the stage immediately after the step described in the description of Fig. The wafer 10 is removed from the support device 34 and a protective layer 135 is formed on the lower surface of the inner portion 125. [

Referring to Figure 30, a carrier tape 63 may be applied to the wafer 10 to provide support for the wafer 10. The carrier tape 63 is applied to the top of the wafer 10 so that the upper surface of the substrate 18 faces the tape 63. [ The tape 63 is typically similar to the tape 30 described above. In some embodiments, the tape 63 is attached to a film frame 64 similar to the frame 62. The tape 63 is applied as a vehicle that handles and supports the wafer 10. For embodiments that use different carriers to handle the wafer 10, different carriers may be used, and the tape 63 may be omitted. Any portion of the protective layer 135 formed on the bottom surface of the outer rim 127 is removed, as shown by dashed lines, For example, the bottom surface of the outer rim 127 may undergo a grinding process for a sufficient time to remove the protective layer portions 133 as shown by dashed lines, or the layer 135 may be masked Portions 133 may be etched away from rim 127. As discussed above, in some embodiments, the protective layer portions 133 are not formed on the outer rim 127.

A dry etch process may be used to reduce the thickness of the outer rim 127 to thickness 69. [ The dry etch process used to reduce the thickness of the outer rim 127 is similar to that of the dry etch processes described herein, such as the dry etch processes used to form singulation openings such as the singulation openings 28 and 29 It can be either. The thickness 69 is less than the previous thickness 67 of the outer rim 127. The value of thickness 69 is typically chosen such that the lower surface of the outer rim 127 is close to thickness 68 so that the carrier tape 30 (see FIG. 31) provides better support for the wafer 10 . In a preferred embodiment, the thickness 69 forms the lower surface of the rim 127 substantially parallel to the outer surface of the protective layer 135. Portions 133 are removed to reduce the thickness of the dry rim 127. As long as portions 133 are removed prior to reducing the thickness of rim 127, portions 133 can be removed at different stages of the method. In some embodiments, thickness 68 is no more than about fifty (50) microns, and may be less than twenty-five (25) microns. Those skilled in the art will recognize that at such thicknesses, the wafer 10 can be fragile. Using a dry etch process to reduce the thickness of the rim 127 minimizes mechanical stresses on the wafer 10, as compared to other thickness reduction methods such as back grinding or CMP.

Figure 31 shows the wafer 10 in a subsequent step. After reducing the thickness of the outer rim 127, the wafer 10 is typically inverted and placed on the carrier tape 30 as described above. The singulation openings 28 and 29 are formed through the substrate 18 from the top surface of the substrate 18 and are suspended on the protective layer 135. Singulation openings 140 and 141 are also typically formed with openings 28 and 29 to separate the outer rim 127 from the semiconductor die of the wafer 10. Those skilled in the art will appreciate that other singulation apertures are typically formed simultaneously with the openings 28 and 29 to singulate the other die of the wafer 10. Because of the small thickness of the wafer 10, using a dry etch to singulate the die minimizes mechanical stresses on the wafer 10 and reduces fracture and other damage.

32 and 33 illustrate various steps of an exemplary embodiment of another alternative method of singulating die from wafer 10. [ Fig. 32 shows the wafer 10 at the stage immediately after the step described in Fig. The device 34 is generally removed from the wafer 10 and a protective layer 135 is formed on the lower surface of the inner portion 125, as described above. The protective layer 135 is substantially aligned with the portion of the wafer 10 on which the singulation lines of the wafer 10 should be formed, such as the singulation lines 11, 13, 15, 17, 137, May be patterned to have openings through protective layer 135. Those skilled in the art will appreciate that the openings formed in the layer 135 may be formed on a variety of backplanes to ensure that alignment lines, such as the singulation lines 13, 15, 137, and 138, It will be appreciated that alignment techniques may be used.

Referring to Figure 33, a dry etch process is performed to expose the substrate 18 from the lower surface of the substrate 18 and extend through the singulation openings 28, 29, 140, And 141, a protective layer 135 may be used as a mask to protect the substrate 18. [ Any of the described dry etch methods for forming the singulation openings 28 and 29 or 47 and 48 may also be used to etch through the singulation openings 140 and 141 and any other singulation < RTI ID = 0.0 > Can be used to form openings. While forming the singulation openings, the process also reduces the thickness of the outer rim 127 to a thickness 69 by etching the outer rim 127. Any portion of the protective layer portion 133 is removed prior to reducing the thickness of the rim 127 and etching the singulation openings, as described above in the description of FIG. Reducing the thickness of the portion 127 along with forming the singulation openings reduces manufacturing costs by reducing processing steps and reducing the thickness also improves yield by minimizing mechanical stress on the wafer 10 Thereby reducing costs. The reduced thickness of the rim 127 makes it easier to handle the wafer 10 and to remove the die after the dies are singulated. In other embodiments, the rim 127 may be masked and not etched while forming the openings 28, 29, 140, and 141. Another carrier tape (not shown), such as a carrier tape 30, may be applied to the lower surface of the wafer 10, such as the lower surface of the inner portion 125, after forming the singulation apertures, The wafer 10 or the inner portion 125 can be inverted. The semiconductor die may then be removed by pick-and-place or other techniques as described above.

One skilled in the art will appreciate that one example of a method of forming a semiconductor die is a semiconductor substrate having a first thickness, an upper surface, a lower surface, and a second semiconductor layer formed on the upper surface of the semiconductor substrate, Providing a semiconductor wafer having a plurality of semiconductor dies, such as dies 12, 14, or 16, which are separated from each other by portions of the semiconductor wafer on which the lines should be formed; Inverting the semiconductor wafer; Such as a portion 125 of the lower surface of the semiconductor wafer, to a second thickness that is less than the first thickness, and the outer rim of the semiconductor wafer, e.g., rim 127, 1 thickness, wherein the outer rim is juxtaposed to a periphery of the semiconductor wafer, and wherein the inner portion lies below the plurality of semiconductor die, wherein the thickness of the inner portion is less than a second thickness Reducing the outer rim to a first thickness; Forming a protective layer that is one of a metal or a metal compound or a metal-silicon compound on the inner portion of the lower surface of the semiconductor wafer; And using a dry etch to reduce the first thickness of the outer rim to a third thickness less than the first thickness, wherein the protective layer protects the inner portion from the dry etch, It will be appreciated that the second thickness remains substantially constant.

One skilled in the art will recognize that the method may also include patterning the protective layer to expose portions of the semiconductor substrate over which the singulation lines are to be formed; And using the dry etch to etch the singulation lines from the lower surface of the semiconductor substrate to the upper surface of the semiconductor substrate through the semiconductor substrate.

An example of yet another method of forming a semiconductor die is as follows: a semiconductor substrate having a first thickness, an upper surface, a lower surface, and portions of a semiconductor wafer formed on the upper surface of the semiconductor substrate and on which the singulation lines are to be formed Providing a semiconductor wafer having a plurality of semiconductor dies, such as a die 12/14/16, separated from each other by portions such as a semiconductor chip 13/15; Reducing the thickness of an interior portion, such as portion (125) of the lower surface of the semiconductor wafer, to a second thickness that is less than a first thickness, and forming an outer rim, such as rim (127) Wherein the outer rim is juxtaposed to the rim of the semiconductor wafer and the inner portion lies below the plurality of semiconductor dies, the thickness of the inner portion being reduced to a second thickness less than the first thickness, Leaving the rim at a first thickness; Forming a protective layer that is one of a metal or a metal compound or a metal-silicon compound on the inner portion of the lower surface of the wafer; And using a dry etch to form singulation openings in which singulation lines are to be formed, said method comprising the step of using said dry etch through said semiconductor substrate to form said singulation openings, One singulation opening is formed between the outer rim and one of the semiconductor dies adjacent to the outer rim.

Those skilled in the art will also appreciate that the method may also include using a dry etch to form a singulation aperture through the semiconductor substrate from the upper surface of the semiconductor wafer.

The method also includes patterning the protective layer to expose portions of the lower surface of the semiconductor wafer on which the singulation lines are to be formed; And using a dry etch to form the singulation openings, wherein the dry etch using step includes passing the singulation openings through the semiconductor substrate from the lower surface of the semiconductor wafer to the semiconductor substrate Using the dry etch to etch to the top surface, using the protective layer as a mask, and etching the outer rim and etching the first thickness of the outer rim to a third thickness less than the first thickness And using the dry etch to reduce the etch rate.

In view of all of the above, it is clear that a novel apparatus and method are disclosed. Among other features, etching the singulation openings completely through the semiconductor wafer using a dry etch process is included. Such dry etch procedures are generally referred to as plasma etching or reactive ion etching (RIE). Etching openings from one side helps to ensure that the singulation openings have nearly straight sidewalls thereby providing a uniform singulation line along each side wall of each semiconductor die. Fully penetrating the semiconductor wafer to etch the singulation openings facilitates forming narrow singulation lines, thereby allowing room for use in forming a semiconductor die on a given wafer size. Both singulation lines are formed simultaneously. The etching process is faster than the scribing or wafer sawing process, thereby increasing the throughput of the manufacturing area.

Formation of the singulation lines through the filler material of the trench facilitates forming narrow singulation lines, thereby increasing wafer availability and reducing costs. The use of a singulation mask helps protect the interior portions of the die while forming the singulation lines through the substrate. Formation of angled sidewalls reduces damage during assembly operations, thereby reducing costs. In some embodiments, sloped sidewalls are generally formed on both die at the same time.

While the subject matter of the present invention has been described in conjunction with specific preferred embodiments, many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, the layers 20 and / or 21 may be omitted from the substrate 18. The singulation apertures may alternatively be formed before or after forming the contact openings overlying the pads 24. Also, the singulation openings may be formed prior to thinning the wafer 10, e.g., the singulation openings may be formed partially through the substrate 18, and a thinning process may be applied to the bottom of the singulation openings Lt; / RTI >

10: Semiconductor wafer
12, 14, 16, 42, 44, 46, 71, 72, 73:
13, 15, 43, 45, 137, 138: singulation line 19: bulk substrate
20: epitaxial layer 23, 26: dielectric
24: contact pad 32: mask
50, 54, 58: Insulation trench 105: Polymer
135: Protective layer
144, 145: semiconductor die

Claims (5)

A method for singulating a plurality of semiconductor dies from a semiconductor wafer, comprising:
Providing a semiconductor wafer having the plurality of semiconductor dies, the semiconductor wafer comprising a first major surface and a second major surface opposite the first major surface, wherein a metal layer Providing the semiconductor wafer;
Positioning a first carrier tape adjacent the metal layer;
Creating a space between the plurality of semiconductor dies by penetrating portions of the semiconductor wafer but without plasma penetrating the metal layer to form a singulation line opening; And
Blowing an air jet onto a portion of the first carrier tape underlying the semiconductor die of the plurality of semiconductor dies, including blowing an air jet substantially perpendicular to the second major surface of the semiconductor die , Moving the first carrier tape upward and into the space to cut the metal layer lying below the space and leaving a portion of the metal layer below the space on the first carrier tape Wherein the plurality of semiconductor dies are electrically coupled to the plurality of semiconductor dice. The method according to claim 1,
Further comprising positioning a second carrier tape on the first major surface of the semiconductor wafer and thereafter removing the first carrier tape. A method for singulating a plurality of semiconductor dies from a semiconductor wafer, the method comprising:
Providing a semiconductor wafer, wherein a metal layer is formed along a primary surface and a first carrier tape adjacent the metal layer, the semiconductor wafer having singulation line openings through portions of the semiconductor wafer, Creating a space between the dies; providing the semiconductor wafer; And
Directly blowing an air jet onto a portion of the first carrier tape underlying the semiconductor die such that the air jet is blown substantially perpendicular to the major surface of the semiconductor die, And blowing the air jet directly where the metal layer is cut. The method according to claim 1,
Further comprising stretching said first carrier tape upwardly into said singulation line opening to cut said metal layer underlying said singulation line opening. ≪ Desc / Clms Page number 21 > A method of singulating a substrate comprising:
Providing a substrate having a plurality of dies formed on the substrate and separated from one another by singulation lines, the substrate having a first major surface and a second major surface opposite the first major surface, Providing a substrate having a metal layer formed on the second major surface and the singulation lines terminating proximate to the metal layer;
Providing the substrate affixed to the first side of the carrier tape; And
And directing an air jet onto the carrier tape to cut the metal layer underlying the singulation lines by singulating portions of the metal layer from the singulation lines. ≪ Desc / Clms Page number 21 >

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