TWI671813B - Semiconductor wafer manufacturing method - Google Patents

Abstract

Embodiments of the present invention relate to a method for manufacturing a semiconductor wafer, a semiconductor wafer, and a semiconductor device.

The method for manufacturing a semiconductor wafer according to an embodiment includes the steps of forming a plurality of etching masks each including a protective film on a semiconductor substrate, and delimiting a plurality of first regions protected by the plurality of etching masks on the semiconductor substrate And the second region that is an exposed region in the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process to form at least a portion that is located on the same surface as the end surface of the etching mask. The inner side wall and the plurality of grooves reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions.

Description

Manufacturing method of semiconductor wafer

This application is based on and claims the benefit of priority from Japanese Patent Application No. 2013-235470, filed on November 13, 2013, the entirety of which is incorporated herein by reference.

Embodiments of the present invention relate to a method for manufacturing a semiconductor wafer, a semiconductor wafer, and a semiconductor device.

When a semiconductor substrate is singulated into a wafer, a blade that mechanically cuts the wafer by a rotating blade is usually used. In blade cutting, a plurality of cutting grooves are sequentially formed on a semiconductor substrate, and the semiconductor substrate is singulated into a wafer. Therefore, blade cutting has a problem that if the wafer size is reduced and the number of cutting grooves (number of lines) increases, the cutting time becomes longer in proportion to the number of lines.

Moreover, the corners of the wafer obtained by dicing with a blade are right-angled, and impact resistance is low. In addition, since the blade cutting produces minute defects (cracks) at the ends of the wafer, the bending strength of the wafer obtained by this is low.

In addition, in recent years, the idea of forming deeper holes with a high aspect ratio by chemical action on a single crystal substrate has been proposed.

The problem to be solved by the present invention is to provide a method capable of manufacturing a semiconductor wafer with high productivity.

According to an embodiment, a method for manufacturing a semiconductor wafer includes the steps of forming a plurality of etching masks each including a protective film on a semiconductor substrate, and delimiting a plurality of first ones of the semiconductor substrate protected by the plurality of etching masks The second region is the region and the exposed region in the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process so as to have at least a portion located on the same end face of the etching mask The in-plane side walls and the plurality of grooves reaching the bottom of the back surface of the semiconductor substrate thereby singulate the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions.

With the above configuration, a method capable of manufacturing a semiconductor wafer with high productivity can be provided.

10‧‧‧ semiconductor substrate

10'‧‧‧Chip body

12‧‧‧component area

14‧‧‧ Etching Mask

15‧‧‧ insulating film

16‧‧‧ protective film

18‧‧‧ exposed area

18'‧‧‧ exposed area

20‧‧‧cut sheet

22‧‧‧precious metal catalyst

22a‧‧‧Ag particles

24‧‧‧ separation groove

24a‧‧‧Deep Trench

26‧‧‧ Needle Residue

28‧‧‧Semiconductor wafer

28'‧‧‧Semiconductor wafer

29‧‧‧ side

30‧‧‧etching solution

31‧‧‧ side

32‧‧‧etch marks

34‧‧‧Joint material

35‧‧‧ substrate

36‧‧‧Solder

40‧‧‧semiconductor device

41a‧‧‧lead frame

41b‧‧‧lead frame

43‧‧‧Joint material

45‧‧‧Al line

47a‧‧‧moulding resin

47b‧‧‧moulding resin

51‧‧‧electrode pad

52‧‧‧electrode protection layer

54‧‧‧ Insulation

55‧‧‧Wiring layer

57‧‧‧Metal catalyst film

57'‧‧‧Metal catalyst film

58‧‧‧ resist pattern

59‧‧‧semiconductor wafer

70‧‧‧ metallization

72‧‧‧ substrate polishing device

A‧‧‧Area

B‧‧‧ area

C1‧‧‧ Corner

C2‧‧‧ Corner

FIG. 1 is a plan view of a semiconductor substrate on which an etching mask is formed.

FIG. 2 is a sectional view showing a part of the semiconductor substrate shown in FIG. 1. FIG.

FIG. 3A is a plan view showing an example of the shape of an etching mask.

FIG. 3B is a plan view showing another example of the shape of the etching mask.

FIG. 3C is a plan view showing another example of the shape of the etching mask.

FIG. 3D is a plan view showing another example of the shape of the etching mask.

FIG. 3E is a plan view showing still another example of the shape of the etching mask.

FIG. 4 is a sectional view showing a step subsequent to the step of FIG. 2.

5 is a plan view of a semiconductor substrate provided with a precious metal catalyst.

FIG. 6 is a diagram showing a precious metal catalyst disposed in an exposed area.

Fig. 7 is a scanning electron microscope (SEM) photograph of Ag nanoparticle catalyst.

FIG. 8 is a SEM photograph showing the results of replacement plating.

FIG. 9 is a sectional view showing a step subsequent to the step of FIG. 4.

FIG. 10 is a plan view of a semiconductor substrate on which a deep trench is formed.

FIG. 11 is a cross-sectional SEM photograph of the silicon substrate after the etching process.

FIG. 12 is a sectional view showing a step subsequent to the step of FIG. 9.

FIG. 13 is a plan view of a semiconductor substrate having needle-shaped residues.

FIG. 14 is a perspective view showing an example of a semiconductor wafer obtained by singulation.

15A is a cross-sectional view showing a step of a method for manufacturing a semiconductor wafer according to an embodiment.

FIG. 15B is a sectional view showing a step subsequent to the step of FIG. 15A.

FIG. 15C is a sectional view showing a step subsequent to the step of FIG. 15B.

Fig. 15D is a cross-sectional view showing a step subsequent to the step of Fig. 15C.

FIG. 15E is a sectional view showing a step subsequent to the step of FIG. 15D.

FIG. 16 is a plan view showing a semiconductor wafer group obtained by singulation.

FIG. 17A is a perspective view schematically showing an example of an etching mark.

FIG. 17B is a perspective view schematically showing another example of the etching mark.

FIG. 17C is a perspective view schematically showing still another example of the etching mark.

FIG. 18 is a cross-sectional view of a semiconductor device according to an embodiment.

FIG. 19 is a cross-sectional view of a semiconductor device according to another embodiment.

FIG. 20 is a sectional view of a semiconductor device according to still another embodiment.

21A is an enlarged cross-sectional view showing an example of a wafer body including an electrode pad.

21B is an enlarged cross-sectional view showing an example of a wafer body covered with an electrode pad with an electrode protection layer.

FIG. 22 is an enlarged sectional view showing an insulating film and the like of a wafer body.

FIG. 23A is a cross-sectional view showing the steps of a method of manufacturing a semiconductor wafer according to another embodiment.

FIG. 23B is a sectional view showing a step subsequent to the step of FIG. 23A.

Fig. 23C is a cross-sectional view showing a step subsequent to the step of Fig. 23B.

24A is a cross-sectional view showing a step of a method for manufacturing a semiconductor wafer according to another embodiment.

Fig. 24B is a plan view showing the step of Fig. 24A.

FIG. 25A is a sectional view showing a step subsequent to the step of FIG. 24A.

Fig. 25B is a plan view showing the step of Fig. 25A.

Fig. 26A is a cross-sectional view showing a step subsequent to the step of Fig. 25A.

Fig. 26B is a plan view showing the step of Fig. 26A.

FIG. 27A is a sectional view showing a step subsequent to the step of FIG. 26A.

Fig. 27B is a plan view showing the step of Fig. 27A.

FIG. 28A is a sectional view showing a step subsequent to the step of FIG. 27A.

Fig. 28B is a plan view showing the step of Fig. 28A.

FIG. 29A is a sectional view showing a step subsequent to the step of FIG. 28A.

Fig. 29B is a plan view showing the step of Fig. 29A.

FIG. 30 is a cross-sectional view showing another example of a semiconductor substrate.

Fig. 31A is a sectional view showing a step of a method according to another embodiment.

FIG. 31B is a sectional view showing a step subsequent to the step of FIG. 31A.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor substrate used in a method of an embodiment. FIG. 2 is a partial cross-sectional view of the semiconductor device of FIG. 1. FIG.

As shown in the figure, a plurality of element regions 12 each including one or more semiconductor elements are provided on the semiconductor substrate 10. The element regions 12 are arranged spaced apart from each other. Each element region 12 is protected by being covered with an etching mask 14.

The semiconductor element included in the element region 12 is, for example, a transistor, a diode, a light emitting diode, or a semiconductor laser. The element region 12 may further include a capacitor, wiring, or the like.

A region between adjacent element regions 12 is an exposed region 18 on which the surface of the semiconductor substrate 10 is exposed. As described later, a noble metal catalyst is disposed in the exposed area 18. In this embodiment, the semiconductor is chemically etched using a precious metal catalyst and an etching solution. The exposed area 18 of the substrate 10 is removed, thereby obtaining a semiconductor wafer obtained by singulation.

In the example shown in FIG. 2, the etching mask 14 is composed of a laminated structure of an insulating film 15 and a protective film 16. Although the insulating film may be referred to as a kind of protective film, the electrode pad (not shown) of the element region 12 can be reliably protected by providing the insulating film 15. If necessary, the etching mask 14 may be formed of any of an insulating film and a protective film.

Furthermore, it is preferable to affix a dicing sheet 20 for holding the wafer obtained by singulation in advance on the back surface of the semiconductor substrate 10.

The semiconductor substrate 10 can be selectively etched by the effect of a noble metal catalyst. For example, the semiconductor substrate 10 can be selected from Si, Ge, and III-V semiconductors, i.e., semiconductors containing a group III element and a V element (such as GaAs, GaN, etc.) and SiC and other materials. The term "family" as used herein refers to the "family" of the short-period periodic table.

The thickness of the semiconductor substrate 10 is not particularly limited as long as it is appropriately determined according to the size of the target semiconductor wafer. The thickness of the semiconductor substrate 10 can be set in a range of, for example, 50 μm to 500 μm. Similarly, the doping amount of impurities into the semiconductor substrate 10 is not particularly limited as long as it is appropriately determined. The main surface of the semiconductor substrate 10 may be parallel to any crystal plane of the semiconductor.

The etching mask 14 is selectively formed on a plurality of regions on the upper surface of the semiconductor substrate 10 so as to cover the element region 12. The shape of the upper surface of each etching mask 14 is not limited to a rectangular shape, and may be various shapes as shown in FIGS. 3A to 3E.

In the case where the etching mask 14 is formed to have rounded corners as shown in FIG. 3A, the corners also become rounded in the wafer obtained by singulation. In other words, such an upper surface shape of the etching mask 14 and the semiconductor wafer is a shape which does not have a portion where the straight lines (line segments) constituting the contour are in contact with each other, that is, a shape where the line segments constituting the contour are separated from each other. By making the corners round, the mechanical strength of the wafer can be improved.

The upper surface of the etching mask 14 may also be a polygon having 5 sides or more. For example, in the example shown in FIG. 3B, the etching masks 14 each have a hexagonal upper surface, and Configured in a honeycomb shape. When the etching mask has such an upper surface shape, a semiconductor wafer having an upper surface of a polygon having 5 sides or more can be obtained. Compared with a semiconductor wafer having a polygonal internal angle of 90 °, a semiconductor wafer having a polygonal internal angle greater than 90 ° has a higher mechanical strength.

The etch mask 14 may also have a circular upper surface as shown in FIG. 3C. When the etching mask has such an upper surface shape, a semiconductor wafer having a circular upper surface can be obtained. A semiconductor wafer having a circular upper surface has a mechanical strength equal to or higher than that of a semiconductor wafer having a rectangular upper portion having a rounded corner.

When the shape of the upper surface of the semiconductor wafer has rotational symmetry, the azimuth alignment cannot be performed based only on the shape of the upper surface of the semiconductor wafer. As shown in FIG. 3E, if the upper surface of the etching mask 14 is formed into a shape having no rotational symmetry, a semiconductor wafer having a shape having no upper surface having rotational symmetry can be obtained. Such a semiconductor wafer can be aligned with its orientation only based on the shape of the upper surface, for example. In addition, the shape having no rotational symmetry is not particularly limited, and examples thereof include shapes having a shape of one corner or more different from those of other corners, or shapes having a notch.

The etching masks formed on the semiconductor substrate need not all have the same shape. The etching mask 14 may also be formed into a pattern having a different shape as shown in FIG. 3D.

When an etching mask of any shape is used, the semiconductor wafer is singulated so as to have a shape that faithfully reflects the upper surface shape of the upper surface shape of the mask.

The material of the insulating film 15 is not particularly limited as long as it can suppress the attachment of a noble metal catalyst to the semiconductor substrate, and any one of organic and inorganic insulating materials may be used. Examples of the organic insulating material include organic resins such as polyimide, fluororesin, phenol resin, and epoxy resin. Examples of the inorganic insulating material include an oxide film and a nitride film. The insulating film 15 need not necessarily be formed on the element region 12 separately. A part of the insulating film constituting the element region 12 may be used as the insulating film 15.

Furthermore, an insulating film is used as an insulating film, such as an organic resin. In this case, the insulating film may be left as a permanent film in the final product. If the remaining insulating film is used as an impact absorbing film of a singulated wafer, the upper surface of the singulated wafer is completely covered with the impact absorbing film, so the mechanical strength of the wafer can be improved.

The material of the protective film 16 is not particularly limited as long as it is not eroded by the etchant. For example, the protective film 16 can be formed using an organic resin such as polyimide, a fluororesin, a phenol resin, and an epoxy resin, or a noble metal such as Au, Ag, and Pt.

The exposed area 18 is used for singulation of a semiconductor wafer and corresponds to a so-called dicing line. The width of the exposed region 18 is not particularly limited, and is, for example, in a range of 1 μm to 200 μm.

A noble metal catalyst 22 is arranged in the exposed area 18 as shown in FIG. 4. Here, the etching mask 14 functions as a mask for preventing the noble metal catalyst 22 from being attached to a portion other than the exposed area 18. FIG. 5 is a plan view of the semiconductor substrate 10 in which the precious metal catalyst 22 is disposed in the exposed area 18.

The precious metal catalyst 22 activates the oxidation reaction of the semiconductor substrate 10 in contact with the precious metal catalyst. Any precious metal having an effect of activating the oxidation reaction can be used as the precious metal catalyst 22. The material of the noble metal catalyst 22 may be selected from, for example, Au, Ag, Pt, and Pd.

The precious metal catalyst 22 may be arranged in a granular shape, for example. A granular noble metal catalyst is preferred because it is also stable during etching. Examples of the shape of the granular catalyst include a spherical shape, a rod shape, and a plate shape. In the case of a spherical shape, it is preferable because the direction in which the semiconductor substrate is etched is close to vertical. The particle diameter of the granular catalyst is not particularly limited, and may be in the range of, for example, tens of nm to hundreds of nm. In addition, in order to easily perform wafer division after etching, the granular catalyst is preferably arranged at a high density or in a multilayer.

FIG. 6 is a schematic view showing a part of the upper surface of the semiconductor substrate 10 in which the granular noble metal catalyst 22 is arranged in the exposed area 18.

The noble metal catalyst can be disposed on the exposed region 18 of the semiconductor substrate 10 by, for example, electrolytic plating, reduction plating, and replacement plating. Also, precious metals can be used. Coating, evaporation, sputtering, etc. of particle dispersion. In these methods, when replacement plating is used, a granular noble metal catalyst can be formed directly and uniformly in the exposed area 18 corresponding to the cutting line.

When disposing a granular noble metal catalyst by displacement plating, for example, a silver nitrate solution can be used. An example of this process will be described below. As the replacement plating solution, for example, a mixed solution of a silver nitrate solution, hydrofluoric acid, and water can be used. Hydrofluoric acid has the effect of removing the natural oxide film on the surface of the semiconductor substrate.

The silver nitrate concentration in the replacement plating solution is preferably in the range of 0.001 mol / L to 0.1 mol / L, and more preferably in the range of 0.005 to 0.01 mol / L. The hydrogen fluoride concentration in the replacement plating solution is preferably in the range of 1 mol / L to 6.5 mol / L.

By immersing the semiconductor substrate 10 which is selectively protected by the etching mask in a specific area for about 1 to 5 minutes as described above, the semiconductor substrate 10 can be selectively used only in the exposed area 18 of the semiconductor substrate 10. Ag nanoparticles of the granular noble metal catalyst 22 precipitate. The temperature of the replacement plating solution is not particularly limited, and may be appropriately set to, for example, 25 ° C, 35 ° C, or the like.

FIG. 7 shows a SEM image of a sample in which Ag nanoparticle groups are formed on a silicon substrate by displacement plating. Here, a single crystal silicon substrate protected by an etching mask in a specific region is immersed in a replacement plating solution at 25 ° C. for 3 minutes, thereby forming Ag nano particles in the exposed region of the single crystal silicon substrate.

As the etching mask, an insulating film containing a polyfluorene film was used, and as a replacement plating solution, an aqueous solution containing 0.005 mol / L silver nitrate and 5.0 mol / L hydrogen fluoride was used. In the SEM image of FIG. 7, the Ag nano-particles 22 a corresponding to the granular noble metal catalyst 22 are shown as white areas. The Ag nanoparticle 22 has a particle diameter of about 100 nm.

The particle diameter of the Ag nanoparticle 22 can be controlled by, for example, changing the immersion time or replacing the concentration of the plating solution. The particle diameter of the Ag nanoparticle is preferably about several tens to several hundreds of nm. It was confirmed that if Ag nano particles having a particle size in this range were formed, they were immersed in an etching solution. In this case, the etching of the semiconductor substrate proceeds well.

Moreover, the entire surface of the exposed area of the single crystal silicon substrate may not be completely covered by Ag nano particles. A part of the surface of the semiconductor substrate 10 is shown as a black area in a part of the SEM image in FIG. 7.

Here, an example of a result obtained by immersing a Si substrate in various replacement plating solutions having different compositions for one minute is summarized in FIG. 8. The concentration of the silver nitrate solution in the replacement plating solution is set to 0.001 to 0.05 mol / L, the concentration of hydrogen fluoride is set to 3.5 to 6.5 mol / L, and the temperature of the replacement plating solution is 25 ° C.

No matter what the concentration of hydrogen fluoride in the replacement plating solution is in the range of 3.5 to 6.5 mol / L, when the concentration of silver nitrate is greater than or equal to 0.03 mol / L, the crystals of Ag grow in a tree shape. When the concentration is 0.005 to 0.01 mol / L, the formation of Ag nano particles having a particle diameter of about 10 to 100 nm can be confirmed. In order to obtain Ag nano-particles having a desired particle diameter, the composition and temperature of the replacement plating solution, the immersion time, and the like may be appropriately set to perform the replacement plating.

As shown in FIG. 9, the semiconductor substrate on which the precious metal catalyst 22 is arranged is immersed in the etching solution 30. As the etching solution 30, a mixed solution containing hydrofluoric acid and an oxidizing agent is used. By the action of the noble metal catalyst 22, the semiconductor substrate 10 is oxidized only at the portion (exposed area 18) that is in contact with the noble metal catalyst 22. The oxidized area of the semiconductor substrate 10 can be dissolved and removed by hydrofluoric acid, and only the portion in contact with the granular noble metal catalyst 22 can be selectively etched. That is, the etching of the exposed region 18 is performed anisotropically.

When the semiconductor substrate 10 is selectively dissolved and removed, the noble metal catalyst 22 itself does not change, and as the etching progresses, it moves below the semiconductor substrate 10 and is etched again there. Therefore, when the semiconductor substrate 10 is immersed in the etching solution 30, the etching is performed in a vertical direction with respect to the surface of the semiconductor substrate 10 to form a plurality of trenches or holes. In this embodiment, the trench or hole formed in this manner is referred to as a deep trench 24a. In FIG. 10, a semiconductor substrate 10 having a deep trench 24 a formed in the exposed region 18 is shown. Top view. Although not clearly shown, in the semiconductor substrate 10, a plurality of deep trenches 24 a are formed in the exposed region 18.

The region where the deep trench 24a is formed may correspond to a region (white region) where the Ag nanoparticle 22a shown in FIG. 7 exists. In the region (black region) where the Ag nanoparticle 22 a does not exist in FIG. 7, the etching of the semiconductor substrate 10 is not performed. This will be described later.

As the etching solution, a mixed solution containing hydrofluoric acid and an oxidizing agent can be used. The oxidant may be selected from hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg (NO ₃ ) ₂ , Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMnO ₄ , and K ₂ Cr ₂ O ₇ and the like. In terms of not generating harmful by-products or causing contamination of the element area, hydrogen peroxide is preferred as the oxidant. Furthermore, a mixed gas of fluorine gas and oxidizing gas may be used instead of the etching solution, and the etching may be advanced by a dry process.

The concentrations of hydrogen fluoride and oxidant in the etching solution are not particularly limited. For example, an aqueous solution having a hydrogen fluoride concentration of 5 mol / L to 15 mol / L and a hydrogen peroxide concentration of 0.3 mol / L to 5 mol / L can be used.

In order to more accurately etch the exposed area 18 of the semiconductor substrate 10, it is desirable to use an oxidizing agent corresponding to the material of the substrate. For example, as the oxidant, in the case of a Ge substrate, an Ag-based salt such as AgNO ₃ is preferred, and in the case of a SiC substrate, K ₂ S ₂ O ₈ is preferred. In the case of a substrate containing a III-V semiconductor such as GaAs and GaN or a Si substrate, hydrogen peroxide is preferred as the oxidizing agent. Among them, when a Si substrate is used, the etching is performed particularly well.

FIG. 11 shows an example of a cross-sectional SEM image of a single crystal silicon substrate after being immersed in an etching solution. As shown in the SEM image of FIG. 7, a plurality of Ag nano particles are formed on the exposed area of the single crystal silicon substrate. The SEM image in FIG. 11 is a result obtained by immersing such a single crystal silicon substrate in an aqueous solution having a hydrogen fluoride concentration of 10 mol / L and a hydrogen peroxide concentration of 1 mol / L for 10 minutes.

In the SEM image of FIG. 11, the area A is a portion protected by the etching mask, and the area B is It is equivalent to an exposed area where a plurality of Ag nano particles are arranged as a precious metal catalyst. In the area B, a plurality of deep trenches are represented as black areas. It can be seen that according to this embodiment, a plurality of deep trenches can be formed in the exposed area of the silicon substrate corresponding to the opening portion of the etching mask pattern. Since it is formed by so-called self-alignment, the deep trench located closest to the area A protected by the etching mask may have a sidewall in the same plane as the end face of the etching mask.

The etching is advanced so that the deep trench 24 a reaches the back surface of the semiconductor substrate 10 as shown in FIG. 12. By disposing the granular noble metal catalyst 22 in a high density in the exposed region 18 on the semiconductor substrate 10 in advance, the density of the deep trenches 24a formed in the exposed region 18 also increases. The wafer dividing trenches 24 are formed by connecting a plurality of deep trenches 24 a to each other. When the etching is completed, the semiconductor substrate 10 is singulated into a plurality of wafer bodies 10 ′ each including an element region 12. Here, the structure 28 including the wafer body 10 ′ and the etching mask 14 is referred to as a wafer or a semiconductor wafer.

As shown in FIG. 12, needle-shaped residues 26 are generated between the wafer bodies 10 ′ obtained by singulation and corresponding to the gaps between the granular noble metal catalysts 22. FIG. 13 is a plan view of the semiconductor substrate 10 in which the needle-shaped residues 26 are generated. It is also possible to complete the singulation process at this point and pick up each wafer 28 for use. This method is advantageous in that a semiconductor wafer obtained by singulation can be easily obtained.

After singulation, if necessary, the granular noble metal catalyst 22 can also be chemically removed. The noble metal catalyst 22 can be removed by wet etching using a dissolving solution. As the dissolving liquid, any liquid that can remove the precious metal catalyst film without attacking the semiconductor substrate 10, the insulating film 15, and the protective film 16 can be used. Specifically, examples of the dissolving solution include a halogen solution, an ammonium halide solution, nitric acid, and aqua regia.

After singulation, the protective film 16 can also be removed as needed. The protective film 16 can be removed by dissolving and removing with a diluent or removing with an O ₂ plasma.

If necessary, the insulating film 15 may be removed. As for the removal method of the insulating film 15, Dissolution and removal using a diluent, and removal using various plasmas can be applied.

If necessary, the needle-shaped residue 26 may be removed by etching. When the needle-shaped residue 26 has been removed, the risk of the needle-shaped residue sticking to the wafer as dust when the semiconductor wafer 28 is picked up can be reduced.

The acicular residue 26 can be removed by any etching method capable of etching the semiconductor substrate material. For example, in the case of a silicon substrate, either a wet etching method or a dry etching method may be used. The etching solution in the wet etching method may be selected from, for example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, tetramethylammonium hydroxide (TMAH, Tetramethyl Ammonium Hydroxide), and KOH. Examples of the dry etching method include plasma etching using a gas such as SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CClF ₂ , CCl ₄ , PCl ₃ , or CBrF ₃ .

FIG. 14 is a perspective view of a semiconductor wafer 28 according to an embodiment. As shown in the figure, in the semiconductor wafer 28 according to an embodiment, the surface of the wafer body 10 'where the element region is formed is composed of an insulating film (not shown) used as a part of the etching mask and an etching mask. The laminated body of the protective film 16 on the other part of the film is covered. An end surface of the protective film 16 is at least partially the same surface as a side surface of the wafer body 10 ′. The planar shape of the wafer body 10 ′, specifically, the contour of the upper surface may be at least partially consistent with the contour of the protective film 16 orthographically projected onto a plane including the upper surface. With this structure, the area exposed from the protective film 16 in the upper surface of the wafer body 10 'is greatly reduced. Therefore, the mechanical strength of the wafer can be improved. The protective film 16 may also cover the entire area of the upper surface of the wafer body 10 '. In this case, the strength is further improved.

In the case where the protective film 16 is a material having high impact resistance, the effect of the protective film 16 in suppressing wafer defects due to external impact or contact of the pickup device is further increased. Examples of materials having high impact resistance include organic resins such as polyimide, fluororesin, phenol resin, and epoxy resin.

As shown in FIG. 14, the corner portion C1 on the upper surface of the semiconductor wafer 28 is It has a round shape, which improves impact resistance. On the lower surface, the corner portion C2 is also round, so the bending strength of the semiconductor wafer 28 in this embodiment will not decrease. Thereby, it is also possible to greatly suppress chip damage caused by external impact or contact of the wafer pickup device.

Since the semiconductor wafer 28 in this embodiment is obtained by singulation using a chemical etching process, the side surface is not physically damaged. This method improves the reliability of the operation of the semiconductor wafer.

A process for singulating a semiconductor substrate into a semiconductor wafer using an insulating film as an etching mask and disposing a granular noble metal catalyst is summarized in FIGS. 15A to 15E. The protective film 16 is omitted here.

As shown in FIG. 15A, in the semiconductor substrate 10 in which a plurality of element regions 12 are formed, the element regions 12 are protected by an insulating film 15 as an etching mask. The etching mask is a region defined by the semiconductor substrate 10 to be protected by the etching mask and an exposed region, that is, an exposed region 18. A dicing sheet 20 is provided on the back surface of the semiconductor substrate 10.

A granular noble metal catalyst 22 is arranged on the exposed area 18 of the semiconductor substrate 10 as shown in FIG. 15B. The semiconductor substrate 10 is immersed in an etching solution 30 as shown in FIG. 15C. The etching is performed on the exposed region 18 of the semiconductor substrate 10, and a plurality of deep trenches 24 a are formed in each of the exposed regions 18. Due to the formation of the plurality of deep trenches 24a, needle-shaped residues are generated in the etched area.

After the etching is performed to the back surface of the semiconductor substrate 10, as shown in FIG. 15D, there is a needle-shaped residue 26 in a region corresponding to the exposed region 18. The needle-shaped residue 26 and the precious metal catalyst 22 on the dicing sheet 20 are removed, and a semiconductor wafer 28 'as shown in Fig. 15E is obtained. Here, the semiconductor wafer 28 ′ includes a wafer body 10 ′ and an insulating film 15. Between the semiconductor wafers 28 ′, the dicing sheet 20 is exposed as shown in the top view of FIG. 16.

The side surface 29 of the wafer body 10 'shown in FIG. 15E is formed from the upper surface to the lower surface in a continuous manner along the circumferential direction of the wafer body 10 due to the granular noble metal catalyst 22 located near the etching mask. Etching that extends in each direction. Etching marks reflect the The concave or convex portions of the size or shape of the granular noble metal catalyst 22 are often formed as vertical stripes, but may be formed as concave or convex portions extending in an oblique direction. Although the width of the concave or convex portions forming the etching marks depends on the particle size of the granular noble metal catalyst, it is usually about 10 to 100 nm, especially about 10 to 50 nm.

An example of the etching marks on the side surface 29 of the wafer body 10 'is shown in the schematic view of FIG. 17A. As shown in the figure, a nano-level etching mark 32 is formed on the side surface 29. Since the etching mark is a nano-level concave portion or a convex portion, even if it exists on the side surface 29 of the wafer body 10 ', it does not exert any adverse effect. In addition, depending on the etching conditions, the etch marks 32 may not be in the form of vertical stripes, but may be formed into concave or convex portions having irregular shapes or arrangements as shown in FIG. 17B.

Hereinafter, a process and a mechanism for forming the etching marks 32 will be described.

When a granular noble metal catalyst 22 is formed in the exposed area 18, as shown in FIG. 6, the shape of the area occupied by the noble metal catalyst 22 is not exactly the same as the shape of the exposed area 18, but has a grain shape. Corresponding bump. If etching is performed under precise conditions, for example, 10 mol / L of hydrofluoric acid and 2 mol / L of hydrogen peroxide, the etching occurs only in the vicinity of the precious metal catalyst 22 extremely. Therefore, on the sidewall of the wafer body 10 ', etching marks 32 are formed which reflect the grain shape of the precious metal catalyst 22 and extend from the upper surface to the lower surface. On the other hand, if the etching is performed under conditions where the concentration of the oxidant in the etching solution is high, such as 2.5 mol / L of hydrofluoric acid and 8 mol / L of hydrogen peroxide, the range affected by the precious metal catalyst 22 will be expanded. Therefore, the etching marks 32 no longer reflect the grain shape of the precious metal catalyst 22, but are formed into irregular uneven shapes.

In the case of singulation by plasma etching, as shown in FIG. 17C, due to the switching action in the plasma processing, a lateral groove 29 is formed on the side surface 29 of the wafer body 10 'parallel to the device formation surface. groove. The semiconductor wafer having such a structure is different from the semiconductor wafer of this embodiment.

A semiconductor wafer 28 ′ having an etch mark on the side surface 29 can be bonded by bonding as shown in FIG. 18. The material 34 is fixed to the substrate 35. The bonding material 34 is, for example, an adhesive, an adhesive film, or an anisotropic conductive film. The substrate 35 is, for example, a circuit board or an interposer.

A structure having an etching mark on the side surface 29 has a larger surface area than a structure having no etching mark on the side surface 29. Therefore, the heat dissipation efficiency of the semiconductor wafer 28 ′ from the side surface 29 is high. Especially for optical semiconductor wafers or power devices, the heat dissipation of the wafers is an important characteristic in ensuring the normal operation of the wafers. Furthermore, in FIG. 18, an electrode pad 51 is exposed on the upper surface of the semiconductor wafer. The electrode pad is described later.

That is, when a bonding member such as solder 36 is arranged between the substrate 35 and the semiconductor wafer 28 ′ as shown in FIG. 19, the effect of the etching marks on the side surface 29 is also exerted. In this case, the remaining solder can be moved upward on the side surface 29 by a capillary phenomenon. Thereby, the height of the wafer 28 'using the substrate 35 as a reference is reduced, and the deviation of the height is also suppressed. Further, the allowable coating amount limit of the solder 36 can be enlarged, and the step management becomes easy. Furthermore, when this structure is adopted, since the side surface 29 is in contact with the solder 36 having a high thermal conductivity, an increase in the amount of heat radiation can also be expected. This effect is also the same when the underfill is used as a bonding member instead of the solder 36.

When a semiconductor wafer 28 'having an etching mark on the side surface 29 is disposed on a lead frame and resin molding is performed, a semiconductor device 40 as shown in FIG. 20 can be obtained. In the semiconductor device 40 shown in the figure, a semiconductor wafer 28 ′ is disposed on the lead frame 41 a via a bonding material 43. The semiconductor wafer 28 ′ has a nano-level etching mark on the side surface 29 as described above, and is electrically connected to the lead frame 41 b through the A1 wire 45. These are sealed by molding resins 47a and 47b except for the external connection end portions of the lead frame 41b.

Since nanometer-level etching marks are formed on the side surface 29 of the semiconductor wafer 28 ', an anchor effect can be exerted between the semiconductor wafer 28' and the molding resin 47b to improve adhesion. For this reason, even if it is a material with weak adhesion to a wafer, such as a fluorine resin, it can also be used as a molding resin, and the selection of a molding material can be expanded.

Furthermore, even when the wafer body 10 ′ is protected by the protective film 16, the electrode pad 51 may be exposed as shown in FIG. 21A for electrical connection with the outside. The electrode pad 51 usually contains aluminum, and thus has a low resistance to an etching solution containing hydrofluoric acid and an oxidizing agent. The electrode protection layer 52 can be provided as shown in FIG. 21B to protect the electrode pad 51 from the etching solution.

The electrode protective layer 52 can be formed using any material having resistance to an etching solution, and any one of a metal and an organic material can be used. In the case where the electrode protection layer 52 is formed using a metal such as Ni / Au, even if the electrode protection layer 52 remains on the electrode pad 51, no problem will occur in the subsequent steps. The electrode protection layer 52 formed using a resin may be removed by an appropriate method after the etching process.

Here, the dimensions of the protective film and the like in the protective element region will be described with reference to FIG. 22. The thickness of the semiconductor substrate 10 forming the element region is usually about several hundred μm, and the thickness of the plurality of insulating films 54 and wirings 55 included in the element region is about several tens to several hundreds of nm. The lines and gaps of the wirings 55 have a width of about several tens to several hundreds of nm, respectively. The insulating film 54 usually contains SiN or the like.

The lines and gaps of the protective film 16 in the protective element region have widths of about several tens to several hundreds of μm, respectively. In consideration of the unevenness existing on the outermost surface of the semiconductor substrate 10, the protective film 16 is formed in a thickness of about several μm to several tens of μm.

As described with reference to FIG. 22, the thickness of the protective film 16 of the protective element region 12 is about several μm to several tens of μm, and the thickness of the insulating film 54 in the element region 12 is about several tens to several hundreds of nm. Since the insulating film 54 in the element region 12 is extremely thin, when the insulating film 54 is used as an etching mask, a fine exposed region can be formed. This process will be described with reference to FIG. 23.

As shown in FIG. 23A, a plurality of element regions 12 are formed on the semiconductor substrate 10 on which the dicing sheet 20 is disposed on the back surface, and an insulating film 54 and a protective film 16 are sequentially laminated on each element region 12. Between adjacent element regions 12, there is an exposed region where the semiconductor substrate 10 is exposed Domain 18 '. As described above, since the thickness of the insulating film 54 is about several tens to several hundreds of nm, the width of the exposed region 18 ′ may be finely set to about several tens to several hundreds of nm.

As shown in FIG. 23B, a noble metal catalyst 22 is disposed in the exposed area 18 '. At this time, by using the replacement plating method as described above, the precious metal catalyst 22 can be selectively arranged only on the exposed area 18 ′, avoiding the insulating film 54 and the protective film 16.

The semiconductor substrate 10 in which the precious metal catalyst 22 is selectively arranged in the exposed area 18 'is immersed in the etching solution as described above. Thereby, the exposed region 18 'of the semiconductor substrate is selectively removed. As a result, a wafer dividing trench 24 as shown in FIG. 23C is formed, and the semiconductor substrate 10 is singulated into a wafer body.

According to this method, since the width of the exposed area 18 ′ used to expose the cutting lines corresponds to the interval between the insulating films 54, the width of the cutting lines can be theoretically set to about several tens to several hundreds of nm. This situation is more advantageous in terms of increasing the area of the wafer where the scribe line becomes thinner and more effective.

The precious metal catalyst disposed in the exposed area of the semiconductor substrate is not limited to a granular shape, and may be a film shape. Hereinafter, a method of forming a film-like noble metal catalyst into an exposed region of a semiconductor substrate and singulating it will be described.

FIG. 24A is a partial cross-sectional view of a semiconductor substrate 10 in which a plurality of element regions 12 are formed. Each element region 12 is protected by an insulating film 15. The insulating film 15 defines a region covered by the insulating film 15 in the semiconductor substrate 10 and an exposed portion 18 of the semiconductor substrate 10 as an exposed portion. A dicing sheet 20 is provided on the back surface of the semiconductor substrate 10. A plan view of the semiconductor substrate 10 is shown in FIG. 24B.

A metal catalyst film 57 is formed on the entire upper surface of the semiconductor substrate 10 on which the insulating film 15 is formed as shown in FIG. 25A. The metal catalyst film 57 can be formed by, for example, sputtering or vapor deposition. By forming a film by this method, a metal catalyst film 57 having a uniform film thickness can be obtained. In consideration of subsequent steps such as etching, it is desirable to set the film thickness of the metal catalyst film 57 to about 10 to 50 nm. Since the metal catalyst film 57 is formed on the entire surface of the semiconductor substrate 10, the top view is as shown in FIG. 25B. As shown in the figure, the insulating film 15 and the exposed area 18 are covered with a metal catalyst film 57.

Then, as shown in FIG. 26A, a resist pattern 58 is formed to selectively protect a region on the exposed region 18 in the metal catalyst film 57. The resist pattern 58 is only required to be formed and protected in a specific region of the metal catalyst film 57 by a common method. As shown in the top view of FIG. 26B, since the resist pattern 58 is formed at a portion corresponding to the exposed area, the metal catalyst film 57 is exposed at the position of the insulating film 15.

If the exposed portion of the metal catalyst film 57 is removed by a common method, as shown in FIG. 27A, the metal catalyst film 57 is left only at the position of the resist pattern 58. A plan view of the semiconductor substrate 10 in this state is shown in FIG. 27B. The exposed portion of the metal catalyst film 57 can be removed using, for example, a halogen solution, an ammonium halide solution, nitric acid, and aqua regia.

Thereafter, the resist pattern 58 is peeled off, and the patterned metal catalyst film 57 ′ is exposed as shown in FIG. 28A. The resist pattern 58 may be peeled off using a suitable peeling liquid depending on the resist material. As shown in the top view of FIG. 28B, the patterned metal catalyst film 57 ′ is left only on the exposed area 18.

The patterned metal catalyst film 57 ′ is used as an etching mask, and the substrate removal region 18 of the semiconductor substrate 10 is selectively removed according to the steps described above. Thereby, as shown in FIG. 29A, the semiconductor substrate 10 is singulated into a wafer body 10 ′, thereby obtaining a semiconductor wafer 59 including the wafer body 10 ′ and the insulating film 15. The metal catalyst film 57 'moves downward in this state, and reaches the dicing sheet 20 as shown in the figure. A plan view of the plurality of semiconductor wafers 59 obtained by singulation is shown in FIG. 29B.

When a film-like noble metal catalyst is used, it is easier to control the film thickness than when a film-like noble metal catalyst is arranged. When a film-like precious metal catalyst is used, the catalyst film can be formed using any metal regardless of the type of semiconductor substrate material. In addition, in this case, no needle-like residue is generated.

In the above example, although the dicing sheet is provided in direct contact with the back surface of the semiconductor substrate, it is not limited to this. Alternatively, as shown in FIG. 30, the metallization layer 70 A cutting sheet 20 is provided on the back surface of the body substrate 10. The metallization layer 70 may be formed using any metal, and may have either a single-layer film or a multilayer film structure.

In particular, when noble metals such as Au, Ag, and Pt are contained in the metallization layer 70, the etching of the adhesive layer of the dicing sheet can be suppressed when the semiconductor substrate 10 is etched to reach the back surface. Depending on the situation, the metallization layer 70 may be directly left and used as a metallization film when the wafer obtained by the singulation is bonded.

It is also possible to combine the chemical etching and substrate polishing as described above to form a single piece. This process is a so-called dicing before grinding (DBG) method. This process will be described with reference to FIGS. 31A and 31B.

First, as shown in FIG. 31A, a wafer separation trench 24 is formed on the semiconductor substrate 10 to a depth equal to or greater than the thickness of the wafer body 10 ′. Thereafter, as shown in FIG. 31B, the lower surface region of the semiconductor substrate 10 is removed by the substrate polishing device 72 until it reaches the wafer separation trench 24, thereby obtaining a semiconductor wafer 28.

The area on the lower surface side of the semiconductor substrate 10 can also be removed by etching. Examples of the etching include wet etching or plasma etching. The wet etching is an etching solution selected from a mixed solution of hydrofluoric acid, nitric acid and acetic acid, TMAH, and KOH. SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CClF ₂ , CCl ₄ , PCl ₃ , and CBrF ₃ etc.

In the case of the cutting-first-polishing method, since the etching for forming the separation trench 24 is stopped before the separation trench 24 reaches the back surface of the semiconductor substrate, the rigidity of the semiconductor substrate can be maintained immediately after the etching. Therefore, this method has the advantage of being easy to handle the substrate immediately after the etching.

As described above, in the method of one embodiment, the entire exposed area of the semiconductor substrate corresponding to the scribe line can be simultaneously etched to obtain a semiconductor wafer. Therefore, even if the number of cutting lines is changed, for example, the singulation can be completed within a certain time. Moreover, since a plurality of semiconductor substrates can be processed simultaneously by batch processing, Therefore, the processing time of each substrate is greatly shortened, thereby improving productivity.

In addition, in the method of one embodiment, singulation is performed by a chemical etching process using a noble metal catalyst and an etchant or an etching gas. Therefore, optical alignment is not required in this method, and no positional deviation due to reading errors of the alignment marks or substrate distortion is generated. Furthermore, since substantially the entirety of the upper surface end portion of the wafer body can be covered with the protective resin, it is possible to reduce cracks or defects as much as possible.

A number of embodiments of the present invention have been described, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and variations are included in the scope or gist of the invention, and are included in the invention described in the scope of the patent application and their equivalents.

This embodiment includes the following aspects.

[1]

A method for manufacturing a semiconductor wafer includes the steps of forming a plurality of etching masks each including a protective film on a semiconductor substrate, and delimiting a plurality of first regions in the semiconductor substrate protected by the plurality of etching masks. And the second region that is an exposed region in the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process to form at least a portion that is located on the same surface as the end surface of the etching mask. The inner side wall and the plurality of grooves reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions.

[2]

The method as in [1], wherein the upper surface of the above-mentioned etching mask does not have a corner portion defined by two line segments with one end connected to each other.

[3]

The method as in [1], wherein the upper surface of the etching mask has 5 sides or more Polygon.

[4]

The method according to any one of [1] to [3], wherein the chemical etching process includes a step of providing a noble metal catalyst in the second region, and then contacting an etching solution or an etching gas with the semiconductor substrate.

[5]

The method as in [4] is to arrange the noble metal catalyst in the second area by electroless plating.

[6]

The method as in [4] or [5], wherein the precious metal catalyst is granular.

[7]

The method according to any one of [4] to [6], wherein the chemical etching process includes a step of contacting the etching solution with the semiconductor substrate, and the etching solution includes hydrofluoric acid and hydrogen peroxide.

[8]

The method according to any one of [1] to [7], wherein the chemical etching treatment is performed so that each of the plurality of wafer bodies has, on an end surface thereof, an opposite direction from a surface on which the protective film is formed of the wafer body. Stripe-shaped recesses or protrusions each extending on the side surface.

[9]

The method as in [8], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm.

[10]

The method as in [8], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 50 nm.

[11]

The method according to any one of [1] to [10], wherein the plurality of first regions include Semiconductor elements for electrode pads.

[12]

The method according to any one of [1] to [11], wherein the semiconductor substrate is a silicon substrate.

[13]

A semiconductor wafer includes a wafer body having a surface area including a semiconductor element, and an end surface of the wafer body has an etching mark.

[14]

The semiconductor wafer according to [13], wherein the etching marks are stripe-shaped concave portions or convex portions each extending from a surface on the surface region side of the wafer body toward a surface on the opposite side.

[15]

The semiconductor wafer as in [14], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm.

[16]

The semiconductor wafer as in [14], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 50 nm.

[17]

The semiconductor wafer according to any one of [13] to [16], further comprising a protective film covering the surface region, and the contour of the surface of the wafer body on the surface region side and the protective film toward the surface region side The orthographic profile of the plane of the face is at least partially consistent.

[18]

The semiconductor wafer according to any one of [13] to [17], wherein the surface on the surface region side of the wafer body does not have a corner portion defined by two line segments with one end in contact with each other.

[19]

A semiconductor wafer includes: a wafer body having a surface area including a semiconductor element; and a protective film covering the surface area; and the above-mentioned wafer system It is obtained by forming an etching mask including the above-mentioned protective film on a semiconductor substrate, and singulating the semiconductor substrate in a chemical etching process using a noble metal catalyst and an etching solution or an etching gas. The contour of the surface on the side of the surface region is at least partially consistent with the contour of the orthographic projection of the protective film onto a plane including the upper surface.

[20]

A semiconductor wafer includes a wafer body having a surface area including a semiconductor element, and the above-mentioned wafer system is formed by forming an etching mask including a protective film on a semiconductor substrate, and the semiconductor substrate is provided for contacting with a precious metal. In the case of singulation in a chemical etching process using a medium and an etching solution or an etching gas, the surface of the wafer body on the surface region side does not have a corner portion defined by two line segments with one end in contact with each other.

[twenty one]

A semiconductor device includes: a support member; the semiconductor wafer according to any one of [13] to [20], which is located on the support member; and a molding resin, which is provided on the support so as to cover the semiconductor wafer. Component.

[twenty two]

A semiconductor device includes: a support member; the semiconductor wafer according to any one of [13] to [20], which is located on the support member; and a bonding member, which is interposed between the support member and the semiconductor wafer.

Claims (5)

A method for manufacturing a semiconductor wafer includes the steps of forming a plurality of etching masks each including a protective film on a semiconductor substrate, and delimiting a plurality of first regions in the semiconductor substrate protected by the plurality of etching masks. And the second region that is an exposed region in the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process to form at least a portion that is located on the same surface as the end surface of the etching mask. The inner side wall and the plurality of grooves reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions, wherein the chemical etching is performed The process includes the steps of: setting a noble metal catalyst in the second area, and then contacting an etching solution or an etching gas with the semiconductor substrate, wherein the noble metal catalyst is granular, and the chemical etching process is performed to make the above Each of the plurality of wafer bodies has a stripe-shaped concave portion or a convex portion on each end surface. The concave portion or the convex portion from the line forming the main body of the wafer surface on the protective film of the surface facing the opposite side of the respective extension. The method of claim 1, wherein each of the above etching masks has an upper surface shape selected from the group consisting of a rectangle, a rectangle with rounded corners, a polygon with 5 sides or more, a circular shape, and A group of rotationally symmetric shapes. The method as claimed in claim 2, wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm. The method of claim 1, wherein each of the etching masks has an upper surface shape selected from the group consisting of a rectangle, a rectangle with a rounded corner, a hexagon, a round shape, and a corner A group of rectangles whose shapes are different from those of other corners. The method as claimed in claim 4, wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm.