KR20150055567A - Method for manufacturing semiconductor chip, semiconductor chip and semiconductor device - Google Patents

Abstract

The embodiment of the present invention relates to a method for manufacturing a semiconductor chip, the semiconductor chip, and a semiconductor device. The method for manufacturing the semiconductor chip according to the embodiment of the present invention includes the steps of determining a plurality of first regions protected by a plurality of etching masks and a second region which is an exposure region on a semiconductor substrate by forming the etching masks with protection layers on the semiconductor substrate; and reforming the semiconductor substrate into a plurality of chip bodies corresponding to the first regions by forming a plurality of grooves with the lower sides which reach the rear side of the semiconductor substrate and a sidewall which is partially located on the same surface as the end surface of the etching mask by anisotropically the second region by a chemical etching process.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a semiconductor chip,

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-235470, filed on November 13, 2013, the entire contents of which is incorporated herein by reference.

An embodiment of the present invention relates to a semiconductor chip manufacturing method, a semiconductor chip, and a semiconductor device.

In order to separate semiconductor substrates into chips, blade dicing for mechanically cutting wafers by rotating blades is generally used. In the blade dicing, a plurality of dicing grooves are sequentially formed on a semiconductor substrate, and the semiconductor substrate is divided into chips. For this reason, in the blade dicing, if the chip size is reduced and the number of dicing grooves (the number of lines) is increased, there is a problem that the dicing time is prolonged in proportion to the number of lines.

The chip obtained by blade dicing has a low impact resistance since the corners are at right angles. Furthermore, because the blade dicing causes fine cut (chipping) at the end of the chip, the chip obtained thereby has a low transverse strength.

In recent years, however, it has been proposed to form deep holes of a high aspect ratio on a single crystal substrate by a chemical action.

A problem to be solved by the present invention is to provide a method for manufacturing a semiconductor chip with high productivity.

According to the embodiment, a method of manufacturing a semiconductor chip includes: forming a plurality of etching masks, each including a protective film, on a semiconductor substrate; a plurality of first regions of the semiconductor substrate protected by the plurality of etching masks; A side wall positioned at least partially in the same plane as the end face of the etching mask to remove the second region anisotropically by a chemical etching treatment and to define a second region that is an exposed region of the semiconductor substrate; Forming a plurality of grooves each having a bottom portion reaching a back surface of the semiconductor substrate, thereby dividing the semiconductor substrate into a plurality of chip bodies corresponding to the plurality of first regions.

With this configuration, it is possible to provide a method for manufacturing a semiconductor chip with high productivity.

1 is a top view of a semiconductor substrate on which an etching mask is formed;
FIG. 2 is a cross-sectional view showing a part of the semiconductor substrate shown in FIG. 1; FIG.
FIG. 3A is a plan view showing an example of the shape of an etching mask. FIG.
FIG. 3B is a plan view showing another example of the shape of the etching mask. FIG.
3C is a plan view showing another example of the shape of the etching mask.
FIG. 3D is a plan view showing another example of the shape of the etching mask. FIG.
3E is a plan view showing another example of the shape of the etching mask.
4 is a cross-sectional view showing a process subsequent to that of Fig.
5 is a top view of a semiconductor substrate on which a noble metal catalyst is disposed;
6 is a view showing a noble metal catalyst disposed in an exposed region;
7 is a scanning electron microscope (SEM) photograph of the Ag nanoparticle catalyst.
8 is a SEM photograph showing a result of displacement plating.
9 is a cross-sectional view showing a process subsequent to that of Fig.
10 is a top view of a semiconductor substrate on which a deep trench is formed;
11 is a cross-sectional SEM photograph of the silicon substrate after the etching treatment.
12 is a cross-sectional view showing a process subsequent to the process of FIG. 9;
Fig. 13 is a top view of a semiconductor substrate in which a needle-shaped residue is generated. Fig.
FIG. 14 is a perspective view showing an example of a discrete semiconductor chip. FIG.
15A is a cross-sectional view showing a step of a method of manufacturing a semiconductor chip according to an embodiment.
15B is a cross-sectional view showing a process subsequent to the process of FIG. 15A;
15C is a cross-sectional view showing a process subsequent to the process of FIG. 15B; FIG.
15D is a cross-sectional view showing a step subsequent to the step of FIG. 15C;
15E is a cross-sectional view showing a step subsequent to the step of FIG. 15D;
16 is a top view showing a semiconductor chip group that has been fragmented.
17A is a perspective view schematically showing an example of an etching mark.
17B is a perspective view schematically showing another example of an etching mark.
17C is a perspective view schematically showing another example of an etching mark.
18 is a cross-sectional view of a semiconductor device according to an embodiment;
19 is a cross-sectional view of a semiconductor device according to another embodiment;
20 is a cross-sectional view of a semiconductor device according to still another embodiment;
21A is an enlarged cross-sectional view showing an example of a chip body including an electrode pad.
21B is an enlarged cross-sectional view showing an example of a chip body in which an electrode pad is covered with an electrode protection layer.
22 is an enlarged cross-sectional view showing an insulating film or the like of the chip body.
23A is a cross-sectional view showing the manufacturing method steps of a semiconductor chip according to another embodiment;
23B is a cross-sectional view showing a step subsequent to the step of FIG. 23A;
23C is a cross-sectional view showing the process subsequent to the process of FIG. 23B; FIG.
24A is a cross-sectional view showing a step of a method of manufacturing a semiconductor chip according to another embodiment;
Fig. 24B is a top view showing the process of Fig. 24A. Fig.
25A is a cross-sectional view showing a process subsequent to the process of FIG. 24A; FIG.
Fig. 25B is a top view showing the process of Fig. 25A. Fig.
26A is a cross-sectional view showing a process subsequent to the process of FIG. 25A; FIG.
FIG. 26B is a top view showing the process of FIG. 26A. FIG.
FIG. 27A is a cross-sectional view showing a process subsequent to the process of FIG. 26A; FIG.
FIG. 27B is a top view showing the process of FIG. 27A. FIG.
28A is a cross-sectional view showing a process subsequent to the process of FIG. 27A;
Fig. 28B is a top view showing the process of Fig. 28A. Fig.
29A is a cross-sectional view showing a process subsequent to the process of FIG. 28A;
FIG. 29B is a top view showing the process of FIG. 29A. FIG.
30 is a cross-sectional view showing another example of a semiconductor substrate;
31A is a cross-sectional view showing one step of the method of another embodiment;
FIG. 31B is a cross-sectional view showing a step subsequent to the step of FIG. 31A; FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a top view of a semiconductor substrate used in a method according to an embodiment. Fig. 2 is a partial cross-sectional view of the semiconductor device of Fig.

As shown in the drawing, a plurality of element regions 12 each including one or more semiconductor elements are formed in a semiconductor substrate 10. These element regions 12 are arranged apart from each other. Each device region 12 is protected by covering it with an etching mask 14.

The semiconductor element included in the element region 12 is, for example, a transistor, a diode, a light emitting diode, or a semiconductor laser. The element region 12 may further include a capacitor, a wiring, and the like.

The region between the adjacent element regions 12 is the exposed region 18 in which the surface of the semiconductor substrate 10 is exposed. As will be described later, the noble metal catalyst is disposed in the exposed region 18. [ In this embodiment, the exposed region 18 of the semiconductor substrate 10 is removed by chemical etching treatment using a noble metal catalyst and an etchant to obtain a semiconductor chip in a discrete manner.

In the example shown in Fig. 2, the etching mask 14 includes a laminated structure of the insulating film 15 and the protective film 16. The insulating film is a kind of a protective film. However, by forming the insulating film 15, it is possible to reliably protect the electrode pads (not shown) of the element region 12. In some cases, the etching mask 14 may be formed of an insulating film or a protective film.

It is preferable that a dicing sheet 20 for holding the individual chips is attached to the back surface of the semiconductor substrate 10.

The semiconductor substrate 10 is selectively etchable by the effect of a noble metal catalyst and is made of a semiconductor such as Si, Ge, III-V semiconductor, that is, a semiconductor including a compound of a Group III element and a V element (for example, GaAs, GaN or the like) and SiC. The term " family " used herein is a " family "

The thickness of the semiconductor substrate 10 is not particularly limited and may be suitably determined according to the size of the intended semiconductor chip. The thickness of the semiconductor substrate 10 may be, for example, in the range of 50 탆 to 500 탆. The doping amount of the impurity into the semiconductor substrate 10 is also not particularly limited and may be appropriately determined. The major surface of the semiconductor substrate 10 may be parallel to any crystal plane of the semiconductor.

The etching mask 14 is selectively formed in a plurality of regions on the upper surface of the semiconductor substrate 10 so as to cover the element regions 12. [ The shape of the top surface of each etching mask 14 is not limited to a rectangular shape, and may be various shapes as shown in Figs. 3A to 3E.

When the etching mask 14 is formed to have a rounded corner portion as shown in FIG. 3A, the corner portion is also rounded even in the individualized chip. In other words, the etching mask 14 and the top surface shape of the semiconductor chip have a shape in which straight lines (line segments) constituting the contour do not have portions in contact with each other, that is, the line segments constituting the contour are spaced apart from each other . By making the corner portion round, the mechanical strength of the chip is increased.

The upper surface of the etching mask 14 may be a polygon having five or more sides. For example, in the example shown in Fig. 3B, each of the etching masks 14 has a hexagonal upper surface and is arranged in a honeycomb shape. When the etching mask has such a top surface shape, a semiconductor chip whose top surface is a polygon having five or more sides is obtained. A semiconductor chip in which each internal angle of a polygon is larger than 90 degrees has a higher mechanical strength than a semiconductor chip in which each internal angle of the polygon is 90 degrees.

The etching mask 14 may have a circular upper surface as shown in Fig. 3C. When the etching mask has such a top surface shape, a semiconductor chip whose top surface is circular is obtained. A semiconductor chip whose top surface is circular has a mechanical strength equal to or higher than that of a rectangular semiconductor chip whose top surface has a rounded corner portion.

In the case where the top surface shape of the semiconductor chip has rotational symmetry, the orientation alignment can not be performed based only on the top surface shape of the semiconductor chip. As shown in FIG. 3E, when the upper surface of the etching mask 14 is formed to have no rotational symmetry, a semiconductor chip having a shape in which the upper surface does not have rotational symmetry can be obtained. Such a semiconductor chip can align its orientation based on, for example, only the top surface shape. There is no particular limitation on the shape having no rotational symmetry. For example, the shape of at least one corner portion may be different from the shape of the other corner portion, or a shape in which a notch is formed.

The etching masks formed on the semiconductor substrate need not all have the same shape. For example, the etching mask 14 may be formed into a pattern having a different shape as shown in FIG. 3D.

Even when an etching mask of any shape is used, the semiconductor chip is disassembled so as to have a top surface shape substantially reflecting the top surface shape of the mask.

The material of the insulating film 15 is not particularly limited as long as it can suppress adhesion of the noble metal catalyst to the semiconductor substrate, and any insulating material such as organic or inorganic may be used. Examples of the organic insulating material include organic resins such as polyimide, fluororesin, phenol resin, and epoxy resin. As the inorganic insulating material, for example, an oxide film and a nitride film can be given. The insulating film 15 is not necessarily formed separately on the element region 12. It is also possible to use a part of the insulating film constituting the element region 12 as the insulating film 15.

When a material having impact absorbability such as an organic resin is used as the insulating film, the insulating film can be left as a permanent film in the final product. When the remaining insulating film is used as the shock absorbing film of the individualized chip, the upper surface of the individualized chip is completely covered with the shock absorbing film, so that the mechanical strength of the chip is increased.

The material of the protective film 16 is not particularly limited as long as it is not eroded by the etching solution. For example, the protective film 16 can be formed using an organic resin such as polyimide, a fluororesin, a phenol resin, and an epoxy resin, or a noble metal such as Au, Ag, and Pt.

The exposed region 18 is used for discretization of semiconductor chips and corresponds to a so-called dicing line. The width of the exposed region 18 is not particularly limited, but is, for example, in the range of 1 m to 200 m.

As shown in Fig. 4, the noble metal catalyst 22 is disposed in the exposed region 18. As shown in Fig. Here, the etching mask 14 functions as a mask for preventing the adhesion of the noble metal catalyst 22 to a portion other than the exposed region 18. FIG. 5 shows a top view of the semiconductor substrate 10 in which the noble metal catalyst 22 is disposed in the exposed region 18. As shown in FIG.

The noble metal catalyst 22 activates the oxidation reaction of the semiconductor substrate 10 in contact with the noble metal catalyst. Any noble metal having the effect of activating this oxidation reaction can be used as the noble metal catalyst 22. The material of the noble metal catalyst 22 can be selected from, for example, Au, Ag, Pt, and Pd.

The noble metal catalyst 22 can be arranged, for example, in a granular form. The noble metal catalyst of the granular phase is preferable because it is stable during etching. Examples of the shape of the granular catalyst include spherical, rod-shaped, and plate-like shapes. In the case of the spherical shape, the direction in which the etching of the semiconductor substrate proceeds is close to vertical, which is preferable. The particle diameter of the granular catalyst is not particularly limited, and can be, for example, in the range of several tens nm to several hundreds of nanometers. Further, in order to facilitate chip division after etching, the granular catalysts are preferably arranged in a high-density or multilayer structure.

6 is a schematic view showing a part of the upper surface of the semiconductor substrate 10 on which the noble metal catalyst 22 in the granular state is arranged in the exposed region 18. As shown in Fig.

The noble metal catalyst can be disposed in the exposed region 18 of the semiconductor substrate 10 by, for example, electrolytic plating, reduction plating, or displacement plating. Further, application of a dispersion liquid containing noble metal particles, vapor deposition, sputtering or the like may be used. Among these methods, when substitution plating is used, it is possible to uniformly and directly form the noble metal catalyst in a granular state in the exposed region 18 corresponding to the dicing line.

In order to arrange the noble metal catalyst in the granular state by displacement plating, for example, a silver nitrate solution can be used. Hereinafter, an example of this process will be described. As the substitution plating solution, for example, a silver nitrate solution, a mixed solution of hydrofluoric acid and water may be used. The hydrofluoric acid has an action of removing a natural oxide film on the surface of the semiconductor substrate.

The silver nitrate concentration in the displacement plating liquid is preferably in the range of 0.001 mol / L to 0.1 mol / L, more preferably in the range of 0.005 to 0.01 mol / L. The concentration of hydrogen fluoride in the displacement plating liquid is preferably in the range of 1 mol / L to 6.5 mol / L.

The semiconductor substrate 10 in which the predetermined region is selectively protected by the etching mask is immersed in the replacement plating liquid as described above for about 1 to 5 minutes so that only the exposed region 18 of the semiconductor substrate 10 Ag nanoparticles as the catalyst 22 can be precipitated. The temperature of the displacement plating liquid is not particularly limited, and may be suitably set, for example, at 25 占 폚 or 35 占 폚.

Fig. 7 shows an SEM image of a sample in which Ag nanoparticle groups are formed on a silicon substrate by displacement plating. Here, a single crystal silicon substrate having a predetermined region protected by an etching mask was immersed in a displacement plating liquid at 25 占 폚 for 3 minutes to form Ag nanoparticles in the exposed region of the single crystal silicon substrate.

As the etching mask, an insulating film containing a polyimide film was used, and an aqueous solution containing 0.005 mol / L of silver nitrate and 5.0 mol / L of hydrogen fluoride as substitution plating solutions was used. In the SEM image of Fig. 7, the Ag nanoparticles 22a corresponding to the noble metal catalyst 22 in the granular state appear as a white region. These Ag nanoparticles 22 have a particle diameter of about 100 nm.

The particle diameter of the Ag nanoparticles 22 can be controlled by, for example, changing the immersion time or the concentration of the displacement plating liquid. The particle diameter of the Ag nanoparticles is preferably about several tens to several hundreds of nanometers. When Ag nanoparticles having a particle diameter in this range were formed, it was confirmed that the etching of the semiconductor substrate proceeded well when immersed in the etching solution.

Also, the entire surface of the exposed region of the single crystal silicon substrate is not completely covered with Ag nanoparticles. In a part of the SEM image of Fig. 7, a part of the surface of the semiconductor substrate 10 is shown as a black region.

Here, an example of the results obtained by immersing the Si substrate in various substitution plating solutions having different compositions for 1 minute is summarized in FIG. The concentration of the silver nitrate solution in the displacement plating solution was 0.001 to 0.05 mol / L, the concentration of hydrogen fluoride was 3.5 to 6.5 mol / L, and the temperature of the displacement plating solution was 25 ° C.

When the concentration of hydrogen fluoride in the displacement plating liquid is any value within the range of 3.5 to 6.5 mol / L, when the concentration of silver nitrate is 0.03 mol / L or more, the crystal of Ag grows in the form of a tree, L, the formation of Ag nanoparticles having a particle diameter of about 10 to 100 nm is confirmed. In order to obtain Ag nanoparticles having a desired particle diameter, substitution plating may be performed by appropriately setting the composition and temperature of the displacement plating liquid, the immersion time, and the like.

The semiconductor substrate on which the noble metal catalyst 22 is disposed is immersed in the etching liquid 30 as shown in Fig. As the etching liquid 30, a mixed liquid containing hydrofluoric acid and an oxidizing agent is used. The oxidation of the semiconductor substrate 10 occurs only at a portion (the exposed region 18) that is in contact with the noble metal catalyst 22 due to the action of the noble metal catalyst 22. The oxidized region of the semiconductor substrate 10 is dissolved and removed by hydrofluoric acid, whereby it becomes possible to selectively etch only a portion in contact with the noble metal catalyst 22 in the granular state. That is, the etching of the exposed region 18 proceeds anisotropically.

When the semiconductor substrate 10 is selectively dissolved and removed, the noble metal catalyst 22 itself does not change and moves to the lower side of the semiconductor substrate 10 along with the progress of the etching, and etching is performed thereafter. Therefore, when the semiconductor substrate 10 is immersed in the etching solution 30, etching proceeds in a direction perpendicular to the surface of the semiconductor substrate 10 to form a plurality of grooves or holes. In this embodiment, the grooves or holes thus formed are referred to as deep trenches 24a. 10 shows a top view of the semiconductor substrate 10 in which the deep trench 24a is formed in the exposed region 18. As shown in FIG. A plurality of deep trenches 24a are formed in the exposed region 18 in the semiconductor substrate 10 although not clearly shown.

The region where the deep trench 24a is formed corresponds to the region (white region) where the Ag nanoparticles 22a shown in FIG. 7 exist. In the region (black region) where the Ag nanoparticles 22a are not present in FIG. 7, the etching of the semiconductor substrate 10 does not proceed. This will be described later.

As the etching solution, a mixed solution containing hydrofluoric acid and an oxidizing agent can be used. The oxidizing agent is hydrogen peroxide, _{nitrate, AgNO 3, KAuCl 4, HAuCl} 4, K 2 PtCl 6, H 2 PtCl 6, Fe (NO 3) 3, Ni (NO 3) 2, Mg (NO 3) 2, Na 2 S 2 O ₈ , K ₂ S ₂ O ₈ , KMnO _4, and K ₂ Cr ₂ O ₇ . Hydrogen peroxide is preferable as the oxidizing agent since harmful by-products are not generated and contamination of the element region does not occur. It is also possible to use a mixed gas of a fluorine gas and an oxidizing gas in place of the etching liquid, and to advance the etching by a dry process.

The concentration of hydrogen fluoride and oxidizing agent in the etching solution is not particularly limited. For example, an aqueous solution having a hydrogen fluoride concentration of 5 to 15 mol / L and a hydrogen peroxide concentration of 0.3 to 5 mol / L can be used.

In order to more reliably etch the exposed region 18 of the semiconductor substrate 10, it is desired to use an oxidizing agent depending on the material of the substrate. For example, an Ag-based salt such as AgNO ₃ is preferable as an oxidizing agent in the case of a Ge substrate, and K ₂ S ₂ O ₈ is preferable in the case of a SiC substrate. In the case of a substrate including a III-V group semiconductor such as GaAs and GaN or a Si substrate, hydrogen peroxide is preferable as an oxidizing agent. Among them, in the case of using a Si substrate, etching proceeds particularly well.

Fig. 11 shows an example of a cross-sectional SEM image of a single crystal silicon substrate after being immersed in an etching solution. In the exposed region of the single crystal silicon substrate, a plurality of Ag nanoparticles were formed as shown in the SEM image of FIG. The SEM image of Fig. 11 shows the result of immersing such a single crystal silicon substrate in an aqueous solution having a hydrogen fluoride concentration of 10 mol / L and a hydrogen peroxide concentration of 1 mol / L for 10 minutes.

In the SEM image of Fig. 11, region A is a portion protected by an etching mask, and region B corresponds to an exposed region where a plurality of Ag nanoparticles are arranged as a noble metal catalyst. In the region B, a plurality of deep trenches are shown as black regions. According to this embodiment, it is understood that a plurality of deep trenches can be formed in the exposed region of the silicon substrate corresponding to the opening portion of the etching mask pattern. The deep trench located closest to the protected region A with the etch mask can have sidewalls in the same plane as the end face of the etch mask, since it is formed of so-called self-aligning.

And the deep trench 24a is allowed to reach the back surface of the semiconductor substrate 10 as shown in Fig. The density of the deep trench 24a formed in the exposed region 18 is increased by arranging the noble metal catalyst 22 in a high density in the exposed region 18 on the semiconductor substrate 10. [ The chip dividing grooves 24 are formed by connecting the plurality of deep trenches 24a to each other and at the time the etching is completed, the semiconductor substrate 10 is divided into a plurality of chip bodies 10 ' ). Here, the structure 28 including the chip body 10 'and the etching mask 14 is referred to as a chip or a semiconductor chip.

Like residue 26 is generated in a portion corresponding to the gap of the noble metal catalyst 22 between the individual chip bodies 10 'as shown in Fig. Fig. 13 shows a top view of the semiconductor substrate 10 in which the needle-shaped residue 26 is generated. At this point, it is also possible to complete the fragmentation process and pick up each chip 28 for use. This method is advantageous in that a discrete semiconductor chip can be obtained easily.

After the preparation, the noble metal catalyst 22 may be chemically removed if necessary. The noble metal catalyst 22 can be removed by wet etching using a dissolution liquid. Any liquid capable of removing the noble metal catalyst film without eroding the semiconductor substrate 10, the insulating film 15, and the protective film 16 can be used as the dissolving solution. Specifically, examples of the dissolving solution include a halogen solution, an ammonium halide solution, nitric acid, and aqua regia.

After the reorganization, the protective film 16 may be removed as necessary. The protective film 16 can be removed by dissolution removal by a thinner or removal by O ₂ plasma or the like.

If necessary, the insulating film 15 can also be removed. For removing the insulating film 15, dissolution by thinner, removal by various plasma, and the like are applicable.

If necessary, the needle-shaped residue 26 may be etched away. When the needle-like residue 26 is removed, it is possible to reduce the possibility that the needle-like residue sticks to the chip as dust when the semiconductor chip 28 is picked up.

The needle-like residue 26 can be removed by any etching method that allows the semiconductor substrate material to be etched. For example, in the case of a silicon substrate, either a wet etching method or a dry etching method may be used. The etching solution in the wet etching method can be selected from, for example, a mixed solution of hydrofluoric acid, nitric acid and acetic acid, tetramethylammonium hydroxide (TMAH), and KOH. Examples of the dry etching method include plasma etching using a gas such as SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CClF ₂ , CCl ₄ , PCl ₃ , or CBrF ₃ .

Fig. 14 shows a perspective view of a semiconductor chip 28 according to an embodiment. As shown in the figure, in the semiconductor chip 28 according to the embodiment, the surface on which the element region of the chip body 10 'is formed is divided into an insulating film (not shown) used as a part of the etching mask, And a protective film 16 used as a protective film. The end surface of the protective film 16 is at least partially flush with the side surface of the chip body 10 '. The planar shape of the chip body 10 ', specifically, the contour of the upper surface may at least partially coincide with the contour of the orthogonal projection of the protective film 16 on the plane including this upper surface. With this structure, the area exposed from the protective film 16 in the upper surface of the chip body 10 'is greatly reduced. Therefore, the mechanical strength of the chip is increased. The protective film 16 may cover the entire upper surface of the chip body 10 '. In this case, the strength is further increased.

When the protective film 16 is made of a material having high impact resistance, the effect of the protective film 16 on suppressing chip cutting due to external impact or contact with the pickup device becomes even greater. Examples of the material having high impact resistance include organic resins such as polyimide, fluororesin, phenol resin, and epoxy resin.

In addition, as shown in Fig. 14, since the corner C1 on the upper surface of the semiconductor chip 28 is round, the impact resistance is increased. Since the corner portion C2 is round in the bottom surface, the semiconductor chip 28 according to the present embodiment is not reduced in the transverse strength. As a result, the external impact or chip cut-off due to the contact of the chip pick-up apparatus is greatly suppressed.

Since the semiconductor chip 28 in the present embodiment is obtained by fragmentation using a chemical etching treatment, the side surface is not subjected to a physical impact. This leads to an improvement in the operational reliability of the semiconductor chip.

15A to 15E summarize the process of disposing the semiconductor substrate into a semiconductor chip by using an insulating film as an etching mask and disposing a noble metal catalyst in a granular state. Here, the protective film 16 is omitted.

The element region 12 is protected by the insulating film 15 as an etching mask in the semiconductor substrate 10 in which the plurality of element regions 12 are formed as shown in Fig. The etching mask defines, on the semiconductor substrate 10, a region protected by an etching mask and an exposed region 18 which is an exposed region. Further, a dicing sheet 20 is provided on the back surface of the semiconductor substrate 10.

In the exposed region 18 of the semiconductor substrate 10, a noble metal catalyst 22 is disposed as shown in Fig. 15B. The semiconductor substrate 10 is immersed in the etching liquid 30 as shown in Fig. 15C. The etching proceeds in the exposed region 18 of the semiconductor substrate 10 to form a plurality of deep trenches 24a in each of the exposed regions 18. [ By forming a plurality of deep trenches 24a, needle-like residues are generated in the etched regions.

After etching proceeds to the back surface of the semiconductor substrate 10, the needle-shaped residue 26 is present in the region corresponding to the exposed region 18 as shown in Fig. 15D. The needle-shaped residue 26 on the dicing sheet 20 and the noble metal catalyst 22 are removed to obtain a semiconductor chip 28 'as shown in Fig. 15E. Here, the semiconductor chip 28 'includes a chip body 10' and an insulating film 15. Between the semiconductor chips 28 ', the dicing sheet 20 is exposed as shown in the top view of Fig.

An etched mark extending from the upper surface toward the lower surface due to the noble metal catalyst 22 located in the vicinity of the etching mask is formed on the side surface 29 of the chip body 10 ' (10 '). The etching mark is often a concave or convex portion reflecting the size or shape of the noble metal catalyst 22 in the granular phase used and is sometimes formed as a vertical line, but it may be formed as a concave portion or a convex portion extending in the oblique direction. The width of the concave or convex portion forming the etching mark depends on the particle diameter of the noble metal catalyst of the granular phase, but is generally about 10 to 100 nm, particularly about 10 to 50 nm.

An example of the etching mark on the side surface 29 of the chip body 10 'is shown in a schematic view of Fig. 17A. As shown in the figure, a nano-order etching mark 32 is formed on the side surface 29. Since the etching mark is a concave portion or a convex portion of the nano order, even if it exists on the side surface 29 of the chip body 10 ', it does not work at all. Depending on the etching condition, the etching trace 32 may not be formed in a vertical line shape but may be formed as a concave portion or a convex portion randomly shaped or arranged as shown in Fig. 17B.

Hereinafter, the process and mechanism in which the etching trace 32 is formed will be described.

6, the shape of the area occupied by the noble metal catalyst 22 does not completely coincide with the shape of the exposed area 18, and when the noble metal catalyst 22 is formed in the exposed area 18, And has irregularities depending on the shape of the particles. When etching is performed under the proper conditions, for example, hydrofluoric acid 10 mol / L and hydrogen peroxide 2 mol / L, etching occurs only in the vicinity of the noble metal catalyst 22. Therefore, on the side walls of the chip body 10 ', the etching marks 32 extending from the upper surface toward the lower surface are formed reflecting the particle shape of the noble metal catalyst 22. On the other hand, when the etching is performed under conditions where the oxidizing agent concentration of the etching liquid is high, for example, under the conditions of hydrofluoric acid of 2.5 mol / L and hydrogen peroxide of 8 mol / L, the range of influence of the noble metal catalyst 22 is widened. Therefore, the etching mark 32 is formed as a random irregular shape without reflecting the particle shape of the noble metal catalyst 22.

When the discretization is performed by plasma etching, lateral grooves parallel to the device forming surface are formed on the side surface 29 of the chip body 10 'due to the switching operation in the plasma processing as shown in Fig. 17C . The semiconductor chip having such a structure is different from the semiconductor chip according to the present embodiment.

The semiconductor chip 28 'having the etching mark on the side surface 29 can be provided on the substrate 35 via the bonding material 34 as shown in Fig. The bonding material 34 is, for example, an adhesive, an adhesive film, or an anisotropic conductive film. The substrate 35 is, for example, a circuit board or an interposer.

The structure having the etching mark on the side surface 29 has a larger surface area than the structure having no etching mark on the side surface 29. Therefore, the semiconductor chip 28 'has high heat dissipation efficiency from the side surface 29 thereof. Especially in optical semiconductor chips and power devices, heat dissipation of chips is an important characteristic in ensuring normal operation of the chip. 18, the electrode pad 51 is exposed on the upper surface of the semiconductor chip. The electrode pads will be described later.

The effect of the etching marks on the side surface 29 is exerted even when a bonding member such as the solder 36 is disposed between the substrate 35 and the semiconductor chip 28 'as shown in Fig. In this case, the excess solder can move upward on the side surface 29 by the capillary phenomenon. As a result, the height of the chip 28 'based on the substrate 35 is reduced, and the unevenness of the height is also suppressed. Further, the allowable application amount margin of the solder 36 can be widened, and the process control is facilitated. In addition, when this structure is employed, since the side surface 29 is in contact with the solder 36 having a high thermal conductivity, an increase in the amount of heat dissipation can also be expected. This effect is also obtained when an underfill agent is used instead of the solder 36 as the bonding member.

When the semiconductor chip 28 'having the etching mark on the side surface 29 is disposed on the lead frame and resin molded, a semiconductor device 40 as shown in Fig. 20 is obtained. In the illustrated semiconductor device 40, a semiconductor chip 28 'is disposed on a lead frame 41a with a bonding material 43 interposed therebetween. The semiconductor chip 28 'has an etching mark on the side surface 29 of the nano-order as described above and is electrically connected to the lead frame 41b by the Al wire 45. [ They are sealed by the mold resin 47a and 47b except for the end portion for external connection of the lead frame 41b.

Since the nano-order etching mark is formed on the side surface 29 of the semiconductor chip 28 ', an anchor effect acts between the semiconductor chip 28' and the mold resin 47b, so that the adhesion can be enhanced. For this reason, even a material such as a fluorine-based resin generally having poor adhesiveness to a chip can be used as a mold resin, and it becomes possible to broaden the selection of a mold material.

In addition, even when the chip body 10 'is protected by the protective film 16, the electrode pad 51 may be exposed as shown in Fig. 21A in order to be electrically connected to the outside. Since the electrode pad 51 usually contains aluminum, resistance to an etching solution containing hydrofluoric acid and an oxidizing agent is weak. By forming the electrode protection layer 52 as shown in Fig. 21B, the electrode pad 51 can be protected from the etching solution.

The electrode protection layer 52 can be formed using any material resistant to the etching solution, and either a metal or an organic material may be used. For example, when the electrode protection layer 52 is formed using a metal such as Ni / Au, even if the electrode protection layer 52 remains on the electrode pad 51, none. The electrode protection layer 52 formed using the resin may be removed by an appropriate method after the etching treatment.

Here, with reference to FIG. 22, the dimensions of a protective film or the like for protecting an element region will be described. The thickness of the semiconductor substrate 10 on which the element region is formed is usually several hundreds of micrometers and the thickness of the insulating film 54 and the wiring 55 included in the element region is on the order of tens to hundreds of nanometers. The lines and spaces of the wirings 55 each have a width of several tens to several hundreds nm. The insulating film 54 generally includes SiN or the like.

The line-and-space of the protective film 16 for protecting the element region is about several tens to several hundreds of micrometers wide. The protective film 16 is formed to a thickness of several to several tens of micrometers in consideration of the unevenness existing on the outermost surface of the semiconductor substrate 10. [

The thickness of the insulating film 54 in the element region 12 is in the range of several tens to several hundreds of microns, while the thickness of the protective film 16 for protecting the element region 12 is about several to several tens of microns, Nm. Since the insulating film 54 in the element region 12 is extremely thin, a fine exposed region can be formed when this insulating film 54 is used as an etching mask. This process will be described with reference to Fig.

23A, a plurality of device regions 12 are formed on a semiconductor substrate 10 on which a dicing sheet 20 is disposed, and an insulating film 54 and a protective film 16 are sequentially stacked. Between the adjacent element regions 12, there is an exposed region 18 'in which the semiconductor substrate 10 is exposed. Since the thickness of the insulating film 54 is about several tens to several hundreds nm as described above, the width of the exposed region 18 'can be made as small as several tens to several hundreds nm.

The noble metal catalyst 22 is disposed in the exposed region 18 'as shown in FIG. 23B. At this time, by adopting the substitution plating method as described above, the noble metal catalyst 22 can be selectively disposed only on the exposed region 18 'while avoiding the insulating film 54 or the protective film 16.

In the exposed region 18 ', the semiconductor substrate 10 selectively disposed on the noble metal catalyst 22 is immersed in the etching solution as described above. Thereby, the exposed region 18 'of the semiconductor substrate is selectively removed. As a result, chip dividing grooves 24 as shown in Fig. 23C are formed, and the semiconductor substrate 10 is divided into chip bodies.

According to this method, since the width of the exposed region 18 'used as the exposure dicing line corresponds to the interval between the insulating films 54, the width of the dicing line can theoretically be set to several tens to several hundreds nm. This is advantageous in that the dicing line is thinned and the effective chip area is increased.

The noble metal catalyst disposed in the exposed region of the semiconductor substrate is not limited to the granular phase, and may be a film. Hereinafter, a method of forming and separating the film-type noble metal catalyst in the exposed region of the semiconductor substrate will be described.

24A is a partial cross-sectional view of a semiconductor substrate 10 on which a plurality of element regions 12 are formed. Each device region 12 is protected by an insulating film 15. The insulating film 15 defines a region covered by the insulating film 15 and an exposed region 18 in the semiconductor substrate 10 that is a portion where the semiconductor substrate 10 is exposed. Further, a dicing sheet 20 is provided on the back surface of the semiconductor substrate 10. A top view of the semiconductor substrate 10 is shown in Fig.

A metal catalyst film 57 is formed on the entire upper surface of the semiconductor substrate 10 on which the insulating film 15 is formed as shown in Fig. The metal catalyst film 57 can be formed by, for example, sputtering or vapor deposition. By this film formation, a metal catalyst film 57 having a uniform film thickness can be obtained. Considering the subsequent process such as etching, it is desired that the film thickness of the metal catalyst film 57 is about 10 to 50 nm. Since the metal catalyst film 57 is formed on the entire surface of the semiconductor substrate 10, the insulating film 15 and the exposed region 18 are covered with the metal catalyst film 57 as shown in the top view of FIG. 25B.

26A, a resist pattern 58 is formed to selectively protect an area of the metal catalyst film 57 that is located on the exposed region 18. Next, as shown in FIG. The resist pattern 58 may be formed by a conventional method to protect a predetermined region of the metal catalyst film 57. The metal catalyst film 57 is exposed at the position of the insulating film 15 because the resist pattern 58 is formed in the portion corresponding to the exposed region as shown in the top view of FIG.

When the exposed portion of the metal catalyst film 57 is removed by a conventional method, the metal catalyst film 57 is left only at the position of the resist pattern 58 as shown in Fig. FIG. 27B shows a top view of the semiconductor substrate 10 in this state. The exposed portion of the metal catalyst film 57 can be removed by using, for example, a halogen solution, an ammonium halide solution, nitric acid, and aqua regia.

Thereafter, the resist pattern 58 is peeled off to expose the patterned metal catalyst film 57 'as shown in FIG. 28A. The resist pattern 58 may be peeled off using a suitable peeling liquid depending on the resist material. The patterned metal catalyst film 57 'is left only on the exposed region 18 as shown in the top view of FIG. 28B.

Using the patterned metal catalyst film 57 'as an etching mask, the substrate removal region 18 of the semiconductor substrate 10 is selectively removed according to the process as described above. 29A, the semiconductor substrate 10 is divided into the chip body 10 ', and the semiconductor chip 59 including the chip body 10' and the insulating film 15 is obtained. The metal catalyst film 57 'moves downward as it is, and reaches the dicing sheet 20 as shown in the figure. FIG. 29B shows a top view of a plurality of discrete semiconductor chips 59. FIG.

When the noble metal catalyst is used, the film thickness can be easily controlled as compared with the case where the noble metal catalyst is disposed. When a film-type noble metal catalyst is used, a catalyst film can be formed using any metal, regardless of the kind of the semiconductor substrate material. In addition, in this case, needle-shaped residue does not occur.

In the above example, the back surface of the semiconductor substrate is provided directly on the dicing sheet, but the present invention is not limited to this. The dicing sheet 20 may be provided on the back surface of the semiconductor substrate 10 via the metallization layer 70 as shown in Fig. The metallization layer 70 may be formed using any metal, and may be any of a single layer film and a multilayer film.

Particularly, when noble metals such as Au, Ag and Pt are included in the metallization layer 70, the etching of the semiconductor substrate 10 proceeds to suppress the invasion of the adhesive layer of the dicing sheet into the etching solution can do. In some cases, the metallization layer 70 may be left as it is and used as a metallization film when die-bonding the discrete chips.

The above-described chemical etching and substrate grinding may be combined and separated. This process is a so-called dicing before grinding method. This process will be described with reference to Figs. 31A and 31B.

First, as shown in Fig. 31A, a chip separation groove 24 is formed in the semiconductor substrate 10 at a depth equal to or greater than the thickness of the chip body 10 '. Thereafter, as shown in Fig. 31B, the substrate side grinding device 72 removes the area on the lower surface side of the semiconductor substrate 10 until reaching the chip separating groove 24, thereby obtaining the semiconductor chip 28. [

The lower surface side region of the semiconductor substrate 10 may be removed by etching. As the etching, for example, wet etching with the etching solution is selected from hydrofluoric acid and mixture of nitric acid and acetic acid, TMAH, and KOH, and the like, or _{SF 6, CF 4, C 2} F 6, C 3 F 8, CClF 2, CCl 4 , PCl ₃ , CBrF ₃ , and the like.

When the pre-dicing method is adopted, the etching for forming the separation grooves 24 is stopped before the separation grooves 24 reach the back surface of the semiconductor substrate, so that the rigidity of the semiconductor substrate is maintained immediately after this etching. Therefore, this method has an advantage that the substrate can be easily handled immediately after etching.

As described above, in the method according to the embodiment, the entire exposed region of the semiconductor substrate corresponding to the dicing line can be simultaneously etched to obtain the semiconductor chip. Therefore, even if the number of dicing lines is changed, for example, the discretization can be completed at a constant time. In addition, since a plurality of semiconductor substrates can be simultaneously processed by a batch process, the processing time per substrate is greatly shortened, and the productivity is improved.

Further, in the method according to an embodiment, discretization is performed by a chemical etching treatment using a noble metal catalyst and an etching solution or an etching gas. Therefore, in this method, optical alignment is not required, and positional fluctuations caused by reading errors of the alignment marks and substrate distortion do not occur. In addition, substantially the entire upper surface end portion of the chip body can be covered with the protective resin, so that breakage and cut-out can be minimized.

While several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and alterations can be made without departing from the gist of the invention. These embodiments and their modifications fall within the scope and spirit of the invention, and are included in the scope of the invention described in claims and their equivalents.

The present embodiment includes the following modes.

[One]

A plurality of etching masks, each including a protective film, are formed on a semiconductor substrate, and a plurality of first regions protected by the plurality of etching masks in the semiconductor substrate and a second region which is an exposed region of the semiconductor substrate However,

The second region is anisotropically removed by a chemical etching treatment to form a plurality of grooves each having a sidewall at least partially located in the same plane as the end face of the etching mask and a bottom reaching the back face of the semiconductor substrate, And thereby the semiconductor substrate is divided into a plurality of chip bodies corresponding to the plurality of first regions

The method comprising the steps of:

[2]

The method according to [1], wherein the upper surface of the etching mask has no corner portion defined by two line segments with one end contacting each other.

[3]

The method according to [1], wherein the upper surface of the etching mask is a polygon having five or more sides.

[4]

The method according to any one of [1] to [3], wherein the chemical etching treatment includes the step of providing a noble metal catalyst in the second region, and then contacting the semiconductor substrate with an etching solution or an etching gas.

[5]

The noble metal catalyst is provided in the second region by electroless plating.

[6]

The process according to [4] or [5], wherein the noble metal catalyst is granular.

[7]

The method according to any one of [4] to [6], wherein the chemical etching treatment includes contacting the etching liquid to the semiconductor substrate, and the etching liquid includes hydrofluoric acid and hydrogen peroxide.

[8]

The chemical etching treatment may be carried out such that each of the plurality of chip bodies has a stripe-shaped concave portion or convex portion extending on the end face thereof from the face of the chip body on which the protective film is formed toward the opposite face , And the method according to any one of [1] to [7].

[9]

The method according to [8], wherein each of the concave or convex portions has a width of 10 to 100 nm.

[10]

The method according to [8], wherein each of the concave or convex portions has a width of 10 to 50 nm.

[11]

The method according to any one of [1] to [10], wherein the plurality of first regions includes a semiconductor element having an electrode pad.

[12]

The method according to any one of [1] to [11], wherein the semiconductor substrate is a silicon substrate.

[13]

A semiconductor chip comprising: a chip body having a surface region including a semiconductor element; and the end face of the chip body has an etching trace.

[14]

Wherein the etching trace is a striped concave portion or a convex portion extending from the surface of the chip body toward the surface on the opposite side from the surface of the chip body.

[15]

The semiconductor chip according to [14], wherein each of the concave portion and the convex portion has a width of 10 to 100 nm.

[16]

The semiconductor chip according to [14], wherein each of the concave portions or the convex portions has a width of 10 to 50 nm.

[17]

Wherein a contour of the surface of the chip body on the side of the surface region at least partially coincides with an orthorhombic contour of the protective film on a plane including a side of the surface region side, The semiconductor chip according to any one of [13] to [16].

[18]

The semiconductor chip according to any one of [13] to [17], wherein the surface of the chip body on the side of the surface region has no corner portion defined by two line segments whose ends are in contact with each other.

[19]

1. A semiconductor device comprising: a chip body having a surface region including a semiconductor element; and a protective film covering the surface region, wherein the chip body is formed by forming an etching mask including the protective film on a semiconductor substrate, Or a chemical etching process using an etching gas, and the outline of the surface of the chip body on the side of the surface region is at least partially coincident with the orthorhombic contour of the protective film on the plane including the upper surface Semiconductor chip.

[20]

The chip body is formed by forming an etching mask including a protective film on a semiconductor substrate and subjecting the semiconductor substrate to a chemical etching treatment using a noble metal catalyst and an etching solution or an etching gas And the surface of the chip body on the side of the surface region does not have a corner portion defined by two line segments with one end being in contact with each other.

[21]

A support member,

The semiconductor chip according to any one of [13] to [20], which is disposed on the support member,

A mold resin provided on the support member so as to cover the semiconductor chip;

.

[22]

A support member,

The semiconductor chip according to any one of [13] to [20], which is disposed on the support member,

And a joining member interposed between the support member and the semiconductor chip

.

10: semiconductor substrate
10 ': chip body
12:
14: etching mask
15:
16: Shield
18: Exposed area
18 ': Exposed area
20: dicing sheet
22: Precious metal catalyst
22a: Ag particles
24a: deep trench
24: separation groove
26: Needle-like residue
28: Semiconductor chip
28 ': Semiconductor chip
29: Side
30: etching solution
31: Side
32: Etch marks
34: Bonding material
35: substrate
36: Solder
40: Semiconductor device
41a: lead frame
41b: lead frame
43: Bonding material
45: Al wire
47a: Mold resin
47b: Mold resin
51: Electrode pad
52: electrode protection layer
54: Insulation layer
55: wiring layer
57: metal catalyst film
58: Resist pattern
59: Semiconductor chip
80: Metallized layer
82: Substrate grinding device

Claims (15)

A method of manufacturing a semiconductor chip,
A plurality of etching masks, each including a protective film, are formed on a semiconductor substrate, and a plurality of first regions protected by the plurality of etching masks in the semiconductor substrate and a second region which is an exposed region of the semiconductor substrate However,
The second region is anisotropically removed by a chemical etching treatment to form a plurality of grooves each having a sidewall at least partially located in the same plane as the end face of the etching mask and a bottom reaching the back face of the semiconductor substrate, And thereby the semiconductor substrate is divided into a plurality of chip bodies corresponding to the plurality of first regions
Wherein the semiconductor chip is a semiconductor chip. The method according to claim 1,
Wherein the upper surface of the etching mask does not have a corner portion defined by two line segments whose ends are in contact with each other. 3. The method of claim 2,
Wherein the chemical etching treatment includes a step of providing a noble metal catalyst in the second region, and then contacting the semiconductor substrate with an etching solution or an etching gas. The method of claim 3,
Wherein the noble metal catalyst is granular. 5. The method of claim 4,
The chemical etching treatment may be carried out such that each of the plurality of chip bodies has a stripe-shaped concave portion or convex portion extending on the end face thereof from the face of the chip body on which the protective film is formed toward the opposite face , A method of manufacturing a semiconductor chip. 6. The method of claim 5,
And each of the concave portions or the convex portions has a width of 10 to 100 nm. The method according to claim 6,
Wherein the semiconductor substrate is a silicon substrate. As a semiconductor chip,
And a chip body having a surface area including a semiconductor element, wherein the end surface of the chip body has a striped concave portion or a convex portion extending from the surface of the chip body toward the opposite surface, A semiconductor chip having an etching mark. 9. The method of claim 8,
And each of the concave or convex portions has a width of 10 to 100 nm. 10. The method of claim 9,
Wherein a contour of the surface of the chip body on the side of the surface region is at least partially overlapped with an orthogonal contour of the protective film on a plane including a side of the surface region side, Matching, semiconductor chip. 11. The method of claim 10,
Wherein the surface of the chip body on the side of the surface region does not have a corner defined by two line segments whose ends are in contact with each other. As a semiconductor chip,
1. A semiconductor device comprising: a chip body having a surface region including a semiconductor element; and a protective film covering the surface region, wherein the chip body is formed by forming an etching mask including the protective film on a semiconductor substrate, Or a chemical etching process using an etching gas, and the outline of the surface of the chip body on the side of the surface region is at least partially coincident with the orthorhombic contour of the protective film on the plane including the upper surface , Semiconductor chips. As a semiconductor chip,
The chip body is formed by forming an etching mask including a protective film on a semiconductor substrate and subjecting the semiconductor substrate to a chemical etching treatment using a noble metal catalyst and an etching solution or an etching gas And the surface of the chip body on the side of the surface region does not have a corner defined by two line segments whose ends are in contact with each other. A semiconductor device comprising:
A support member,
A semiconductor chip according to claim 8 positioned on the support member,
A mold resin provided on the support member so as to cover the semiconductor chip;
And a semiconductor device. A semiconductor device comprising:
A support member,
A semiconductor chip according to claim 8 positioned on the support member,
And a joining member interposed between the support member and the semiconductor chip
And a semiconductor device.

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