TWI505343B - Semiconductor die singulation method - Google Patents

Description

Semiconductor wafer segmentation method

The present invention relates generally to electronic devices, and more particularly to methods of forming semiconductors.

In the past, the semiconductor industry utilized a variety of different methods and devices to separate individual semiconductor wafers from semiconductor wafers from which wafers were fabricated. Typically, a technique known as scribing or dicing is used to use a diamond cutting wheel or wafer saw along a scribe line formed on a wafer between individual wafers. The grid is cut partially or completely through the wafer. To account for the alignment and width of the cutting tool, each scribe grid typically has a large width, typically about one hundred and fifty (150) microns, which consumes a significant portion of the semiconductor wafer. In addition, the time required to scribe all of the scribe grids over the entire semiconductor wafer can exceed one hour. This time reduces the production and manufacturing capacity in the manufacturing field.

Another method of dividing individual semiconductor wafers is to use a laser to cut through the wafer along the scribe grid. However, laser dicing is difficult to control and can result in uneven separation. Laser scribing also requires expensive lasers and protective devices used by operators. Moreover, it has been reported that laser dicing reduces the strength of the wafer because during the singulation, the laser melts the crystal structure along the periphery of the wafer.

Accordingly, it would be desirable to have a method of singulating wafers from a semiconductor wafer that increases the number of semiconductor wafers on the wafer; provides more uniform segmentation; reduces the time to perform segmentation; and has a narrower scribe line.

For the sake of easy and clear illustration, the elements in the figures are not necessarily to scale, and the same reference numerals are used in the different figures. In addition, descriptions and details of well-known steps and elements are omitted for ease of description. In order to clarify the drawing, the doped regions in the device structure are shown as having generally linear perimeters and angularly accurate corners. However, it will be understood by those skilled in the art that due to the diffusion and activation of the dopant, the perimeter of the doped region may not generally be straight and its corners may not be at precise angles. It will be appreciated by those skilled in the art that the use of the words "approximately" or "substantially" means that the component values expected to have parameters are very close to a set value or set position. However, as is well known in the art, there will always be a slight difference that prevents the value or position from being strictly the same as the set value. In the art, as long as the ideal goal as described, up to at least ten percent (10%) (and as much as twenty-half (20%) of the semiconductor doping concentration) can be accepted as a reasonable difference. .

1 is a simplified plan view illustrating a semiconductor wafer 10 having a plurality of semiconductor wafers, such as wafers 12, 14, and 16, formed on the semiconductor wafer 10. The wafers 12, 14, and 16 are spaced apart from one another on the wafer 10, which form dividing lines, such as dividing lines 13 and 15, in the spaces. As is known in the art, all of the plurality of semiconductor wafers are generally separated from each other on all sides by forming dividing lines, such as lines 13 and 15, by regions.

2 shows an enlarged cross-sectional portion of wafer 10 of FIG. 1 taken along line 2-2. For purposes of clarity of the drawings and the description thereof, the cut lines 2-2 are only cross-section of the wafer 12 and portions of the wafers 14 and 16. Wafers 12, 14, and 16 can be any type of semiconductor wafer that includes a diode, a vertical transistor, a lateral transistor, or an integrated circuit including various different types of semiconductor devices. Semiconductor wafers 12, 14, and 16 generally include a semiconductor substrate 18 that can have doped regions formed within substrate 18 to form active and passive portions of the semiconductor wafer. The cross-sectional portion shown in FIG. 2 is taken along the contact pads 24 of each of the wafers 12, 14, and 16. Contact pads 24 are typically metallic and are formed on a semiconductor wafer to provide electrical contact between the semiconductor wafer and external components of the semiconductor wafer. For example, the contact pads 24 can be formed to receive bond wires that can be subsequently attached to the pads 24, or can be formed to receive solder balls or other types of interconnect structures that can be subsequently attached to the pads 24. The substrate 18 includes a block substrate 19 having an epitaxial layer 20 formed on the surface of the block substrate 19. A portion of the epitaxial layer 20 can be doped to form a doped region 21 that is used to form the active and passive portions of the semiconductor wafer 12, 14, or 16. Layer 20 and/or region 21 may be omitted in some embodiments or may be in other regions of wafer 12, 14, or 16. Typically, a dielectric 23 is formed on the top surface of the substrate 18 to isolate the pads 24 from other portions of the individual semiconductor wafers and to insulate each of the pads 24 from adjacent semiconductor wafers. The dielectric 23 is typically a thin layer of ruthenium dioxide formed on the surface of the substrate 18. Contact pad 24 is generally metallic, with a portion of contact pad 24 in electrical contact with substrate 18 and another portion of which is formed on a portion of dielectric 23. Subsequent to the formation of wafers 12, 14, and 16 including metal contacts and associated interlayer dielectrics (not shown), dielectric 26 is typically formed over all of the plurality of semiconductor wafers to act on wafer 10 And a passivation layer for each individual semiconductor wafer 12, 14, and 16. Dielectric 26 is typically formed over the entire surface of wafer 10, such as by blanket dielectric precipitation, and in some embodiments may be formed under contact pads 24. The thickness of the dielectric 26 is generally greater than the thickness of the dielectric 23.

3 shows a cross-sectional portion of wafer 10 of FIG. 2 at a subsequent stage in the process of dividing wafers 12, 14, and 16 from wafer 10. After forming the passivation layer of dielectric 26, a mask 32, shown by dashed lines, can be applied to the surface of substrate 18 and patterned to form openings that are exposed to cover each pad 24 and overlying the crystal Portions of the dielectric 26 on portions of the circle 10, on portions of the wafer 10, form dividing lines, such as dividing lines 13 and 15. Thereafter, dielectrics 26 and 23 are etched through openings in mask 32 to expose the pads 24 and the surface of substrate 18 beneath them. Openings through the dielectrics 26 and 23 are formed in the regions where the dividing lines such as the lines 13 and 15 are formed, which function to divide the openings 28 and 29. An opening formed through the dielectric 26 overlying the pad 24 acts as a contact opening. The etching process is preferably performed using a process that selectively etches the dielectric faster than etching the metal. The etching process typically etches the dielectric at least ten (10) times faster than the etched metal. The material for the substrate 18 is preferably tantalum, and the material for the dielectric 26 is preferably hafnium oxide or tantalum nitride. The material of dielectric 26 can also be other dielectric materials that can be etched while not etching the material of pad 24, such as polyimide. The metal of pad 24 acts as an etch stop layer that prevents the exposed portions of pad 24 from being removed by etching. In a preferred embodiment, a fluorine-based anisotropic reactive ion etching process is used.

After the opening through the dielectric 26 is formed, the mask 32 is removed and the substrate 18 is thinned to remove material from the bottom surface 17 of the substrate 18 and reduce the thickness of the substrate 18. Generally, substrate 18 is thinned to a thickness of no greater than about one hundred to two hundred (100 to 200) microns. Such thinning programs are well known to those skilled in the art. After thinning the wafer 10, the bottom surface of the wafer 10 including the bottom surface 17 of the substrate 18 can be metallized with a metal layer 27. In some embodiments, this metallization step can be omitted. Subsequently, wafer 10 is typically attached to a conveyor belt or carrier tape 30 that assists in supporting the plurality of wafers after dividing the plurality of wafers. Such carrier tapes are well known to those skilled in the art.

4 shows the wafer 10 on a subsequent stage in the process of singulating the semiconductor wafers 12, 14, and 16 from the wafer 10. The substrate 18 is etched through the split openings 28 and 29 formed in the dielectric 26. The etching process causes the split openings 28 and 29 to extend from the top surface of the substrate 18 and completely penetrate the substrate 18. This etching process is typically performed using chemistry that selectively etches germanium at a much higher rate than the dielectric or metal. The etch process is typically at least fifty (50) times faster than the etched dielectric or metal, and preferably one hundred (100) times faster. Typically, a deep reactive ion etching system using a combination of isotropic and anisotropic etching conditions is used to etch openings 28 and 29 that completely penetrate the bottom surface of substrate 18 from the top surface of substrate 18. In a preferred embodiment, a process commonly referred to as a Bosch process is used to anisotropically etch the split openings 28 and 29 through the substrate 18. In one example, wafer 10 is etched using a Bosch process in an Alcatel deep reactive ion etching system.

The width of the split openings 28 and 29 is typically five to ten (5-10) microns. Such a width is sufficient to ensure that openings 28 and 29 are formed through the substrate 18 completely, and the width is also sufficiently narrow to enable the formation of openings in short time intervals. Typically, openings 28 and 29 are formed through the substrate 18 over a time interval of approximately fifteen to thirty (15 to 30) minutes. Because all of the dividing lines of wafer 10 are formed simultaneously, all of the dividing lines spanning wafer 10 can be formed in the same time interval of approximately fifteen to thirty (15 to 30) minutes. Thereafter, wafer 10 is supported by carrier tape 30 while wafer 10 is brought to a selection and placement device 35 by which each individual wafer can be removed from wafer 10. Typically, device 35 has a pedestal or other tool that pushes each of the divided wafers, such as wafer 12, upwardly to release it from carrier tape 30 and rise all the way to a vacuum picker (not shown), which will The segmented wafer is removed. During the selection and placement process, a portion of the metal layer 27 under the openings 28 and 29 breaks and remains on the carrier tape 30.

Figure 5 shows an enlarged cross-sectional portion of semiconductor wafers 42, 44, and 46 that are formed on wafer 10 and are available for wafers 12, 14, and 16 as illustrated in the description of Figures 1-4. The chosen implementation. Wafers 42, 44, and 46 are shown after the formation of dielectric 23 on the top surface of substrate 18 and in the fabrication state prior to formation of pad 24 (FIG. 1). The wafers 42, 44, and 46 are similar to the wafers 12, 14, and 16 except that the wafers 42, 44, and 46 each have respective isolation trenches 50, 54, and 46 that surround the isolation trench. The wafer is also isolated from adjacent wafers. The trenches 50, 54, and 58 are typically formed adjacent the outer perimeter of each wafer. Grooves 50, 54, and 58 is formed to extend from the top surface of the substrate 18 into the block substrate 19 at a first distance. Each of the trenches 50, 54, and 58 is generally formed as an opening into the substrate 19 having a dielectric formed on the sidewalls of the opening and is typically filled with a dielectric or other material such as germanium or polysilicon. For example, the trench 50 can include a ceria dielectric 51 on the sidewalls of the trench opening and can be filled with a polysilicon 52. Similarly, trenches 54 and 58 each comprise ruthenium dioxide dielectrics 55 and 59 on the sidewalls of the trench opening and may be filled with polysilicon 56 and 60. A dividing line 43 is formed between the grooves 50 and 54, and a dividing line 45 is formed between the grooves 50 and 58. The trenches 50 and 54 are formed adjacent to the dividing line 43, and the trenches 50 and 58 are formed adjacent to the dividing line 45. Methods of forming trenches 50, 54, and 58 are well known to those skilled in the art. It should be noted that the trenches 50 and 54 are for illustrative purposes only and can be any number of isolated trenches or trenches of various shapes and sizes, or a combination thereof.

6 shows a wafer 10 on a subsequent stage in the process of singulating semiconductor wafers 42, 44, and 46 from wafer 10 in accordance with the present invention. After forming trenches 50, 54, and 58, other portions of wafers 42, 44, and 46 are formed, including forming contact pads 24, and forming dielectrics 26 that cover wafers 42, 44, and 46. Dielectric 26 also generally covers other portions of wafer 10, including portions of substrate 18 where segment lines 43 and 45 are to be formed. Thereafter, the mask 32 is applied and patterned to expose the underlying dielectric 26 to be formed at the dividing line and the contact opening. Dielectric 26 is etched through openings in mask 32 to expose the underlying pads 24 and the surface of substrate 18. The openings formed through the dielectric 26 in the regions where the dividing lines (such as the lines 43 and 45) are to be formed function as the dividing openings 47 and 48. Used to form openings 47 and 48 through dielectrics 23 and 26. The etching process is substantially the same as the process used to form openings 28 and 29 (Fig. 3) in dielectrics 23 and 26. Openings 47 and 48 are preferably formed such that dielectrics 51, 55, and 59 on the sidewalls of respective trenches 50, 54, and 58 are not located under openings 47 and 48 such that these dielectrics are subsequently formed The operation of the dividing lines 43 and 45 is not affected.

After forming openings 47 and 48 through dielectric 26, mask 32 is removed, and substrate 18 is thinned and metallized with metal layer 27, as previously explained in the description of FIG. In some embodiments, this step of metallization can be omitted. After metallization, wafer 10 is typically attached to carrier tape 30.

FIG. 7 shows the wafer 10 on a subsequent stage in the process of dividing the semiconductor wafers 42, 44, and 46 in the wafer 10. The substrate 18 is etched through the split openings 47 and 48 formed in the dielectric 26. The etching process extends the split openings 47 and 48, i.e., completely through the substrate 18 from the top surface of the substrate 18. Openings 47 and 48 are typically at least 0.5 microns from dielectrics 51, 55, and 59. The etching process is typically an isotropic etch that selectively etches germanium at a rate that is much higher than the rate at which the dielectric or metal is etched, typically at least fifty (50) times faster than the rate of etching the dielectric or metal. Preferably, it is one hundred (100) times faster. Since the dielectric on the sidewalls of the trench protects the germanium of the substrate 18, isotropic etching can be used. The amount of etching of the isotropic etch is much higher compared to the amount of etch obtained using the Bosch process or the limited use of the Bosch process. However, the isotropic etch typically cuts portions of the substrate 19 underlying the trenches 50, 54, and 58 from the lower portion. Typically, downstream etching using fluorochemical action is used to completely penetrate the substrate from the top surface of the substrate 18. The bottom surface of 18 etches openings 28 and 29 and exposes a portion of metal layer 27 under openings 28 and 29. In one example, wafer 10 is etched using a deep reactive ion etching system that uses fully isotropic etching, which can be purchased from various manufacturers, including a system FL 33716 Purchased at PlasmaTherm, LLC at 10050 16th Street North St. Petersburg. In other embodiments, an isotropic etch can be used for most etches, while an anisotropic etch can be used for another portion of the etch (Bosch process). For example, an isotropic etch can be used until the depth of extension of openings 28 and 29 is substantially the same as the depth of trenches 50, 54, and 58, and an anisotropic etch can then be used to prevent trenches 50 from being cut from the lower portion. , 54, and 58.

The width of the split openings 47 and 48 is generally about the same as the width of the openings 28 and 29. The wafers 42, 44, and 46 can be removed from the carrier tape 30 in a manner similar to the removal of the wafers 12, 14, and 16.

In another embodiment, the grooves 50 and 58 can be spaced apart by a first distance sufficient to allow a standard dicing tool or wafer saw to extend through the opening 48. Thus, portions of the metal layer 27 located below the opening 48 may be severed by a dicing tool or wafer saw; or may be separated along the openings 47 and 48 in order to break the wafer 10 below the openings 47 and 48 by bending over the drum. Or use other techniques such as laser scribing, etc. to remove. The trenches 50 and 54 can have similar spacing which helps to cut portions of the underlying metal layer 27 in a similar manner. For the method of dicing the metal layer 27 using a dicing tool, the metal layer 27 can be broken along the path of the dicing tool to complete the separation. Thereafter, the wafers 42, 44, and the wafers 40, 44 can be removed from the carrier tape 30 by standard selection and placement techniques. 46. These methods help to separate and divide the wafers 42, 44, and 46.

Alternatively, isotropic etching may be terminated when the depths of the openings 47 and 48 reach the bottom of the trenches 50, 54, and 58 or just past the bottom of the trench. Thereafter, the exposed portion of the substrate 19 can be diced with a dicing tool, or sawed with a wafer saw to complete the separation of the wafer or other techniques such as laser cutting, etc., to remove the wafer. The sawing technique can be extended to perform sawing through the metal layer 27. The dicing technique will break the metal layer 27 as the material of the substrate 19 breaks along the path formed by the dicing tool.

Those skilled in the art will appreciate that the use of trenches 50, 54, and 58 to divide the wafer will result in wafers 42, 44, and 46 having smooth sidewalls that pass through the dielectric sidewalls of the trench and the wafer. The external components are insulated. The dielectric forms a dielectric material on the sidewalls of the wafer. The insulation provided by the trench dielectric can reduce leakage current between the wafer and external components. This structure can also increase the breakdown voltage of the wafer. The use of the trenches 50, 54, and 58 also improves the strength of the wafer compared to the laser split wafer method.

Referring again to the etching technique used to extend the openings 47 and 48 into the substrate 19, those skilled in the art will appreciate that isotropic etching etches faster than anisotropic etching, thus using omnidirectional The isotropic etch is performed to quickly remove the material of the opening until the openings 47 and 48 extend as deep as the grooves 50, 54, and 58. Subsequently, anisotropic etching is used to prevent the trenches 50, 54, and 58 from being cut from the lower portion. Thus, the anisotropic etching immediately after the isotropic etch is used to provide high yield and good lateral control, even for portions of openings 47 and 48 deeper than trenches 50, 54, and 58. .

FIG. 8 illustrates one stage in an exemplary embodiment of another alternative method of splitting semiconductor wafers 71, 72, and 73 formed on semiconductor wafer 10. Figure 8 shows an enlarged cross-sectional portion of wafers 71-73 after forming dielectric 23 on the top surface of substrate 18 and in a fabricated state prior to forming pads 24 (Figure 2). These wafers 71-73 are similar to wafers 42, 44, and 46 except that the wafers 71-73 have a single isolation trench 79 surrounding each wafer on the wafer 10.

As will be seen hereinafter, an example of a method of singulating a semiconductor wafer from wafer 10 includes providing a semiconductor wafer, such as wafer 10, having a semiconductor substrate, such as substrate 18, and also having a formation on a semiconductor substrate. a plurality of semiconductor wafers, wherein the semiconductor wafers are separated from one another by portions of the semiconductor wafer, and wherein portions of the semiconductor wafer are at locations where division lines, such as lines 13 and 15, are to be formed; A trench, such as trench 79, is formed over portions of the wafer, wherein the trench surrounds a perimeter of each of the plurality of semiconductor wafers, including forming a dielectric layer on the sidewalls of the trench and forming a fill in the trench a material, and the fill material adjoins the dielectric layer on the sidewall; forming a passivation layer covering portions of the plurality of semiconductor wafers, such as layer 26; etching through the passivation layer and any first opening of the underlying layer, such as opening 82, At least exposing the filling material of the trench; and etching a second opening such as opening 81 that extends through the fill material and is located therethrough Filling materials following any portion of a semiconductor substrate, such that the second opening extends from the surface of the semiconductor wafer completely through the semiconductor substrate, wherein etching the second opening through the first opening is performed.

Another embodiment of the method further includes forming a trench opening extending from the surface of the semiconductor substrate into the semiconductor substrate at a first distance, wherein the first portion of the semiconductor substrate is below the trench opening, and wherein the trench opening has a sidewall and a bottom; a dielectric layer is formed on the sidewall of the trench opening and the bottom of the trench opening, and a portion of the trench opening is left between the sidewalls as an unused space; removing the dielectric on the bottom of the trench opening And the dielectric layer adjoining the sidewalls of the trench fills the unused space of the trench opening with a filling material.

The formation of the trenches 79 is similar to the trenches 50, 54, or 58 except that the trenches 79 extend around the perimeter of each of the wafers 71-73 and the perimeter of any other wafers formed on the wafer 10. Any of them has been described in the description of Figures 5-7. The trenches 79 are formed to include a dielectric liner 80, such as hafnium oxide, on the sidewalls and bottom of the trenches 79. In the preferred embodiment, the bottom of dielectric liner 80 is removed such that the bottom of trench 79 is open, as shown by dashed line 84. One example method of removing the bottom of liner 80 includes applying a mask 85 having an opening that exposes trenches 79, and performing an anisotropic etch, such as a spacer etch, which etches through liner 80. bottom. The dielectric on the crucible can be selectively etched to prevent damage to portions of the substrate 18 underlying the trenches 79. Generally, the mask 85 is removed after the bottom of the liner 80 is removed. After the bottom of the trench 79 is removed, the remaining opening of the trench 79 is filled with a fill material 81. Filler material 81 is typically a germanium based material, such as polysilicon, to facilitate subsequent process steps, as will be seen later.

Those skilled in the art will appreciate that any of the wafers 71-73 can also have other trenches, such as trenches 78, inside the wafer, and the process operations and trenches that can be used when forming the trenches The same as used at 79. Depending on the function to be provided, the trenches 78 may hold the bottom oxide or cause the bottom oxide to be removed. For example, the trenches 78 can be filled with doped polysilicon and provide low impedance substrate contacts or back contacts such as to the metal layer 27 (not shown in Figure 8) or to another contact on the bottom or back side of the substrate 18. . However, the preferred embodiment of trench 78 does not have a removed bottom, and trench 78 is preferably internal to the wafer and does not surround the outer perimeter of the wafer. Thus, the trenches 79 can be formed simultaneously with the trenches 78, or other similar trenches, thereby reducing manufacturing costs. As will be appreciated by those skilled in the art, wafers 71-73 can have a variety of different active or passive components formed on or within substrate 18.

The grooves 79 are formed in the dividing lines 76 and 77, and are preferably in the middle of the dividing lines such that the middle of the groove 79 is approximately the middle of the dividing line. As will be seen hereinafter, the segmentation occurs approximately through the middle of the groove 79.

FIG. 9 illustrates wafer 10 on a subsequent stage in an exemplary method of singulating semiconductor wafers 71-73 from wafer 10. After forming trenches 79, other portions of wafers 71-73 are formed, including: forming contact pads 24 and forming dielectrics 26 that cover wafers 71-73. Dielectric 26 also generally covers other portions of wafer 10 that include portions of substrate 18 where segment lines 77 and 76 are to be formed. Thereafter, a mask 87 is applied and patterned to expose the underlying dielectric 26 to be formed, as well as the dielectric 26 at the contact opening. The mask 87 is similar to the mask 32 shown in Figure 3; however, the position of the mask 87 is typically slightly different. The openings of the mask 87 where the dividing lines 76 and 77 are to be formed are also above the grooves 79. Dielectric 26 is etched through openings in mask 87 to expose fill material 81 located in trenches 79 below. Typically, the etch also exposes the underlying pad 24. The openings formed through the dielectric 26 in the regions where the dividing lines are to be formed, such as lines 76 and 77, act to divide the openings 82 and 83. The etching process used to form openings 82 and 83 through dielectric 26 is substantially the same as the process used to form openings 28 and 29 (FIG. 3) in dielectrics 23 and 26. Openings 82 and 83 are typically formed such that dielectric liner 80 on the sidewalls of respective trenches 79 are located below openings 82 and 83, however, as long as material 81 is exposed, it is not necessary to expose dielectric liner 80 again. Typically, because it is a cross-sectional view, although openings 82 and 83 are two portions of a single opening around wafers 71-73, they are still shown as two openings.

After forming openings 82 and 83 through dielectric 26, mask 87 is removed, as shown by the dashed lines, and substrate 18 is thinned, as shown by dashed line 86. The thinning removes a majority of the substrate 18 located below the trenches 79. Substrate 18 is generally not thinned all the way up to the bottom of trench 79 because the dielectric material of dielectric liner 80 may damage the tool used to thin wafer 10 or may result in a scratched wafer 10. Preferably, substrate 18 is thinned until trench 79 is about two to five (2-5) microns from the bottom of substrate 18. In some embodiments, the substrate 18 can be thinned until the bottom of the trench 79 is exposed. Thereafter, the bottom surface of the substrate 18 is metallized with a metal layer 27, as previously explained in the description of FIG. This metallization step can be omitted in some embodiments. Subsequently, wafer 10 is typically connected to a common carrier substrate or a common carrier, such as carrier tape 30.

FIG. 10 illustrates wafer 10 on a subsequent stage in an example of an embodiment of a method of dividing wafers 71-73 from wafer 10. A second opening is formed through the fill material 81 to form dividing lines 76 and 77 through the substrate 18. Similar to the etching illustrated in the description of FIG. 4, the substrate 18 is preferably etched through the split openings 82 and 83 using the dielectric 26 as a mask. The etching process forms an opening through the material 81. Typically, the etch removes substantially all of the material 81 to extend the dividing lines 76 and 77, which extend completely through the fill material 81 of the trenches 79 from the top surface of the substrate 18. The etching process is typically an isotropic etch that selectively etches germanium at a rate that is much higher than the rate at which the dielectric or metal is etched, typically at least fifty (50) times faster than the rate of etching the dielectric or metal. Preferably, it is one hundred (100) times faster. Because the etching step is selective for germanium on the dielectric, the fill material 81 is removed without etching the dielectric liner 80 on the sidewalls of the trench 79. Thus, the dielectric liner 80 on the sidewalls of the trenches 79 protects the turns of the substrate 18 from isotropic etching. The amount of etching of the isotropic etch is much higher compared to the amount of etch obtained using the Bosch process or the limited use of the Bosch process. The isotropic etch process etches through the fill material 81 and any portion of the substrate 18 underlying the trenches 79. Thus, an isotropic etch quickly etches through portions of trenches 79 and any underlying substrate 18, thereby dicing wafers 71-73. Rapid etching improves throughput and reduces manufacturing costs. Those skilled in the art will appreciate that the bismuth based material in the fill material 81 also reduces stress on the material of the dielectric liner 80 and substrate 19.

Dividing the wafers 71-73 along the dividing lines 76 and 77 of the through-groove 79 results in the dividing line occupying only a small space on the semiconductor wafer. For example, the width of the trenches 79 comprising the fill material 81 is typically only about three (3) microns wide. Thus, the dividing lines 76 and 77 may be only about three microns wide, rather than one hundred microns wide in other wafer segmentation methods, such as dicing or wafer sawing methods. It will be apparent to those skilled in the art that the step of thinning the wafer 10 can be omitted and the etching of the material 81 can continue until the openings 82 and 83 extend through the wafer 10.

As illustrated in the description of FIG. 4, the selection and placement tool can be used to break any portion of the metal layer 27 under the openings 82 and 83 to complete the segmentation of the wafers 71-73. Those skilled in the art will appreciate that other methods can be used to sever the metal layer 27 within the dividing lines 76 and 77. For example, the metal layer 27 may be diced along the bottom side of the metal layer 27 prior to application of the carrier tape 30, so that when the pick and place action is performed, the metal layer 27 will be severed along this line. Alternatively, portions of the metal layer 27 under the dividing lines 76 and 77 may be etched from the back side of the metal layer 27 before the carrier tape 30 is applied. The metal layer 27 is etched to divide the metal layer 27. Another method of cutting the metal layer 27 is to blow an air jet onto a portion of the carrier tape 30 located below the wafer 10. The air will cause the carrier tape 30 to extend upward and cut the metal layer 27, i.e., cut in portions of the metal layer 27 located below the dividing lines 76 and 77. Additionally, an undisplayed second carrier tape can be placed on the front side of the wafer 10. The carrier tape 30 can then be removed. The step of removing the carrier tape 30 will sever the metal layer 27, i.e., cut in portions of the metal layer 27 located below the dividing lines 76 and 77. Any of these alternative methods of severing the metal layer 27 can be used for any of the segmentation methods described herein.

Figure 11 illustrates a stage in an exemplary embodiment of another alternative method of splitting semiconductor wafers 12, 14, and 16 that has been described in the description of Figures 1 and 2-4.

As will be seen below, an example of a method of singulating a semiconductor wafer from a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers Forming the semiconductor wafer on a semiconductor substrate and separating from each other by a portion of the semiconductor wafer at which the dividing line is to be formed; forming a split mask layer covering a plurality of semiconductor wafers, such as AlN 93; forming a through-segment An opening of the cap layer; forming an opening through the underlying layer and exposing a portion of the surface of the semiconductor substrate; and using the opening in the split mask layer as a mask while etching the first opening to extend from the exposed portion of the surface of the semiconductor substrate, And completely through the semiconductor wafer.

Another embodiment of the method further includes: connecting the semiconductor wafer to the carrier tape prior to using the opening in the split mask layer as a mask; and further comprising using the selection and placement device to separate the carrier tape, and A semiconductor wafer of a plurality of semiconductor wafers is separated from other wafers of a plurality of semiconductor wafers.

Another embodiment of the method includes: forming a split mask layer, the material being a metal compound, aluminum nitride, titanium nitride, metal-antimony compound, titanium telluride, aluminum telluride, polymer, or polyimine One of the layers.

Wafers 12, 14, and 16 are shown in a fabricated state after the formation of dielectric 23 on the top surface of substrate 18 and subsequent formation of pad 24 and dielectric 26, as illustrated in the description of FIG. After forming the dielectric 26, a split mask is formed to facilitate formation of the opening through the substrate 18 without etching the underlying layer, such as portions of the dielectric 26. In a preferred embodiment, the split mask is formed from aluminum nitride (AlN). In the preferred embodiment, the AlN layer 91 is formed on at least the dielectric 26. In general, layer 91 is applied to cover all wafers 10.

12 illustrates a cross-sectional portion of wafer 10 of FIG. 11 at a subsequent stage in an example of a preferred embodiment of a method of singulating wafers 12, 14, and 16 from wafer 10. After forming the AlN layer 91, a mask 32 can be applied to the surface of the substrate 18 and patterned to form openings that expose portions of the dielectric 26 that cover each pad 24 and are also covered to form A dividing line, such as portions of the wafer 10 at the dividing lines 13 and 15.

To form the mask 32, a photographic masking material is applied over the wafer 10, and the wafer 10 is then exposed to light, such as ultraviolet light, to modify the chemical composition of the exposed portion of the masking material to form an opening having A mask 32 covering the position where the dividing line is to be formed and the pad 24 is to be formed. The unexposed portion of the masking material is then removed using the developer, thereby leaving a mask 32 with openings 28 and 29 that cover the locations where the respective dividing lines 13 and 15 are to be formed. It has been discovered that a developer based on ammonium hydroxide can also be used to remove a portion of the AlN layer 91 that is below the unexposed portion of the masking material. The removed portion of layer 91 is shown with dashed line 92 and the remaining portion of layer 91 is identified as AlN 93. As will be seen below, AlN 93 acts as a split mask.

13 shows a cross-sectional portion of the wafer 10 of FIG. 12 at another subsequent stage in an example of an alternative embodiment of the method of singulating wafers 12, 14, and 16 from wafer 10. Dielectrics 26 and 23 are etched through openings in mask 32 and AlN 93 to expose the underlying pads 24 and the surface of substrate 18. Openings through the AlN 93 and the dielectrics 26 and 23 are formed in the regions where the dividing lines are to be formed, such as the lines 13 and 15, as the split openings 28 and 29. The opening formed through the dielectric 26 of the cover pad 24 acts as a contact opening. The etching process is preferably performed wherein the process used selectively etches a germanium based dielectric such as hafnium oxide or tantalum nitride faster than etching the metal. The etching process etches the germanium-based dielectric generally at least ten (10) times faster than its etching of the metal. The metal of pad 24 acts as an etch stop layer that prevents the exposed portions of pad 24 from being removed by etching. In a preferred embodiment, an anisotropic reactive ion etching using a fluorine group is used as explained above.

After the openings through the dielectrics 26 and 23 are formed, as shown by the dashed lines, the mask 32 is typically removed. As shown by dashed line 86, substrate 18 is typically thinned to remove material from the bottom surface of substrate 18 and reduce the thickness of substrate 18. Generally, substrate 18 is thinned to a thickness of no greater than about twenty-five to four hundred (25 to 400) microns, and preferably between about fifty and two hundred fifty (50-250) microns. . Such thinning programs are well known to those skilled in the art. After the wafer 10 is thinned, the metal layer 27 can be used to metallize the back side of the wafer 10. In some embodiments, this metallization step can be omitted. Subsequently, wafer 10 is typically attached to a conveyor belt or carrier tape 30 that assists in supporting the plurality of wafers after dividing the plurality of wafers.

FIG. 14 illustrates wafer 10 on a subsequent stage in an exemplary embodiment of an alternative method of singulating semiconductor wafers 12, 14, and 16 from wafer 10. AlN 93 is used as a mask to etch the substrate 18 through the split openings 28 and 29. AlN 93 protects dielectric 26 from etching. The AlN 93 can have a thickness of about fifty to three hundred (50-300) angstroms and still protect the dielectric 26. Preferably, the AlN 93 has a thickness of about two hundred (200) angstroms. The etching process causes the split openings 28 and 29 to extend from the top surface of the substrate 18 and completely through the substrate 18. As with the Bosch process illustrated in the description of FIG. 4, the etching process is typically performed using a chemical action that selectively etches germanium at a much higher rate than etching the dielectric or metal. The wafers 12, 14, and 16 can then be removed from the carrier tape 30, as illustrated in the description of FIG.

Because AlN 93 is a dielectric, it can be left on wafers 12, 14, and 16. In other embodiments, AlN 93 may be removed after etching through substrate 18, such as by using a developer; however, this requires additional processing steps. The use of a light masking developer to remove the exposed portions of layer 91 saves processing steps, thereby reducing manufacturing costs. Using AlN 93 as a mask protects dielectric 26 from the effects of etching operations.

Those skilled in the art will appreciate that AlN 93 can be used as a split mask to protect dielectric 26 in any of the segmentation methods described herein, including the description of Figures 5-7. The illustrated method, such as the method illustrated in Figure 15, and AlN 93 can also be used in the methods illustrated in the description of Figures 8-10.

In other embodiments, the split mask can be formed from materials other than AlN. These other materials used to divide the mask are those that are not generally used to etch the ruthenium of the substrate 18. Since the etching process used to etch the substrate 18 etches germanium faster than etching the metal, a metal compound can be used as the material for forming the split mask. Examples of such metal compounds include: AlN, titanium nitride, titanium oxide, titanium oxynitride, and others. Metal compound. In the case of using a metal compound other than AlN, a metal compound layer can be applied similarly to the layer 91. A mask 32 can then be used to pattern the metal compound layer to form openings in the metal compound. Thereafter, the mask 32 can be removed and the remainder of the metal compound can protect the underlying layer, such as the dielectric 26, during etching of the substrate 18. The metal compound may be left on the wafer to be subsequently divided, or may be removed prior to completion of the segmentation, such as prior to detaching the wafer from the carrier tape 30.

Alternatively, a bismuth-metal compound can be used to form the split mask because the metal in the metal-germanium compound prevents etching from continuing into the metal-germanium material. Some examples of ruthenium-metal compounds include metal halides such as titanium telluride and cobalt telluride. For embodiments of the ruthenium-metal compound, the ruthenium-metal compound layer can be formed and patterned similarly to the example of the metal compound. However, the metal-germanium compound is typically a conductor and must therefore be removed from the wafer, such as to remove the metal-germanium compound prior to completing the singulation of the wafer from the carrier tape 30.

Moreover, the polymer can be used to separate the mask. An example of a suitable polymer is polyimine. Other well known polymers can also be used. Similar to a metal compound, the polymer can be patterned and subsequently removed or left on the wafer.

Figure 16 illustrates a stage in an exemplary embodiment of another alternative method of splitting semiconductor wafers 12, 14, and 16 that has been illustrated in the description of Figures 1 and 2-4.

As will be seen hereinafter, an example of a method of singulating a semiconductor wafer from a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate and having a plurality of semiconductor wafers formed on the semiconductor substrate, And separating from each other by portions of the semiconductor substrate at which the dividing lines are to be formed; and etching a dividing line opening penetrating portions of the semiconductor substrate, wherein the dividing line opening is formed from the first surface of the semiconductor substrate, thereby resulting in The spacing between the plurality of semiconductor wafers forms a sidewall of the semiconductor wafer, wherein the top surface of the semiconductor wafer has a greater width than the bottom surface of the semiconductor wafer.

In another embodiment, the method further includes etching the split line opening to include forming a top surface width of the wafer that is approximately two to ten (2-10) microns larger than the bottom surface width.

Another alternative method includes using an anisotropic etch to etch a split line opening into the semiconductor substrate at a first distance; and etching the split line opening using an isotropic etch to extend the split line opening to The two distances also increase the width of the split line opening.

As will be seen hereinafter, the segmentation method forms angled sidewalls with respect to wafers 12, 14, and 16, such that the lateral width of the wafer is greater at the top of the wafer than at the bottom of the wafer. Wafer 10 and wafers 12, 14, and 16 are shown in a fabricated state after etching through dielectrics 26 and 23 to expose substrate 18 and pad 24, as illustrated in the description of FIG. Alternatively, AlN 93 can be used as a mask for subsequent operations, as explained in the description of Figures 11-14.

Subsequently, in order to expose the surface of the substrate 18, the substrate 18 and any exposed pads 24 are etched using an isotropic etching process that is selected at a much higher rate than the etched dielectric or metal. The etch enthalpy is typically at least fifty (50) times faster than the rate of etching the dielectric or metal, and preferably at least one hundred (100) times faster, as illustrated in the description of FIG. same. An etch process is performed to extend the openings 28 and 29 into the substrate 18 to a depth that laterally extends the width of the opening while also extending its depth to form the opening 100 in the substrate 18. Because the process is used to form angled sidewalls with respect to wafers 12, 14, and 16, a plurality of isotropic etches will be used to incrementally increase the width of openings 28 and 29 while the depth of the opening extends into substrate 18. The isotropic etch is terminated after the width of the opening 100 is greater than the width of the openings 28 and 29 in the dielectrics 23 and 26. Thereafter, the carbon-based polymer 101 is applied to a portion of the substrate 18 that is exposed in the opening 100.

Figure 17 shows a subsequent stage of the stage illustrated in the description of Figure 16. An anisotropic etch is used to remove portions of the polymer 101 on the bottom of the opening 100 while leaving portions of the polymer 101 on the sidewalls of the opening 100.

Figure 18 shows a subsequent stage of the phase illustrated in the description of Figure 17. An isotropic etching process is used to etch the surface of the substrate 18 that is exposed within the opening 100, as well as any exposed pads 24, similar to one of the descriptions of FIG. The isotropic etch again laterally extends the width of the split openings 28 and 29 while also extending its depth to form the opening 104 in the substrate 18. After the width of the opening 104 is greater than the width of the opening 100, an isotropic etch is typically terminated to widen the width of the opening as the depth increases. Portions of the polymer 101 that are left on the sidewalls of the opening 100 protect the sidewalls of the opening 100 to prevent etching of the opening 104 from affecting the width of the opening 100. During etching of the opening 104, substantially all of the polymer 101 is removed from the sidewalls of the opening 100.

Thereafter, a carbon-based polymer 105 similar to polymer 101 is applied to a portion of substrate 18 that is exposed in opening 104. During the formation of the polymer 105, the operation typically again forms the polymer 101 on the sidewalls of the opening 100.

Figure 19 shows another subsequent stage of the phase illustrated in the description of Figure 18. Another anisotropic etch is used to remove portions of the polymer 105 on the bottom of the opening 104 while leaving a portion of the polymer 105 on the sidewalls of the opening 104. This process step is similar to the steps explained in the description of FIG.

FIG. 20 shows a repeatable etch sequence until the dividing lines 13 and 15 completely penetrate the substrate 18. The anisotropic etch can be repeated to form openings, such as openings 108 and 112, to form a polymer on the sidewalls of the opening, and to remove polymer from the bottom of the opening while leaving a portion of the polymer on the sidewalls (such as polymers 109 and 113) The sequence of operations is until openings 28 and 29 extend through substrate 18 to form dividing lines 13 and 15 that extend completely through substrate 18. After the final isotropic etch, such as etching to form the opening 112, the polymer is typically not precipitated because the substrate 18 is generally not required to be protected in subsequent operations. While the polymers 101, 105, and 109 are shown on the sidewalls of their respective openings 100, 104, and 108, it will be appreciated by those skilled in the art, after completing all of the operations, to form the opening 112. The final isotropic etching step substantially removes these polymers from the sidewalls of their respective openings. Therefore, these polymers are shown for the purpose of clarity of explanation.

As can be seen in Figure 20, the sidewalls of wafers 12, 14, and 16 are sloped inwardly from top to bottom such that the wafer width at the bottom of each wafer is less than the wafer width at the top of the wafer. Thus, the outer perimeter of the wafer at the top of the substrate 18 extends beyond the outer perimeter of the wafer at the top of the substrate 18 by a distance 116 so that the top surface of the wafer 13 overhangs the bottom surface 17 beyond the distance 116. In one embodiment, the angled sidewalls help minimize damage during wafer selection and placement operations. For such an embodiment, it is believed that the distance 116 should be between five and ten percent (5-10%) of the thickness of the wafers 12, 14, and 16. In an exemplary embodiment, the distance 116 is approximately one to twenty (1-20) microns, such that the bottom width of the wafer 12 at the bottom of the substrate 18 can be approximately two to forty less than the top width of the wafer 12 at the surface 11. (2-40) microns. In another embodiment, it is believed that the sidewalls should form an angle 118 of approximately fifteen to forty degrees (15° - 40°) at the side walls and perpendiculars, such as a line perpendicular to the top surface of the substrate 18. between. Thus, the width of the opening 29 should be etched each time an amount sufficient to form the angle 118. In general, the top of the dividing line 15-16 is about two to forty (2-40) microns narrower than the bottom of the dividing line. Those skilled in the art will appreciate that multiple isotropic etching operations form the rough sidewalls of each of the wafers 12, 14, and 16 such that the sidewalls have a jagged perimeter along the sidewalls. However, for the purpose of clarity of illustration, the degree of variation of the above periphery is exaggerated in the illustration of Figures 16-21. These sidewalls are generally considered to be substantially smooth sidewalls.

Figure 21 shows wafers 12, 14, and 16 with sidewalls that are inclined inward during the pick and place operation. As can be seen, the sloped sidewalls of wafers 12, 14, and 16 allow punch 35 to move one of the wafers up, such as wafer 12, without colliding with other wafers, such as wafers 14 and 16. This helps reduce cracking and other damage to the wafers 12, 14, and 16 during the pick and place operation.

Figure 22 shows other wafers without sloping sidewalls and how they might collide with each other during the selection operation. This configuration has the potential to cause damage to the wafer during selection and placement operations, such as damage to the periphery of the wafer.

Figure 23 illustrates a stage in an embodiment example of another alternative method of splitting semiconductor wafers 12, 14, and 16 and forming angled or sloped sidewalls as illustrated in the description of Figures 16-22. Those skilled in the art will appreciate that other segmentation techniques, such as those illustrated in the description of Figures 1-15, can be used to split the wafer from the wafer and form angled and oblique on the wafer. Side wall. For example, the anisotropic etch illustrated in the description of FIG. 14 can be used to form openings 28 and 29 into substrate 18 that are a first distance 120 from the top surface of substrate 18. Thus, the sidewall is substantially straight within the first distance of the sidewall. The segmentation method illustrated in the description of Figures 16-22 can then be used to complete the segmentation. The depth of the first distance 120 depends on the thickness of the wafer, but will typically be as much as about fifty percent (50%) of the thickness of the wafer. Thereafter, etching to form openings (such as openings 108 and 112), forming a polymer on the sidewalls of the opening, and removing the polymer from the bottom of the opening while leaving a portion of the polymer (such as polymers 109 and 113) on the sidewalls, This anisotropic etch sequence is repeated until openings 28 and 29 extend through substrate 18 to form dividing lines 13 and 15 that extend completely through substrate 18.

An example of another alternative method of splitting semiconductor wafers 12, 14, and 16 includes using an anisotropic etch, such as an anisotropic etch as illustrated in the description of FIG. 14, to form an entry substrate 18. The openings 28 and 29 therein are at a first distance 120 from the top surface of the substrate 18. Thus, the sidewall is substantially straight within the first distance of the sidewall. Subsequently, an isotropic etch as illustrated in the description of FIGS. 16-22 can be used to extend the depth of the dividing lines 13 and 15 to a second distance that is greater than the distance 120 but not yet completely through the substrate 18. While extending the depth, isotropic etching also increases the width of lines 13 and 15. The width is extended to be wider than the width of the openings 28 and 29 on the dielectric 26. The final portion of the method may use an anisotropic etch to provide a substantially straight sidewall near the bottom of the dividing line. Then the dividing line here will be wider than the middle. This or other combination of methods can then be used to provide improved functionality, such as wafer dies that are locked to the sidewalls or perimeter slopes of wafers 12, 14, and 16, such that the bottom of the wafer is wider than the top of the wafer, or wafer The middle is wider than the top of the wafer.

24-28 illustrate cross-sectional views of wafer 10 at various stages in another alternative embodiment example of splitting a semiconductor wafer from wafer 10. The cross-sectional views of wafer 10 shown in Figures 24-28 are taken along line 24-24 of Figure 1. Example embodiments of the alternative methods illustrated in FIGS. 24-28 also include an alternative method of reducing the thickness of wafer 10 or thinning wafer 10. Wafer 10 includes semiconductor wafers 12, 14, and 16, as well as dividing lines 13 and 15, which are described in the description of Figures 1-4, 8-20, and 23. Although not shown in Figures 24-28 for purposes of clarity of the drawings and the description, wafer 10 can also include wafers 42 along dividing lines 43 and 45 as illustrated in the description of Figures 5-7, 44, and 46, and split openings 47-48. Since the cross-sectional portion of the wafer 10 shown in FIG. 24 is larger than the portion of the wafer 10 shown in FIGS. 2-23, FIG. 24 is shown along the additional dividing line to form on the top surface of the wafer 10. Additional wafers, including the dividing lines 11, 17, 137, and 138, similar to those in the dividing lines 13 and 15 or 43 and 45 illustrated in the description of any of Figures 2-23 anyone. In addition, FIG. 24 illustrates a substrate 18 having a thickness 66 between the top surface of the substrate 18 and the bottom or back surface of the substrate 18. Subsequent to the formation of semiconductor wafers on the top surface of substrate 18, such as wafers 12, 14, 16, 144, and 145, wafer 10 is thinned to reduce the thickness 66 of substrate 18. An example of one embodiment of reducing thickness 66 is shown in Figures 25-28.

With respect to FIG. 25, after a semiconductor wafer is formed on the top surface of substrate 18, wafer 10 can be inverted and attached to support strip or support device 34 such that the top surface of substrate 18 faces device 34. Device 34 can be any known device that can be used to provide support for wafers during thinning operations, such as from the operation of backgrinding tapes or other devices.

FIG. 26 illustrates wafer 10 on a subsequent stage in an example implementation of a method of singulating wafers from wafer 10. Typically, the entire bottom surface of wafer 10 is thinned to reduce the thickness of wafer 10, i.e., from thickness 66 to thickness 67, which is less than thickness 66. A variety of different well known methods can be utilized to reduce the thickness of wafer 10 to a thickness of 67, such as back grinding, chemical mechanical polishing (CMP) or other techniques known to those skilled in the art. In some embodiments, this step can be omitted in the method.

Subsequently, the inner portion 125 of the bottom surface of the wafer 10 is further reduced to a thickness 68 that is less than the thicknesses 66 and 67. The bottom surface portion of the wafer 10 that was removed during the formation of the inner portion 125 is shown by dashed lines. The thickness of the inner portion 125 is typically reduced by subjecting the inner portion 125 to a grinding operation, or by other known techniques to reduce the thickness. Reducing the thickness of portion 125 will leave outer rim 127 juxtaposed with the outer perimeter of wafer 10. Therefore, the outer rim 127 typically maintains a thickness 67. The thickness of the outer rim 127 is then sufficient to provide support for processing or transporting the remaining wafer 10. Tools and methods for reducing the thickness of the inner portion 125 are well known to those skilled in the art. An example of such a tool and method is included in U.S. Patent No. 2006/024,4096, the disclosure of which is incorporated herein by reference.

FIG. 27 shows another subsequent step of dividing the wafer from the wafer 10. The support device 34 can be removed from the wafer 10 and the protective layer 135 applied to the bottom surface of the wafer 10, particularly to the bottom surface of the wafer 10 in the inner portion 125. Device 34 can have an ultraviolet release mechanism, such as when exposed to ultraviolet light, or other well known release mechanisms. Because the method used to form layer 135 typically includes a high temperature that can damage device 34, device 34 is removed. For embodiments that do not include such high temperatures, or for support devices that are resistant to such temperatures, device 34 may be retained. Nonetheless, device 34 typically must be removed prior to subsequent operations. A portion of layer 135 can also be applied to the bottom surface of outer rim 127 as shown by protective layer portion 133. However, in some embodiments, the outer rim 127 can be covered to prevent the formation of the portion 133. For example, a light mask may be applied during operation to form layer 135 to cover rim 127, or a shadow mask may be used to prevent formation of portion 133.

Figure 28 shows the wafer 10 on another subsequent manufacturing stage. After layer 135 is formed, wafer 10 is typically flipped again to an upright state. The carrier tape 30 is applied to the bottom surface of the wafer 10. In some embodiments, the carrier tape 30 is attached to the film frame 62 to provide support for the carrier tape 30. Such film frames and carrier tapes are well known to those skilled in the art. The carrier tape 30 is applied as a carrier tool for processing and supporting the wafer 10. For embodiments that use different carriers to process wafer 10, different carriers can be used and carrier tape 30 can be omitted. The carrier tape 30 is applied as a carrier tool for processing and supporting the wafer 10. For embodiments that use different carriers to process wafer 10, different carriers can be used and carrier tape 30 can be omitted. Typically, a vacuum chuck is used to hold the wafer 10 and the carrier tape 30 conforms to the bottom surface of the wafer 10 such that the carrier tape 30 provides some support for the wafer 10. Thereafter, split openings 28, 29, 140, and 141 are formed which terminate from the top surface of the wafer 10 into the substrate 18 and reach the layer 135, the method of which is used as previously described in the description of Figures 2-23. Openings 28 and 29 or openings 47 and 48, etc., which terminate in the metal layer 27, are formed in a similar manner. Those skilled in the art will appreciate that other split openings are typically formed simultaneously with openings 28 and 29 to divide other wafers of wafer 10. The layer 135 is formed of a material that is not etched by a dry etching method that is used to form the split openings 28, 29, 140, and 141. In one embodiment, the protective layer 135 is a metal or metal compound, and the selected dry etch process is a process that etches germanium at a much faster rate than etching the metal. This process has been explained before. In other embodiments, the protective layer 135 can be a A previously described aluminum nitride, or a previously described bismuth-metal compound. Layer 135 can also be the same material as the metal layer 27 previously described. Further, the split openings 140 and 141 may also be formed along with the split openings 28 and 29. The split openings 140 and 141 are formed through the substrate 18 in a manner similar to the formation of the openings 28 and 29 (or the openings 47 and 48) to form the dividing lines 137 and 138. The dividing lines 137 and 138 are formed to separate the outer rim 127 from the remaining wafer 10. Thus, the formed dividing lines 137 and 138 are typically overlying the inner portion 125 and are located between the outer rim 127 and any semiconductor wafer that is located adjacent the rim 127, such as semiconductor wafers 144 and 145. For example, the dividing lines 137 and 138 may be one (1) continuous dividing line that extends around the outer periphery of the inner portion 125, for example, just within the portion of the crystal 10 that forms the inner edge of the outer rim 127. .

Those skilled in the art will appreciate that using a wafer saw or other type of cutting tool to sing a wafer from a wafer having such an inner portion 125 and rim 127 will subject the inner portion 125 to a large Mechanical stresses and the possibility of breaking the wafer 10 within the inner portion 125. Additionally, removing the rim 127 with a laser scribe may result in recrystallization of the wafer adjacent the rim 127. Using the dry etch method described herein to remove the rim 127 will minimize mechanical stress on the inner portion 125 and reduce damage to the wafer while removing the rim 127 or while dicing the wafer from the wafer 10. The possibility.

In some cases it may be desirable to remove the rim 127 from the wafer 10 without dividing the wafer formed on the wafer 10. For such an alternative implementation In the manner, the dividing lines 137 and 138 may be formed to remove the rim 127 from the wafer 10 without forming dividing lines for dividing the wafer of the wafer 10, such as the dividing lines 11, 13, 15, and 17. After the rim 127 is removed, another strip similar to the carrier tape 30 can be applied to the bottom surface of the portion 125, such as directly to the layer 135, and the wafer can then be singulated as described herein. In other embodiments, the carrier tape 30 can be held to support the remaining wafer 10. Removing the rim 127 prior to singulation of the wafer allows for a quick and clean method that reduces the potential and mechanical stress of the scratched wafer, thereby improving yield and yield.

29-31 illustrate various stages in another alternative embodiment of a method of dividing a wafer from wafer 10. FIG. 29 shows the wafer 10 at a stage just after the stage illustrated in the description of FIG. The wafer 10 is removed from the support device 34, and a protective layer 135 is formed on the bottom surface of the inner portion 125.

Referring to Figure 30, a carrier tape 63 can be applied to the wafer 10 to provide support for the wafer 10. A carrier tape 63 is applied to the top of the wafer 10 such that the top surface of the substrate 18 faces the strip 63. Typically, the strap 63 is similar to the carrier strap 30 previously described. In some embodiments, the strap 63 is attached to the film frame 64, which is similar to the frame 62. The tape 63 is applied as a carrier tool for processing and supporting the wafer 10. For embodiments that use different carriers to process wafer 10, different carriers can be used and strip 63 can be omitted. As shown by the dashed line with respect to portion 133, any portion of protective layer 135 formed on the bottom surface of outer rim 127 is removed. For example, the bottom surface of the outer rim 127 can be subjected to a grinding process for a time sufficient to remove the protective layer portion 133 as shown by the dashed line, or can cover the layer 135 and can etch the portion 133 from the rim 127 Come down. As previously explained, in some embodiments, the protective layer portion 133 is not formed on the outer rim 127.

The thickness of the outer rim 127 can be reduced to a thickness 69 using a dry etch process. Using a dry etch process to reduce the thickness of the outer rim 127, the process can be any of the dry etch processes described herein, such as those used to form split openings, such as split openings 28 and 29. The thickness 69 is less than the previous thickness 67 of the outer rim 127. The value of thickness 69 is typically chosen such that the bottom surface of outer rim 127 is near thickness 68 such that carrier tape 30 (see FIG. 31) provides better support for wafer 10. In a preferred embodiment, the thickness 69 forms the bottom surface of the rim 127 that is substantially parallel to the outer side surface of the protective layer 135. The removal portion 133 allows dry etching to reduce the thickness of the rim 127. The portion 133 can be removed at different stages of the method as long as the portion 133 is removed prior to reducing the thickness of the rim 127. In some embodiments, the thickness 68 is no greater than about fifty (50) microns and can be twenty five (25) microns or less. Those skilled in the art will appreciate that at this thickness, wafer 10 may become brittle. Using a dry etch process to reduce the thickness of the rim 127 can minimize mechanical stress on the wafer 10 as compared to other thickness reduction methods, such as back grinding or CMP.

Figure 31 shows wafer 10 on a subsequent stage. After reducing the thickness of the outer rim 127, the wafer 10 is typically flipped over and placed on the carrier tape 30 previously described. Split openings 28 and 29 are formed which terminate from the top surface of the substrate 18, through the substrate 18 and to the protective layer 135. In addition, split openings 140 and 141 are also formed, which are typically formed with openings 28 and 29 to separate outer rim 127 from the semiconductor wafer of wafer 10. Those skilled in the art will appreciate that the split openings are typically formed simultaneously with openings 28 and 29 to divide other wafers of wafer 10. Because of the small thickness of the wafer 10, the use of dry etching to divide the wafer will minimize mechanical stress on the wafer 10 and reduce the likelihood of damage to the wafer and other damage.

32-33 illustrate various stages in an example implementation of another alternative method of singulating wafers from wafer 10. FIG. 32 shows the wafer 10 at a stage just after the stage depicted in FIG. As previously explained, the device 34 can generally be removed from the wafer 10 and a protective layer 135 formed on the bottom surface of the inner portion 125. The protective layer 135 can be patterned to have openings through the protective layer 135 that are substantially aligned with the dividing lines to form the wafer 10, such as wafers at the dividing lines 11, 13, 15, 17, 137, and 138 Part of 10. Those skilled in the art will appreciate that a variety of different back alignment techniques can be utilized to ensure that the openings formed in layer 135 are positioned to align to form a dividing line, such as dividing lines 13, 15, 137, And a portion of the substrate 18 at 138.

Referring to FIG. 33, a protective layer 135 can be used as a mask to protect the substrate 18 while a dry etching process is utilized to form the split openings 28, 29, 140, and 141 that extend from the bottom surface of the substrate 18, completely through the substrate 18 and from The top surface of the substrate 18 is pierced. Any of the dry etching methods illustrated for forming the split openings 28 and 29 or 47 and 48 can also be used to form the split openings 140 and 141, as well as any other split openings through the substrate 18. The process also etches the outer rim 127 while forming the split opening, thereby reducing the thickness of the outer rim 127 to a thickness 69. As previously explained in the description of FIG. 30, any portion of the protective layer 133 is removed prior to reducing the thickness of the rim 127 and etching the split opening. Along with forming the thickness of the split opening reducing portion 127, the processing steps are reduced, thereby reducing manufacturing costs, and reducing the thickness also minimizes mechanical stress on the wafer 10, thereby improving profitability and reducing cost. The reduced thickness of the rim 127 makes it easier to process the wafer 10 and easier to remove after wafer singulation. In other embodiments, the rim 127 can be covered and the rim 127 is not etched while forming the openings 28, 29, 140, and 141. After forming the split opening, another carrier tape (not shown), such as carrier tape 30, may be applied to the bottom surface of wafer 10, such as to the bottom surface of inner portion 125, and wafer 10 may be flipped, or inner portion 125 . Thereafter, the semiconductor wafer can be removed by the selection and placement techniques or other techniques previously described.

One skilled in the art will appreciate that one example of a method of forming a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers, such as wafers 12, 14, or 16, wherein the semiconductor wafer is formed on a top surface of the semiconductor substrate and separated from each other by a portion of the semiconductor wafer at which the dividing lines are to be formed, such as lines 13 and 15; and the semiconductor wafer is flipped Reducing the thickness of the inner portion of the bottom surface of the semiconductor wafer, such as portion 125, to a second thickness that is less than the first thickness and leaving the outer rim of the semiconductor wafer having the first thickness, such as rim 127, where the outer side The rim is juxtaposed with the outer periphery of the semiconductor wafer, and wherein the inner portion is under the plurality of semiconductor wafers; a protective layer is formed on the inner portion of the bottom surface of the semiconductor wafer, wherein the protective layer is a metal or a metal compound or metal - one of the bismuth compounds; and using dry etching to reduce the first thickness of the outer rim to the first Thickness, the third thickness less than the first thickness, wherein the inner portion is not protected by the protective layer is dry etched, such that the second thickness is kept substantially constant.

Those skilled in the art will appreciate that the method can also include patterning the protective layer to expose portions of the semiconductor substrate where the dividing lines are to be formed; and etching the dividing lines using dry etching from the bottom surface of the semiconductor substrate Initially, the semiconductor substrate is passed through the top surface of the semiconductor substrate.

An example of another method of forming a semiconductor wafer includes providing a semiconductor wafer having a semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers, such as wafer 12/14/16, The semiconductor wafer is formed on the semiconductor substrate and separated from each other by portions of the semiconductor wafer at which the dividing lines are to be formed, such as portions 13/15; the thickness of the inner portion of the bottom surface of the semiconductor wafer, such as portion 125, is reduced to a second a thickness that is less than the first thickness and leaves an outer rim of the semiconductor wafer having a first thickness, such as rim 127, wherein the outer rim is juxtaposed with the perimeter of the semiconductor wafer, and wherein the inner portion is in a plurality of a lower surface of the semiconductor wafer; a protective layer formed on an inner portion of the bottom surface of the wafer, wherein the protective layer is one of a metal or a metal compound or a metal-germanium compound; and forming a split opening at the portion where the dividing line is to be formed using dry etching Forming a split opening through the semiconductor substrate, wherein the outer rim is adjacent to any of the outer rims At least one semiconductor wafer is formed between the divided opening.

Skilled artisans will also appreciate that the method can also include forming a split opening using a dry etch that extends through the semiconductor substrate from a top surface of the semiconductor wafer.

The method may further include patterning the protective layer to expose a portion of the bottom surface of the semiconductor wafer at which the dividing line is to be formed; and the step of forming the divided opening using dry etching may include using the protective layer as a mask while etching the segment using dry etching An opening starting from a bottom surface of the semiconductor wafer, extending through the semiconductor substrate to a top surface of the semiconductor substrate, and etching the outer rim using dry etching, and reducing the first thickness of the outer rim to a third thickness, The three thicknesses are less than the first thickness.

In view of the above, it is apparent that a novel device and method are disclosed. Among other things, it involves the use of a dry etch process to etch a split opening that extends completely through the semiconductor wafer. This dry etching process is generally referred to as plasma etching or reactive ion etching (RIE). Etching the opening from one side helps to ensure that the split opening has very straight sidewalls, thereby providing a uniform dividing line along each side of each semiconductor wafer. Etching the split openings that extend completely through the semiconductor wafer facilitates the formation of narrow dividing lines, thereby allowing more space on a given size of wafer for forming a semiconductor wafer. All dividing lines are generally formed at the same time. The etching process is faster than the dicing or wafer sawing process, thereby increasing throughput in the manufacturing field.

The formation of a dividing line through the trench fill material promotes the formation of a narrow dividing line, thereby increasing wafer utilization and reducing cost. The use of a split mask helps to protect the inner portion of the wafer while forming a dividing line through the substrate. Forming the angled sidewalls reduces damage during the assembly operation, thereby reducing cost. Angled sidewalls are typically formed on all wafers simultaneously.

Although the subject matter of the present invention has been described in terms of specific preferred embodiments, it will be apparent to those skilled in the For example, layers 20 and/or 21 may be omitted from substrate 18. Alternatively, the split opening may be formed before or after the contact opening of the cover pad 24 is formed. Moreover, the split opening can be formed prior to thinning the wafer 10, for example, the split opening can be formed to partially pass through the substrate 18, and a thinning process can be used to expose the bottom of the split opening.

10. . . Semiconductor wafer

11. . . split line

12. . . Semiconductor wafer

13. . . split line

14. . . Semiconductor wafer

15. . . split line

16. . . Semiconductor wafer

17. . . split line

18. . . Base

19. . . Block base

20. . . Epitaxial layer

twenty one. . . Epitaxial layer

twenty three. . . Dielectric

twenty four. . . Contact pad

26. . . Dielectric

27. . . Metal layer

28. . . Split opening

29. . . Split opening

30. . . Carrier tape

32. . . Mask

35. . . Select and place the device/punch

42. . . Semiconductor wafer

43. . . split line

44. . . Semiconductor wafer

45. . . split line

46. . . Semiconductor wafer

47. . . Split opening

48. . . Split opening

50. . . Isolation trench

51. . . Dielectric

52. . . Polycrystalline germanium

54. . . Isolation trench

55. . . Dielectric

56. . . Polycrystalline germanium

58. . . Isolation trench

59. . . Dielectric

60. . . Polycrystalline germanium

62. . . frame

63. . . Carrier tape

64. . . Film frame

66. . . thickness

67. . . thickness

68. . . thickness

71. . . Semiconductor wafer

72. . . Semiconductor wafer

73. . . Semiconductor wafer

76. . . split line

77. . . split line

78. . . Trench

79. . . Trench

80. . . Dielectric spacer

81. . . Filler

82. . . Opening

83. . . Opening

84. . . dotted line

85. . . Mask

86. . . dotted line

87. . . Mask

91. . . AlN layer

92. . . dotted line

93. . . AlN

100. . . Opening

101. . . Carbon-based polymer

104. . . Opening

105. . . Carbon-based polymer

108. . . Opening

109. . . polymer

112. . . Opening

113. . . polymer

116. . . distance

118. . . angle

120. . . First distance

125. . . Internal part

127. . . Outer rim

133. . . Protective layer

135. . . The protective layer

137. . . split line

138. . . split line

140. . . Split opening

141. . . Split opening

144. . . Semiconductor wafer

145. . . Semiconductor wafer

1 shows a simplified plan view of an embodiment of a semiconductor wafer in accordance with the present invention;

2 is an enlarged cross-sectional view showing an embodiment of the semiconductor wafer of FIG. 1 at a stage in the process of dicing a wafer from a wafer, in accordance with the present invention;

Figure 3 illustrates a subsequent state in the process of dividing a wafer from the wafer of Figure 1 in accordance with the present invention;

4 illustrates another subsequent stage in the process of dicing a wafer from the wafer of FIG. 1 in accordance with the present invention;

Figure 5 illustrates an enlarged cross-sectional portion of a semiconductor wafer formed on the wafer of Figures 1-4 and being an alternative embodiment of the wafer illustrated in the description of Figures 1-4;

Figure 6 shows a subsequent stage in the process of dividing the wafer of Figure 5 in accordance with the present invention;

Figure 7 illustrates another subsequent stage in the process of dividing the wafer of Figure 6 in accordance with the present invention;

8 through 10 illustrate steps in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

11 through 14 illustrate steps in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

15 illustrates an example embodiment of another method of dicing a wafer from the semiconductor wafer of FIG. 14 in accordance with the present invention;

16 through 20 illustrate steps in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

21 illustrates another stage in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

Figure 22 shows another segmentation method;

23 illustrates a stage in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention, which is an alternative embodiment of the method of FIGS. 16-20 ;

24 through 28 are cross-sectional views showing different stages in an exemplary embodiment of another method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

29 through 31 are cross-sectional views showing different stages in another alternative embodiment of an example of a method of dividing a wafer from the semiconductor wafer of FIG. 1 in accordance with the present invention;

32-33 are cross-sectional views showing different stages of an exemplary embodiment of another alternative method of singulating wafers from the semiconductor wafer of FIG. 1 in accordance with the present invention.

10. . . Semiconductor wafer

11. . . split line

12. . . Semiconductor wafer

13. . . split line

14. . . Semiconductor wafer

15. . . split line

16. . . Semiconductor wafer

17. . . split line

18. . . Base

20. . . Epitaxial layer

twenty one. . . Epitaxial layer

twenty three. . . Dielectric

28. . . Split opening

29. . . Split opening

30. . . Carrier tape

62. . . frame

125. . . Internal part

127. . . Outer rim

133. . . Protective layer

135. . . The protective layer

137. . . split line

138. . . split line

140. . . Split opening

141. . . Split opening

144. . . Semiconductor wafer

145. . . Semiconductor wafer

Claims (10)

A method of forming a semiconductor wafer, comprising: providing a semiconductor wafer having a semiconductor substrate, the semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers Forming on the top surface of the semiconductor substrate and separating from each other by portions of the semiconductor wafer at which the dividing lines are to be formed; inverting the semiconductor wafer; reducing a thickness of an inner portion of the bottom surface of the semiconductor wafer a second thickness less than the first thickness, and leaving an outer rim of the semiconductor wafer having the first thickness, wherein the outer rim is juxtaposed with a perimeter of the semiconductor wafer, and wherein the interior Part of being disposed under the plurality of semiconductor wafers; forming a protective layer on the inner portion of the bottom surface of the semiconductor wafer, wherein the protective layer is one of a metal or a metal compound or a metal-germanium compound; And using a dry etch to reduce the first thickness of the outer rim to a third thickness, the third thickness being less than the first thickness, Wherein the protective layer protects the inner portion from dry etching such that the second thickness remains substantially constant. The method of claim 1, wherein the using the dry etch to reduce the first thickness comprises using a dry etch that etches germanium faster than etching the metal. The method of claim 1, wherein flipping the semiconductor wafer comprises attaching a support device to the semiconductor wafer before flipping the semiconductor Top surface. The method of claim 3, further comprising removing the support device prior to forming the protective layer. The method of claim 1, wherein forming the protective layer comprises patterning the protective layer to expose a portion of the semiconductor substrate at which the dividing lines are to be formed; and wherein using the dry etching to reduce the first thickness comprises using the Dry etching etches the dividing lines from the bottom surface of the semiconductor substrate through the semiconductor substrate to the top surface of the semiconductor substrate. The method of claim 1, further comprising removing any protective layer from the bottom surface of the outer rim prior to the step of reducing the first thickness using the dry etch. A method of forming a semiconductor wafer, comprising: providing a semiconductor wafer having a semiconductor substrate, the semiconductor substrate having a first thickness, a top surface, a bottom surface, and a plurality of semiconductor wafers Forming on the top surface of the semiconductor substrate and separating from each other by portions of the semiconductor wafer at which the dividing lines are to be formed; reducing a thickness of an inner portion of the bottom surface of the semiconductor wafer to less than the first thickness a second thickness, and leaving an outer rim of the semiconductor wafer having the first thickness, wherein the outer rim is juxtaposed with a perimeter of the semiconductor wafer, and wherein the inner portion is located in the plurality of semiconductors a lower surface of the wafer; forming a protection on the inner portion of the bottom surface of the semiconductor wafer a layer, wherein the protective layer is one of a metal or a metal compound or a metal-germanium compound; and using a dry etch to form the split openings at the formation of the dividing lines, including forming the semiconductor substrate through the semiconductor substrate The opening is divided, wherein at least one split opening is formed between the outer rim and any semiconductor wafer adjacent the outer rim. The method of claim 7, wherein forming the protective layer comprises patterning the protective layer to expose a portion of the bottom surface of the semiconductor wafer at which the dividing lines are to be formed; and wherein the dry etching is used to form the dividing The step of opening includes using the protective layer as a mask while using the dry etching to etch the divided openings from the bottom surface of the semiconductor wafer through the semiconductor substrate to the top surface of the semiconductor substrate, and using the dry pattern Etching to etch the outer rim and reduce the first thickness of the outer rim to a third thickness, the third thickness being less than the first thickness. The method of claim 8, further comprising removing any portion of the protective layer on the bottom surface of the outer rim prior to the step of using the dry etch to form the split openings. The method of claim 8, further comprising covering the bottom surface of the outer rim to prevent any formation of the protective layer on the bottom surface of the outer rim.