JP3427751B2 - Thin processing method of semiconductor chip and etching apparatus for thin processing - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for thinning a semiconductor chip and an etching apparatus for thinning.

[0002]

14 to 1 show an example of a thin processing method for obtaining a thin semiconductor chip, that is, a method of thinning a silicon wafer which is a flat plate material by etching.
This will be described using 9. First, as shown in FIG. 14, a silicon wafer 50 is manufactured by a semiconductor manufacturing apparatus (not shown).
After forming a semiconductor element (or a semiconductor circuit in which the elements are electrically connected) 51 on the surface of, as shown in FIG.
200μ of silicon wafer 50 by grinding process
Roughly cutting to about m, and further, as shown in FIG. 16, while the silicon wafer 50 is being rotated, a droplet 52 of an etching solution is jetted from a nozzle to thin the entire back surface of the silicon wafer 50 by etching (so-called spin etching). Process). Subsequently, as shown in FIG. 17, an adhesive tape 53 is attached to the silicon wafer 50, dicing is performed using a cutter 54 as shown in FIG. 18, and each chip 55 is taken out as shown in FIG.

However, in this method, the silicon wafer 5
When the thickness of 0 is 100 μm or less, for example, there is a problem that the wafer is cracked during etching or during wafer transportation after etching. In addition, since the entire surface of the silicon wafer 50 is thin during transporting and setting in a step of attaching the silicon wafer 50 thinned by etching to the adhesive tape 53 for dicing or a step of dividing by dicing, during handling. There is a big problem that cracks occur in the steel, which causes a remarkable decrease in productivity.

Therefore, it is possible to use the method disclosed in Japanese Patent Laid-Open No. 5-198671. The technique described in the publication is to remove a portion having a constant thickness from the back surface of the wafer to the front surface except for an area within a certain distance from the outer circumference of the wafer, and attach an adhesive tape to the back surface of the wafer including the removed area. The dicing groove is formed to have a depth of at least half the thickness left in the removal region. As a result, the mechanical strength of the wafer is maintained in the area within a certain distance from the outer circumference of the wafer.

[0005]

However, since the dicing is performed in a state where the central portion of the wafer is thinned by etching, the thickness of the manufactured chips is small (30 to 10).
In the case of 0 μm), since the thinned portion is diced in a state of being lifted, it is not possible to satisfactorily perform dicing and the depth of cut is not constant.

Further, in order to make the depth of cut constant, a support base for supporting the thinned portion is required. Therefore, an object of the present invention is to provide a thin-wall processing method for a semiconductor chip and an etching apparatus for thin-wall processing capable of making a dicing cut at a constant depth without using a special wafer support for dicing. is there.

[0007]

According to the invention described in claim 1, since the thickness of the wafer is reduced by performing dicing before etching, the thickness of the wafer during dicing is uniform and the depth of the cut is large. Can be constant. That is, the dicing is performed before the thick portion is formed on the outer peripheral portion of the wafer, and the depth of the cut can be made constant. Further, a jig for maintaining a constant depth of cut (a support base for supporting the thinned portion in the conventional method) is not required.

In this way, the dicing notch can be made to have a constant depth without using a special wafer support for dicing. Also etch
The thickness of the chip area on the semiconductor wafer by
When it is 5 to 100 μm, it is preferable in practical use.
Here, when the etching amount in the second step is set to an amount that does not reach the dicing notch as described in claim 2, it is possible to prevent the chips from falling apart.

According to the third aspect of the invention, since the adhesive tape is attached to the element forming surface of the semiconductor wafer, the chips are scattered even if the etching reaches the dicing notch during etching. Can be prevented.

Further, according to the invention described in claim 4,
Since the adhesive tape is attached to the element formation surface of the semiconductor wafer in the chip connected by face down bonding, after braking after etching, just put the chip on the desired mounting location as it is Will be good. In other words, it suffices to dispose the etched wafer on the adhesive tape, separate each chip by breaking, take out the chip in this state, and place it on the mounting location as it is.

Furthermore, as described in claim 5, before or after making a dicing notch having a predetermined depth from the element forming surface of the semiconductor wafer, the back surface of the semiconductor wafer on which the elements are not formed is ground. When the wafer is processed to have a predetermined thickness, the wafer surface can be thinned to a uniform thickness, which facilitates thinning by etching.

Further, as described in claim 6, the etch
Each wafer can be
If it is separated into chips, it is preferable for practical use.
Become.

Further, as described in claim 7, the wafer
When etching and thinning to a specified depth leaving the outer periphery
In addition, the thickness is measured and etching is performed when the desired thickness is reached.
To end. Then, etch with time management
Thickness during etching compared to when detecting the end point of etching
The etching end point can be detected by measurement, and the thickness
The accuracy can be increased. Further, as described in claim 8, when the thickness of the chip area is 5 to 100 μm,
It is practically preferable.

Further, as an etching apparatus for thin wall processing,
A configuration as described in claim 9 may be adopted. That is,
With the semiconductor wafer placed on the base member, the cylindrical frame member is arranged on the base member with one opening facing down, and the fixing member pulls the base member and the frame member together and fixes them. . As a result, the lower surface of the frame and the outer peripheral portion of the semiconductor wafer are liquid-tightly sealed by the seal packing.
Then, the etching liquid injected into the frame body etches the semiconductor wafer to a predetermined depth to the back surface of the semiconductor wafer on which no element is formed, leaving the outer peripheral portion of the wafer, and becomes thin.

As described above, when the element forming surface of the semiconductor wafer is protected by wax or the like when etching the semiconductor wafer while leaving the outer peripheral portion of the semiconductor wafer, the wafer is thin, and therefore the etching is performed. The wafer is easily cracked when the protective film such as wax is removed later. However, when the thin film etching apparatus of the present invention is used, the outer peripheral portion of the semiconductor wafer is masked by the seal packing and etched, and after etching, Since it is only necessary to remove the seal packing, it is possible to prevent the wafer from cracking.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

1 to 6 show a thin-wall processing step for a semiconductor chip. As shown in FIG. 6, the chip 15 has a thickness of 5
˜100 μm, and the electrode portion (pad) is wire-bonded to a lead frame or the like.

First, as shown in FIG. 1, a semiconductor element (or a semiconductor circuit in which elements are electrically connected) is formed on one surface of a silicon wafer 1. Hereinafter, a region of the silicon wafer 1 in which elements are formed is indicated by reference numeral 2. The element forming region 2 has a predetermined depth on one surface of the silicon wafer 1 and extends to a portion excluding the outer peripheral portion of the wafer. Here, the surface of the silicon wafer 1 opposite to the element formation surface 1a is referred to as a back surface 1b.

Then, as shown in FIG. 2, the back surface 1b of the silicon wafer 1 is ground with a grindstone 3 to a predetermined thickness. That is, the entire area of the silicon wafer 1 is thinned by rough cutting.

Subsequently, shifting to the dicing step, as shown in FIG. 3, an adhesive tape 4 is attached to the back surface 1b (ground surface) of the silicon wafer 1, and an element of the silicon wafer 1 is formed by using a cutter 5. A notch (groove) 6 having a predetermined depth is formed from the surface 1a side, and so-called half-cutting is performed. The depth of the dicing notch 6 is specifically, for example, about 30 μm.

Further, as shown in FIG. 4, the silicon wafer 1 is set in the etching pot 8 containing the etching liquid 7 so that the surface to be etched of the silicon wafer 1 is held upward and exposed to the etching liquid 7. The outer peripheral portion 10 of the wafer is masked by the seal packing 9. In this state, the back surface 1b of the silicon wafer 1 is attached to the wafer outer peripheral portion 10
Etching is performed up to a predetermined depth leaving the above to form the recess 11. The etching amount at this time is an amount that does not reach the notch 6. As a result, the bottom surface of the recess 11 is thinned. That is, since the outer peripheral portion 10 of the silicon wafer 1 which is a flat plate material is masked by the seal packing 9,
Only the part corresponding to the product semiconductor chip area is thin.

Here, referring to the etching amount, as shown in FIG. 4, the depth of the notch 6 is, for example, 30.
If it is μm, etching is performed until the thickness becomes about 50 μm, and the distance between the bottom surface of the notch 6 and the etching surface is 20 μm
And As another example, the depth of the notch 6 is 30 μm
Then, etching is performed until the thickness reaches about 70 μm, and the distance between the bottom surface of the notch 6 and the etching surface is set to 40 μm.

After that, by leaving the outer peripheral portion 10 of the wafer thicker than the etched portion to have strength, cracking and bending of the wafer can be prevented. More specifically, the strength required for handling the wafer 1 can be ensured even after thin-wall processing, and the wafer 1 can be conveyed in a state of being stretched horizontally and can be prevented from bending.

Thereafter, as shown in FIG. 5, an adhesive tape 12 is attached to the back surface 1b of the silicon wafer 1, and further,
The silicon wafer 1 is placed on the wafer mounting table 13 with the element forming surface 1a facing downward, and bending stress is applied to the wafer 1 from above the adhesive tape 12 by using the break roller 14 so that each chip is cut along the dicing notch 6. Destroy and separate. As described above, after the thin-wall etching process is performed, the silicon wafer 1 is not cut, and each chip can be separated only by giving a light impact by braking.

Thereafter, as shown in FIG. 6, the silicon wafer 1 is turned upside down and the adhesive tape 12 to the chips 15 are turned upside down.
Is taken out, and the chip 15 is placed as it is at a desired mount location. In this way, the silicon wafer 1 after etching is arranged on the adhesive tape 12, and in the state where the element formation region 2 is on the top, it is separated into each chip 15 by braking, and in this state the chip 15 is taken out and kept as it is. It only needs to be placed at the location where wire bonding is performed.

It should be noted that Japanese Patent No. 2737859 describes that a wafer and a fixing jig are bonded to a base film and handled, but in this method, a tensile stress can be generated in the wafer. Instead, the wafer becomes thin and cracks when an external force (compression or bending) is applied.
On the other hand, in the present embodiment, the outer peripheral portion 10 of the wafer 1 is left thick to reduce the wafer thickness, and the thin wafer portion can be pulled by the outer peripheral thick portion (rib) 10. Even when an external force is applied, it acts as a tensile stress and can prevent cracking.

Further, by clamping and handling the thick portion (rib) 10 of the wafer 1, it becomes easy to handle the thin wafer 1. The above-described pot etching (etching for thin wall processing) in FIG. 4 will be described in detail.

FIG. 7 shows a specific construction of the etching pot 8, and FIG. 8 shows the overall construction of a pot etching apparatus as an etching apparatus for thin wall processing. As shown in FIG. 7, the etching pot 8 includes a plate-shaped pot base 20 and a cylindrical pot ring 21.
The silicon wafer 1 can be placed on the upper surface of the pot base 20, and the pot ring 21 is placed thereon with one opening thereof facing down. That is, the silicon wafer 1 is arranged so as to close the lower surface opening of the cylindrical pot ring 21. More specifically, the pot base 20 has a central portion which serves as a base on which the silicon wafer 1 is placed.
Further, a recess 22 is formed in an annular shape on the outer peripheral side of the wafer mounting portion of the pot base 20, and the projection 23 of the pot ring 21 is fitted into the recess 22. Thus, the recess 22
Has the function of alignment. Furthermore, pot base 20
A flat seal surface S1 is formed in an annular shape on the outer peripheral side of the concave portion 22 (around the wafer mounting portion).
A concave portion 24 is formed in a ring shape in 1 and functions as a vacuum pocket.

A wafer-shaped seal packing 9 is fixed to the inner peripheral portion of the bottom surface of the pot ring 21, and the packing 9 is formed into a wafer shape to seal the upper surface of the edge portion of the silicon wafer 1. Wafer type seal packing 9
Thus, it is possible to seal against the etching liquid with which the pot ring 21 is filled. That is, the seal packing 9 is for liquid-tightly sealing the lower surface of the pot ring 21 and the outer peripheral portion of the wafer 1 with the silicon wafer 1 placed on the pot base 20. Further, a flat seal surface S is formed on the outer peripheral portion of the lower surface of the pot ring 21.
2 is formed in an annular shape, and a concave portion 25 is formed in an annular shape in the sealing surface S2 and functions as a vacuum pocket.

An annular X-shaped packing 26 is arranged between the sealing surface S1 of the pot base 20 and the sealing surface S2 of the pot ring 21. Then, the air in the recesses (vacuum pockets) 24, 25 is discharged by a vacuum pump or the like, whereby the X-shaped packing 26 contracts and the pot base 20 and the pot ring 21 are attracted to each other, and the seal packing 9 seals the silicon wafer. The outer peripheral portion of 1 is fixed in a sealed state. Thus, the X-shaped packing 26 functions as a fixing member.

The etching pot 8 thus constructed is set in the etching apparatus as shown in FIG. 8, and the etching liquid 7 is injected into the etching pot 8. At this time, the outer periphery of the silicon wafer 1 is masked (protected) by the etching liquid 7 while being sealed by the wafer type seal packing 9.

Thus, the etching liquid 7 is filled in the etching pot 8, the silicon wafer 1 is supported on the bottom of the pot 8, and the surface to be processed of the upward facing silicon wafer 1 is covered with the etching liquid 7. .

More specifically, the etching pot 8 is mounted on the pot mounting table 27, and the top opening of the etching pot 8 is closed by the cap 28. A stirring blade 29 is hung down on the cap 28 while being sealed by a sealing material 30, and the stirring blade 29 is rotated by driving a motor 31 to stir the etching solution 7. Also, the cap 2
The heater 32 is hung down on the heater 8 while being sealed by the sealing material 33, and the etching liquid 7 is heated by the heater 32. Further, a temperature sensor 34 is hung down on the cap 28 while being sealed by a sealing material 35, and the temperature of the etching liquid 7 is detected by the temperature sensor 34. And
During the etching, the etching solution 7 is sufficiently stirred by the stirring blade 29, and the heater 32 is energized and controlled by the temperature controller 36 so that the temperature of the solution by the temperature sensor 34 becomes a predetermined temperature.

Further, a passage 37 for pure water for cleaning is formed in the cap 28, and pure water can be injected into the etching pot 8 along the inner wall of the pot ring 21. Further, a drain port 38 is formed in the cap 28, and the pot 8
The liquid that overflows inside can be discharged.

Further, in FIG. 8, a thickness sensor 39 is provided on the pot base 20, and as shown in FIG. 9, the thickness (etching amount) at the bottom of the recess 11 in the silicon wafer 1 is measured. Detects the progress of etching,
The etching end time is detected. Here, the thickness sensor 3
As shown in FIG. 9, reference numeral 9 shows an example of a measuring device that measures the thickness from one side by utilizing double reflection on the etched surface of the silicon wafer 1 and the opposite surface.

When a predetermined amount of etching is performed and the thickness of the bottom surface of the recess 11 in the silicon wafer 1 reaches a desired value, the passage 3 shown in FIG.
Pure water for cleaning is injected into the etching pot 8 through 7 to dilute and cool the etching solution, and the overflowed solution is drained through the drain port 38. afterwards,
Recesses (vacuum pockets) 24, 25 by vacuum pump, etc.
The vacuum inside is stopped and the inside of the recesses 24, 25 is brought to atmospheric pressure. Then, the cap 28 and the pot ring 21 (seal packing 7) are removed, and the silicon wafer 1 after etching is sent to the next step.

When the pot etching apparatus shown in FIG. 8 is used as an etching apparatus for thin-wall processing as described above, the pot ring 21 as a frame is placed with the silicon wafer 1 placed on the pot base 20 as a base material.
Is placed on the pot base 20, and the X-shaped packing 26 draws and fixes the pot base 20 and the pot ring 21. Thus, the lower surface of the pot ring 21 and the outer peripheral portion of the wafer 1 are liquid-tightly sealed by the seal packing 9. The wafer can be sealed in a state, and the back surface 1b of the wafer 1 can be etched and thinned to a predetermined depth with the etching liquid 7 injected into the pot ring 21 while leaving the outer peripheral portion of the wafer 1.

FIG. 10 shows a wafer after the back surface 1b of the silicon wafer 1 which is a flat plate material is masked by the seal packing 9 and the back surface 1b of the silicon wafer 1 is subjected to thin-wall etching. Etching is 38 wt
% Aqueous potassium hydroxide solution at 110 ° C. During etching, the temperature of the etching solution 7 is 110 ± 0.1 ° C.
And In FIG. 10, a 5-inch silicon wafer 1
The wafer thickness before etching is 300 μm, the wafer thickness after etching is 30 μm, and the thick width of the wafer outer peripheral portion 10 is 5 mm. At this time, width 5 mm,
The wafer outer peripheral portion 10 having a thickness of 300 μm functions as a rib, that is, a strength member.

As a result of performing the thin-wall processing in this way, it has been confirmed that the thin-film processing can be performed without breaking the wafer up to the wafer thickness of the product semiconductor chip area of 15 μm. More specifically, the depth of the cut 6 is 30 μm, and the wafer thickness after thinning is 50 μm or 70 μm.
As a result of performing thin processing under the condition of m (that is, the distance between the bottom surface of the notch 6 and the etching surface is 20 μm or 40 μm), the notch 6 by dicing before etching
It was confirmed that the thin wall can be favorably processed in the case of forming.

As described above, when the flat plate material is etched to be thin, the outer peripheral portion of the silicon wafer 1 which is the flat plate material is masked and left thicker than the central etching portion without etching, so that the silicon wafer 1 is not cracked. In addition to preventing bending, the wafer 1 can be etched thinner than when the outer peripheral portion of the wafer is not masked.

Before the etching, a notch (groove) 6 is formed from the opposite side of the etching surface, and etching is performed so as not to reach the notch 6, and only a light impact is given after the etching. It can be divided without mechanical cutting.

As described above, the present embodiment has the following features. (A) A dicing notch 6 having a predetermined depth is made in the wafer 1 from the element formation surface 1a on which elements are formed in a silicon wafer 1 as a semiconductor wafer, and a wafer 1 is formed on the back surface 1b of the wafer 1 on which the elements are not formed. The outer peripheral portion of 1 was left to be etched to a predetermined depth so as to be thinned, and each chip was separated along the dicing notch 6 in the wafer 1. That is, since the dicing is performed to reduce the thickness before performing the etching, the wafer 1 when dicing is performed.
Has a uniform thickness, and the depth of the cut 6 can be made constant. Further, a jig for maintaining the depth of the notch 6 constant (a support base for supporting the thinned portion in the conventional method) is also unnecessary. As a result, the dicing notch can be made to have a constant depth without using a special wafer support for dicing. (B) Since the etching is terminated when the thickness sensor 39 reaches a desired thickness in the etching process, the thickness measurement during the etching can be performed more than when the etching end point is detected by time management. Thus, the etching end point can be detected, and the thickness accuracy can be improved. (C) The pot etching apparatus shown in FIG. 8 was used as an etching apparatus for thin wall processing. Therefore, when etching is performed using the etching liquid 7 while leaving the outer peripheral portion of the wafer 1,
When the element formation surface 1a of the wafer 1 is protected by wax or the like, the wafer is thin, and therefore the wafer is easily cracked when the protective film such as wax is removed after etching. On the other hand, when this apparatus is used, etching is performed with the outer peripheral portion of the wafer 1 masked by the seal packing 9, and after the etching, the seal packing 9 is used.
It suffices to remove only the element formation surface 1 with wax.
It is possible to reliably prevent the cracking of the wafer that occurs when protecting a. (D) As shown in FIG. 4, since the etching amount in the step of thinning the silicon wafer 1 by etching is set so as not to reach the dicing notch 6, it is possible to prevent the chips from falling apart.

In the steps of FIGS. 1 to 6, the same effect can be obtained even if the order of the grinding step of FIG. 2 and the dicing step of FIG. 3 is exchanged. That is, before the dicing notch 6 having a predetermined depth is made from the element forming surface 1a of the silicon wafer 1 to the wafer back surface 1b to obtain a predetermined thickness, the dicing notch 6 is made after the dicing notch 6 is made. The wafer back surface 1b may be ground to a predetermined thickness. In either case, by grinding the back surface 1b of the wafer 1 to a predetermined thickness, the inside of the wafer can be thinned to a uniform thickness, which facilitates thinning by etching.

Further, the apparatus for the pot etching process used in this embodiment has a structure capable of measuring the thickness during etching in order to improve the thickness accuracy. You may manage by. (Second Embodiment) Next, the second embodiment will be described with reference to the first embodiment.
The difference from the above embodiment will be mainly described.

11 to 13 show thinning processing steps of a semiconductor chip according to the second embodiment. As shown in FIG. 13, the present chip 41 is a flip-chip element having bumps (projection electrodes) 42 on the lower surface, and is face-down bonded to the conductor of the stem.

1 to 3 are the same as in the first embodiment. That is, as shown in FIG. 1, with respect to the silicon wafer 1 having elements formed on one surface thereof, the back surface 1b of the silicon wafer 1 is roughly ground by a grinding process using a grindstone 3 as shown in FIG. As shown in, silicon wafer 1
The adhesive tape 4 is attached to the back surface 1b of the above, and the notch 6 having a predetermined depth is formed from the element forming surface 1a side of the silicon wafer 1 using the cutter 5.

Then, as shown in FIG. 11, an adhesive tape 40 is attached to the element forming surface 1a of the silicon wafer 1,
In this state, it is set in the etching pot 8 and the back surface 1b of the silicon wafer 1 is etched to form the recess 11 while the wafer outer peripheral portion 10 is masked by the seal packing 9.

At this time, since the adhesive tape 40 is adhered to the element forming surface 1a of the silicon wafer 1, even if the silicon wafer 1 is broken during etching, it is possible to prevent the chips from falling apart. That is, it is possible to prevent the chips from falling apart even if the etching reaches the dicing notch 6 during the etching.

Further, as shown in FIG. 12, the silicon wafer 1 is placed with the element forming surface 1a facing downward with the adhesive tape 40 still attached to the element forming surface 1a of the silicon wafer 1, and the wafer back surface 1b is placed. Break roller 14 from above
Are directly brought into contact with each other for braking to separate the chips.

After that, as shown in FIG. 13, each chip 41 is taken out from the adhesive tape 40, mounted on a surface mounting portion, and soldered. At this time, since the adhesive tape 40 is attached to the element forming surface 1a of the silicon wafer 1, the chip 41 which is the flip chip element is directly attached to the desired mounting position on the stem after the braking is performed after the etching. Just put it on. That is, it suffices to dispose the wafer 1 after etching on the adhesive tape 40, separate each chip 41 by braking, and in this state, take out the chip 41 and place it directly on the mounting portion on the stem.

Also in the present embodiment, the pot etching apparatus shown in FIG. 8 is used as an etching apparatus for thin wall processing, and the adhesive tape 40 is attached to the element forming surface 1a of the silicon wafer 1 and set in the etching pot 8. Thereby, the adhesive tape 40 is also protected from the etching liquid 7. As described above, the pot etching apparatus shown in FIG. 8 is practically preferable also in this embodiment.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a method of thinning a semiconductor chip according to a first embodiment.

FIG. 2 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 3 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 4 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 5 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 6 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 7 is a sectional view of an etching pot.

FIG. 8 is a sectional view of an etching apparatus.

FIG. 9 is a partially enlarged sectional view of the etching apparatus.

FIG. 10 is a diagram showing a wafer after etching.

FIG. 11 is a cross-sectional view for explaining the method of thinning a semiconductor chip according to the second embodiment.

FIG. 12 is a sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 13 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 14 is a cross-sectional view for explaining a conventional method for thinning a semiconductor chip.

FIG. 15 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 16 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 17 is a sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 18 is a sectional view for explaining a thin-wall processing method of the same semiconductor chip.

FIG. 19 is a cross-sectional view for explaining a thin-wall processing method of the same semiconductor chip.

[Explanation of symbols]

1 ... Silicon wafer, 1a ... Element forming surface, 1b ... Back surface,
6 ... Dicing notch, 15 ... Chip, 20 ... Pot base, 21 ... Pot ring, 9 ... Seal packing,
26 ... X-shaped packing, 40 ... Adhesive tape, 41 ... Chip.

─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Hiroshi Tanaka 1-1, Showa-cho, Kariya city, Aichi Prefecture DENSO CORPORATION (56) References JP-A-3-270156 (JP, A) JP-A-1-289265 (JP, A) JP 5-198671 (JP, A) JP 63-164336 (JP, A) JP 7-211674 (JP, A) JP 8-316194 (JP, A) 58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/301

Claims (9)

(57) [Claims] 1. A first step of making a dicing notch of a predetermined depth from an element formation surface of a semiconductor wafer on which an element is formed, and an outer periphery of the wafer with respect to a back surface of the semiconductor wafer on which elements are not formed. A second step for etching the chip area to a thickness of 5 to 100 μm by etching to a predetermined depth leaving a portion, and a third step for separating each chip along a dicing cut in the semiconductor wafer. A method for thinning a semiconductor chip, characterized by: 2. The thin-wall processing method for a semiconductor chip according to claim 1, wherein the etching amount in the second step is an amount that does not reach the dicing notch. 3. The semiconductor chip according to claim 1, wherein an adhesive tape is attached to the element formation surface of the semiconductor wafer, and the wafer is thinned by etching to a predetermined depth while leaving an outer peripheral portion of the wafer. Thin-wall processing method. 4. The method of thinning a semiconductor chip according to claim 3, wherein the semiconductor wafer is divided into chips along a dicing notch in a state where an adhesive tape is attached to the element forming surface of the semiconductor wafer. 5. A step of grinding the semiconductor wafer from the rear surface on which no element is formed to a predetermined thickness before or after making a dicing notch of a predetermined depth from the element formation surface of the semiconductor wafer. The method for thinning a semiconductor chip according to claim 1, further comprising: 6. Impact on a wafer thinned by etching
Request to separate each chip by giving
Item 5. A method for thinning a semiconductor chip according to any one of Items 1 to 4 . 7. A device on a semiconductor wafer is formed.
Dicing cutting of a specified depth from the element formation surface to the same wafer
First step of forming a recess and the back surface of the semiconductor wafer on which elements are not formed
In contrast, etching is performed to a specified depth, leaving the outer peripheral portion of the wafer.
The second step of thinning the semiconductor wafer along with the dicing notch in the semiconductor wafer.
And a third step of separating each chip into individual chips, and etching to a predetermined depth while leaving the outer peripheral portion of the wafer thin.
When measuring the thickness, measure the thickness and
A method for thinning a semiconductor chip, characterized in that the etching is terminated . 8. The method of thinning a semiconductor chip according to claim 7 , wherein the thickness of the chip area is 5 to 100 μm in the second step . 9. A base material on which a semiconductor wafer is placed, a frame body which is cylindrical and is arranged on the base material with one opening thereof facing down, and the base material. With the semiconductor wafer placed, a seal packing for sealing the lower surface of the frame body and the outer peripheral portion of the semiconductor wafer in a liquid-tight state, and the base material and the frame body are pulled together to form a semiconductor with the seal packing. A fixing member for fixing the outer peripheral portion of the wafer in a sealed state, and a back surface of the semiconductor wafer, which is injected into the frame and has no elements formed thereon, is thinned by etching to a predetermined depth while leaving the outer peripheral portion of the wafer. An etching apparatus for thin-wall processing, comprising: