TWI669794B - 基板與晶片之壓合步驟及其壓合裝置 - Google Patents

基板與晶片之壓合步驟及其壓合裝置 Download PDF

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TWI669794B
TWI669794B TW107134150A TW107134150A TWI669794B TW I669794 B TWI669794 B TW I669794B TW 107134150 A TW107134150 A TW 107134150A TW 107134150 A TW107134150 A TW 107134150A TW I669794 B TWI669794 B TW I669794B
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substrate
layer
sticking layer
wafer
sticking
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TW107134150A
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TW202013644A (zh
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謝慶堂
Chin-Tang Hsieh
涂家榮
Chia-Jung Tu
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頎邦科技股份有限公司
Chipbond Technology Corporation
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Priority to TW107134150A priority Critical patent/TWI669794B/zh
Priority to CN201811554988.0A priority patent/CN110958782A/zh
Priority to JP2019010188A priority patent/JP6716728B2/ja
Priority to KR1020190010479A priority patent/KR102204147B1/ko
Priority to US16/260,524 priority patent/US20200105712A1/en
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Publication of TWI669794B publication Critical patent/TWI669794B/zh
Publication of TW202013644A publication Critical patent/TW202013644A/zh
Priority to US17/072,175 priority patent/US20210035947A1/en

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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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Abstract

一種基板與晶片之壓合步驟及其壓合裝置，在一晶片壓合至一基板的壓合製程中，藉由設置於一載台的一防沾黏層接觸該基板的一防焊層，在完成該壓合步驟後，藉由該防沾黏層的防沾黏特性，使該防焊層不會沾黏於該防沾黏層，以避免該防焊層產生殘留膠體於該壓合裝置，進而影響下一壓合步驟的壓合精密度。

Description

基板與晶片之壓合步驟及其壓合裝置
本發明是關於一種基板與晶片之壓合步驟及其壓合裝置，特別是一種壓合過程中避免一基板的一防焊層產生殘留膠體。
覆晶製程是半導體封裝製程中常使用的一種製程，其係觸壓一晶片及一基板，以使該晶片的複數個電極接合於該基板的複數個導接墊。
在優化電子商品的市場需求，必增加該晶片的電子特性，且必需在該基板的二側設置電路層，以使電子商品符合輕/薄/運算速度快等需求。
請參閱第1圖，其在習知的一種覆晶製程中將一晶片10壓合至一基板20，並以一載台30支撐該基板20，由於該基板20具有分別位於該基板20不同側的一第一防焊層21及一第二防焊層22，因此在壓合製程中，該第一防焊層21會接觸該載台30，請參閱第2圖，在壓合製程後，該第一防焊層21會產生一殘留膠體21a於該載台30，該第一防焊層21所產生的該殘留膠體21a會影響該載台30的平整度，當進行下一個壓合製程時，殘留在該載台30的該殘留膠體21a將造成另一晶片的電極(圖未繪出)與該基板的導接墊(圖未繪出)產生錯位，而使該晶片與該基板無法電性連接，此外，殘留在該載台30的該殘留膠體21a也可能在下一個壓合製程中沾黏於該第一防焊層21，而污染該基板20。
本發明的主要目的在於藉由設置於一載台的一防沾黏層，在壓合製程中，以該防沾黏層接觸一基板的一防焊層，避免該防焊層在壓合製程中在該載台上產生一殘留膠體。
本發明之一種基板與晶片之壓合步驟，包含提供一基板，該基板包含一本體、一第一線路層、一第二線路層、一第一防焊層及一第二防焊層，該本體具一第一表面及一第二表面，該第一線路層設置於該第一表面，該第一防焊層覆蓋該第一線路層，該第二線路層設置於該第二表面，該第二防焊層覆蓋該第二線路層，且該第二防焊層顯露出該第二線路層的複數個導接墊；提供一晶片，該晶片具有複數個電極；提供一壓合裝置，該壓合裝置包含一載台及一防沾黏層，該防沾黏層設置於該載台；以及進行一壓合製程，首先，將該基板的至少一待壓合區域段移動至該載台，且使該第一防焊層的一顯露表面朝向該防沾黏層，並使該第二線路層的該些導接墊位於該防沾黏層上方，接著，將該晶片壓合至該基板，並使該些電極壓合至該導接墊，以使該晶片與該基板結合成一體，在壓合製程中，以該防沾黏層支撐該基板，且以該防沾黏層接觸該第一防焊層，最後，使該第一防焊層離開該防沾黏層。
本發明之一種使用於基板與晶片壓合步驟之壓合裝置包含一載台及一防沾黏層，該防沾黏層設置於該載台，該防沾黏層用以在一晶片壓合至一基板的一壓合製程中支撐該基板，並以該防沾黏層接觸該基板的一防焊層。
本發明藉由設置於該載台的該防沾黏層，在該壓合製程中接觸該基板的該第一防焊層，並藉由該防沾黏層的防沾黏特性，防止該防焊層在壓合製程中產生殘留膠體於該載台。
10‧‧‧晶片
20‧‧‧基板
21‧‧‧第一防焊層
21a‧‧‧殘留膠體
22‧‧‧第二防焊層
30‧‧‧載台
100‧‧‧基板
100a‧‧‧待壓合區域段
110‧‧‧本體
110a‧‧‧第一表面
110b‧‧‧第二表面
120‧‧‧第一線路層
130‧‧‧第二線路層
131‧‧‧導接墊
140‧‧‧第一防焊層
140a‧‧‧顯露表面
150‧‧‧第二防焊層
200‧‧‧晶片
210‧‧‧電極
300‧‧‧壓合裝置
310‧‧‧載台
310a‧‧‧表面
310b‧‧‧投影區域
311‧‧‧第二通道
320‧‧‧防沾黏層
321‧‧‧第一通道
321a‧‧‧開口
321b‧‧‧溝槽
321c‧‧‧導通孔
322‧‧‧支撐表面
330‧‧‧壓合頭
S1‧‧‧提供一基板
S2‧‧‧提供一晶片
S3‧‧‧提供一壓合裝置
S4‧‧‧進行一壓合製程
第1圖：習知技術覆晶製程的示意圖。
第2圖：習知技術載台的示意圖。
第3圖：本發明之壓合步驟的流程圖。
第4A圖：本發明之壓合步驟的基板的示意圖。
第4B圖：本發明之壓合步驟的晶片的示意圖。
第4C圖：本發明之壓合步驟的壓合裝置的示意圖。
第4D圖：本發明之壓合步驟的壓合製程的示意圖。
第5A圖：本發明之壓合步驟的壓合製程的示意圖。
第5B圖：本發明之防沾黏層的上視圖。
第6A圖：本發明之壓合步驟的壓合製程的示意圖。
第6B圖：本發明之防沾黏層的上視圖。
第7A圖：本發明之壓合步驟的壓合製程的示意圖。
第7B圖：本發明之防沾黏層的上視圖。
請參閱第3圖，其為本發明之一實施例，一種基板與晶片之壓合步驟包含「提供一基板」步驟S1、「提供一晶片」步驟S2、「提供一壓合裝置」步 驟S3及「進行一壓合製程」步驟S4。
請參閱第3圖，在本實施例中，不限制該「提供一基板」步驟S1、該「提供一晶片」步驟S2及「提供一壓合裝置」步驟S3的先後順序。
請參閱第3及4A圖，在「提供一基板」的步驟S1中，所提供一基板100為一捲帶式基板，但本發明不以此為限，該基板100具有複數個待壓合區域段100a，該基板100包含一本體110、一第一線路層120、一第二線路層130、一第一防焊層140及一第二防焊層150，該本體110具一第一表面110a及一第二表面110b，該第一線路層120設置於該第一表面110a，該第一防焊層140覆蓋該第一線路層120，該第二線路層130設置於該第二表面110b，該第二防焊層150覆蓋該第二線路層130，且該第二防焊層150顯露出該第二線路層130的複數個導接墊131，該些導接墊131分別位於各該待壓合區域段100a，該第一防焊層140及該第二防焊層150的材料選自於綠漆(Solder mask or Solder Resist)。
請參閱第3及4B圖，在「提供一晶片」的步驟S2中，所提供的一晶片200具有複數個電極210，各該電極210用以壓合位各該待壓合區域段100a的該些導接墊131，使該晶片200與該基板100電性連接。
請參閱第3及4C圖，在「提供一壓合裝置」的步驟S3中，所提供的一壓合裝置300包含一載台310、一防沾黏層320及一壓合頭330，該防沾黏層320設置於該載台310，較佳地，在該防沾黏層320設置於該載台310前，預先粗糙化該載台310的一表面310a，該防沾黏層320設置於經粗糙化的該表面310a，以使該防沾黏層320可固定附著於該載台310，該防沾黏層320具有一支撐表面322，在本實施例中，該防沾黏層320選自於聚四氟乙烯(Polytetrafluoroethylene，PTFE)，將該防沾黏層320設置於該載台310的方法選自於網印(Screen Printing)、噴霧塗佈 (Spray Coating)滾輪塗佈(Roller Coating)或薄膜貼附，其中薄膜貼附方法是預先將該防沾黏層320形成為一薄膜，並將該防沾黏層320貼附於該壓合頭330。
請參閱第5A及5B圖，在不同的實施例中，該防沾黏層320包含複數個第一通道321，該載台310具有複數個第二通道311，各該第二通道311連通各該第一通道321，該些第一通道321具有複數個開口321a，該些開口321a位於該防沾黏層320的該支撐表面322，該第一通道321及該第二通道311供一氣體通過。
請參閱第6A及6B圖，在不同的實施例中，該第一通道321包含複數個溝槽321b，該開口321a為該溝槽321b的開口，較佳地，該些溝槽321b為一凹槽，請參閱第6A圖，該些溝槽321b未貫穿該防沾黏層320，該第一通道321包含複數個導通孔321c，該些導通孔321c連通未貫穿該防沾黏層320的該些溝槽321b，較佳地，該些溝槽321b相互連通，並使該防沾黏層320區隔成為複數個區塊。
請參閱第7A及7B圖，在不同的實施例中，該些溝槽321b貫穿該防沾黏層320，較佳地，該些溝槽321b相互連通，並使該防沾黏層320區隔成為複數個區塊。
請參閱第3及4D圖，在「進行一壓合製程」的步驟S4中，可以在一高於常溫的壓合環境中進行該壓合製程，首先，將該基板100的至少一待壓合區域段100a移動至該載台310，請參閱第4A及4D圖，在本實施例中，該防沾黏層320至少設置於該基板100的該待壓合區域段100a投影至該載台310的一投影區域310b，且使該第一防焊層140的一顯露表面140a朝向該防沾黏層320的該支撐表面322，並使該第二線路層130的該些導接墊131位於該防沾黏層320上方，接著，以該壓合頭330觸壓該晶片200，以使該第一防焊層140接觸該防沾黏層320，並使該些電極210壓合至該導接墊131，以將該晶片200與該基板100結合成一體，在該 壓合製程中，以該防沾黏層320支撐該基板100，且以該防沾黏層320接觸該第一防焊層140。
請參閱第3、5A、6A及7A圖，在該些不同的實施例中，進行該壓合製程S4時，是以各該第一通道321的各該開口321a吸附該基板100，以使該第一防焊層140接觸該防沾黏層320，並使該基板100暫時性地固定於該防沾黏層320，以避免該晶片200的該些電極210接觸該些導接墊131時，該基板100發生位移而導致該些電極210與該導接墊131發生錯位。
在完成壓合製程S4後，使該第一防焊層140離開該防沾黏層320，請參閱第5A、6A及7A圖，較佳地，可提供一氣體通過該些第一通道321及該些第二通道311，並藉由些開口321a提供一氣體，以使該基板100離開該防沾黏層320。
本發明藉由設置於該載台310的該防沾黏層320具有防沾黏特性，在該壓合製程中以該防沾黏層320接觸該基板100的該第一防焊層140，以避免該第一防焊層140在壓合製程中產生殘留膠體，使該防沾黏層320的該支撐表面322具有一致的平整度，以避免該第一防焊層140產生殘留膠體於該載台310而影響下一個壓合製程，且可避免該第一防焊層140產生殘留膠體而使該基板100被污染。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。

Claims (20)

  1. 一種基板與晶片之壓合步驟，包含：提供一基板及提供一晶片，該基板包含一本體、一第一線路層、一第二線路層、一第一防焊層及一第二防焊層，該本體具一第一表面及一第二表面，該第一線路層設置於該第一表面，該第一防焊層覆蓋該第一線路層，該第二線路層設置於該第二表面，該第二防焊層覆蓋該第二線路層，且該第二防焊層顯露出該第二線路層的複數個導接墊，該晶片具有複數個電極；提供一壓合裝置，該壓合裝置包含一載台及一防沾黏層，該防沾黏層設置於該載台；以及進行一壓合製程，首先，將該基板的至少一待壓合區域段移動至該載台，且使該第一防焊層的一顯露表面朝向該防沾黏層，並使該第二線路層的該些導接墊位於該防沾黏層上方，接著，將該晶片壓合至該基板，並使該些電極壓合至該導接墊，以將該晶片與該基板結合成一體，在該壓合製程中，以該防沾黏層支撐該基板，且以該防沾黏層接觸該第一防焊層。
  2. 如申請專利範圍第1項所述之基板與晶片之壓合步驟，其中該防沾黏層選自於聚四氟乙烯(Polytetrafluoroethylene，PTFE)。
  3. 如申請專利範圍第1項所述之基板與晶片之壓合步驟，其中該防沾黏層包含複數個第一通道，該些第一通道具有複數個開口，該些開口位於該防沾黏層的一支撐表面，該支撐表面朝向該第一防焊層，藉由該些開口吸附該基板，以使該第一防焊層接觸該防沾黏層，並使該基板暫時性地固定於該防沾黏層。
  4. 如申請專利範圍第3項所述之基板與晶片之壓合步驟，其中該第一通道包含複數個溝槽，該開口為該溝槽的開口。
  5. 如申請專利範圍第4項所述之基板與晶片之壓合步驟，其中該些溝槽為一凹槽，該些溝槽未貫穿該防沾黏層，該第一通道包含複數個導通孔，該些導通孔連通未貫穿該防沾黏層的該些溝槽。
  6. 如申請專利範圍第4項所述之基板與晶片之壓合步驟，其中該些溝槽貫穿該防沾黏層。
  7. 如申請專利範圍第4項所述之基板與晶片之壓合步驟，其中該些溝槽相互連通，並使該防沾黏層區隔成為複數個區塊。
  8. 如申請專利範圍第3項所述之基板與晶片之壓合步驟，其中該載台具有複數個第二通道，各該第二通道連通各該第一通道。
  9. 如申請專利範圍第1項所述之基板與晶片之壓合步驟，其中在該防沾黏層設置於該載台前，預先粗糙化該載台的一表面，該防沾黏層設置於經粗糙化的該表面，以使該防沾黏層可固定附著於該載台。
  10. 如申請專利範圍第1項所述之基板與晶片之壓合步驟，其中該防沾黏層設置於該載台的方法選自於網印(Screen Printing)、噴霧塗佈(Spray Coating)滾輪塗佈(Roller Coating)或薄膜貼附。
  11. 一種使用於基板與晶片壓合步驟之壓合裝置，包含：一載台；以及一防沾黏層，設置於該載台，該防沾黏層用以在一晶片的複數個電極壓合至一基板的複數個導接墊的一壓合製程中支撐該基板，並以該防沾黏層接觸該基板的一防焊層，其中該些導接墊位在該基板的一待壓合區域段，該防沾黏層至少設置於該基板的該待壓合區域段投影至該載台的一投影區域。
  12. 如申請專利範圍第11項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該防沾黏層選自於聚四氟乙烯(Polytetrafluoroethylene，PTFE)。
  13. 如申請專利範圍第11項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該防沾黏層包含複數個第一通道，該些第一通道具有複數個開口，該些開口位於該防沾黏層的一支撐表面，該支撐表面朝向該防焊層，藉由該些開口吸附該基板以使該防焊層接觸該防沾黏層，並使該基板暫時性地固定於該防沾黏層。
  14. 如申請專利範圍第13項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該第一通道包含複數個溝槽，該開口為該溝槽的開口。
  15. 如申請專利範圍第14項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該些溝槽為一凹槽，該些溝槽未貫穿該防沾黏層，該第一通道包含複數個導通孔，該些導通孔連通未貫穿該防沾黏層的該些溝槽。
  16. 如申請專利範圍第14項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該些溝槽貫穿該防沾黏層。
  17. 如申請專利範圍第14項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該些溝槽相互連通，並使該防沾黏層區隔成為複數個區塊。
  18. 如申請專利範圍第13項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該載台具有複數個第二通道，各該第二通道連通各該第一通道。
  19. 如申請專利範圍第11項所述之使用於基板與晶片壓合步驟之壓合裝置，其中在該防沾黏層設置於該載台前，預先粗糙化該載台的一表面，該防沾黏層設置於經粗糙化的該表面，以使該防沾黏層可固定附著於該載台。
  20. 如申請專利範圍第11項所述之使用於基板與晶片壓合步驟之壓合裝置，其中該防沾黏層設置於該載台的方法選自於網印(Screen Printing)、噴霧塗佈(Spray Coating)滾輪塗佈(Roller Coating)或薄膜貼附。
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