JP2011023407A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP2011023407A JP2011023407A JP2009164841A JP2009164841A JP2011023407A JP 2011023407 A JP2011023407 A JP 2011023407A JP 2009164841 A JP2009164841 A JP 2009164841A JP 2009164841 A JP2009164841 A JP 2009164841A JP 2011023407 A JP2011023407 A JP 2011023407A
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Abstract
【解決手段】半導体装置が、互いの端子面を有さない背面同士が接着剤層を介して接着された第1の半導体素子と第2の半導体素子と、第2の半導体素子の端子面と同一面に設けられた端子部材と、前記端子部材と前記第1の半導体素子の端子面とを接続する導電性ワイヤとを備える。
【選択図】図1
Description
複数の半導体チップに対して電極を一括形成することにより低コストで半導体部品が製造できる。
ところで近年、携帯端末やデジタル家電においてSiP(System in Package)と呼ばれる高機能でかつ小型の半導体装置の使用が広がっている。
SiPの半導体装置を上記した従来技術を用いて製造する場合、半導体素子が平面的に配置されるため、半導体装置の小型化が困難である。
を備える。
以下、本発明を実施するための最良の形態を図面に基づき説明する。図1は本発明の第1の実施の形態にかかる半導体装置1を示す断面図である。
図1に示すように半導体装置1は、再配線用端子101、半導体チップ102、チップ部品103、半導体チップ104、素子接着剤層105、ワイヤ106、封止樹脂107、絶縁膜108、配線109、保護膜110、UBM(Under Bump Metal)膜111及びはんだバンプ112を備える。
半導体チップ104は、第1の半導体素子であり、例えばメモリとしての機能を備える。半導体チップ104は、半導体チップ102と同様に端子面及び背面を備える。半導体チップ104は、端子面が図1における上方向に向けられ、背面が半導体チップ102の背面に対面するように配置される。半導体チップ104の端子面は、ワイヤ106によって、再配線用端子101に接続される。
封止樹脂107は、再配線用端子101、半導体チップ102、チップ部品103、半導体チップ104、素子接着剤層105及びワイヤ106を封止するための部材であり、例えば、石英の微粉末などを充填剤とした熱硬化性樹脂である。
封止樹脂107の熱硬化によって、再配線用端子101、半導体チップ102、チップ部品103、半導体チップ104、素子接着剤層105及びワイヤ106をまとめて一つの部材として扱うことができる。封止樹脂107及びこの封止樹脂107によって封止された再配線用端子101、半導体チップ102、チップ部品103、半導体チップ104、素子接着剤層105及びワイヤ106を擬似ウェーハ100と称す。
擬似ウェーハ100の高さ方向の厚みはワイヤ106が隠れる程度が好ましいが、封止樹脂107の硬化後の反りや強度、ウェーハプロセスで処理可能な厚みなどを考慮して適宜変更が可能である。
擬似ウェーハ100において、半導体チップ102の端子面、チップ部品103の端子面及び再配線用端子101の1つの面が同一平面上に露出する。これら半導体チップ102の端子面、チップ部品103の端子面及び再配線用端子101の1つの面が露出する擬似ウェーハ100の面上には、ウェーハプロセスの過程で絶縁膜108、配線109、保護膜110、UBM膜111及びはんだバンプ112が順に形成される。
はんだバンプ112は、半導体装置1が搭載される図示しないプリント基板との接合部であり、はんだバンプ112を介して、半導体チップ102、104、チップ部品103及びプリント基板との間で電気信号の送受信が行われる。
はんだバンプ112は、UBM膜111上に、メッキを付けた後、はんだを供給し、このはんだを加熱して溶解させることによって形成される。はんだバンプ112は、UBM膜111上に、はんだペーストを印刷することでも形成可能である。すなわち、印刷されたはんだペーストは、はんだバンプ112の元となる。
また、UBM膜111間のピッチが0.3mm以上の場合、はんだバンプ112に替えてはんだボール(図示せず)をUBM膜111上に取り付けることもできる。
はんだボールをUBM膜111上に取り付ける場合、UBM膜111上に酸化物を溶解するためのフラックスを塗布したのち、はんだボールを搭載する。そして、リフローすることではんだボールが溶解し、はんだボールとUBM膜111が接合する。
図2に示すように、半導体装置1の製造には、粘着シート120が張られた支持基板130が用いられる。
支持基板130は、擬似ウェーハ100を形成する土台である。支持基板130は、平坦性、強度、寸法安定性が良好なものであるものが好ましく、例えば、ガラス板や石英板が好ましい。また、支持基板130は、擬似ウェーハ100を既存のウェーハプロセスで処理可能なように円状であることが好ましい。既存のウェーハプロセスが矩形状のウェーハを処理可能ならば、支持基板130も矩形状でよい。すなわち、支持基板130の形状は、既存のウェーハプロセスに対応させて種々の変形が可能である。
支持基板130の外形寸法は、擬似ウェーハ100を既存のウェーハサイズに合わせてカットすることを考慮して、ウェーハプロセスで処理される通常のウェーハサイズよりも数mm程度大きくしておくことが望ましい。
粘着シート120の弾性率及びまたは厚さは、ワイヤ106がボンディング可能であることが望ましい。粘着シート120は、図示しないローラ装置に、同様に図示しない剥離用フィルムを介して取り付けられ、このローラ装置によって支持基板130に貼り付けられる。
粘着剤フィルム140bは、粘着シート120よりも弱い粘着性を備える。粘着剤フィルム140bは、のり残りなどせず綺麗に剥離可能な材料で形成されることが望ましい。粘着剤フィルム140bには、あらかじめ再配線用端子101を形成しておくことが望ましい。例えば、粘着剤フィルム140bに、銅拍を張り、この銅拍にメッキ、マスクを用いた選択的エッチングを施して再配線用端子101を形成する。
再配線用端子101は、粘着剤フィルム140bの粘着力によって保持される。なお、粘着剤フィルム140bは、再配線用端子101が形成される位置にのみ粘着性を備えればよく、再配線用端子101形成の過程において、再配線用端子101が形成される位置以外の粘着性が失われても問題ない。
なお、後述の工程において、半導体チップ102、チップ部品103を粘着シート120上に載置するが、再配線用端子101に対する位置精度を上げるため、前述の転写工程において、アライメントマークになる端子を再配線用端子と一緒に粘着シート120上に転写するのがよい。転写されたアライメントマークを目標に半導体チップ102、チップ部品103を載置すれば、良好な相対位置精度を得ることができる。
さらに、図7に示すように、粘着シート120に載置された半導体チップ102上に、素子接着剤層105を介して半導体チップ104を載置する。
なお、半導体チップ102、チップ部品103は粘着シート120上に複数配置することができる。また、チップ部品103は、粘着シート120上に配置されない場合もある。
また、半導体チップ104と半導体チップ102の配置関係は、逆にすることもできる。すなわち、半導体チップ104を粘着シート120上に配置し、半導体チップ102を半導体チップ104上に積載するようにしてもよい。その場合は、半導体チップ104の端子面が下方向に、半導体チップ102の端子面が上方向に配置され、それぞれのチップの背面が対面するようになる。
なお封止樹脂107を支持基板130に印刷することで再配線用端子101、半導体チップ102、チップ部品103、半導体チップ104、素子接着剤層105及びワイヤ106を封止することもできる。この場合、支持基板130の上にマスクを掛けマスクの上から液状の封止樹脂107を滴下する。次に、マスク上面をスクイージングし、所定の厚さに仕上げる。スクイージング終了後に、マスクを外し、支持基板130ごとオーブンに入れ、加熱することで封止樹脂107を硬化させる。
次に、図11〜図15に示すように、粘着シート120から剥離した擬似ウェーハ100に絶縁膜108、配線109、保護膜110、UBM膜111及びはんだバンプ112を順に形成していく。
チャックテーブルは、擬似ウェーハ100の所定箇所(例えば、図16中の保護膜110などが形成されていない封止樹脂107の一部分)を既存の半導体ウェーハと同様のサイズに切断するための台である。チャックテーブルに固定した擬似ウェーハ100をダイシングブレード170を用いて切断する(図16において、ダイシングブレード170もダイシングテープ160と同様にハッチングを省略する)。
近年、従来の半導体装置の高性能化に伴い、この半導体装置で使用されるメモリ素子のチップサイズは大型化する傾向にある。メモリ素子及びこのメモリ素子に接続される演算素子を平面上に並べて配置した場合、メモリ素子のチップサイズに対応して半導体装置の外形寸法が大きくなる。
この実施の形態の半導体装置1では、半導体チップ102及び半導体チップ104を積載することで、粘着シート120上での搭載面積を狭くでき、半導体装置1の外形寸法が大きくなることを抑制することができる。
また擬似ウェーハ100に対して一括して配線処理及びバンプ処理が可能となり、低コストで半導体装置1を製造することができる。
さらに、半導体装置1の製造過程において、ダイシングブレード170で擬似ウェーハ100から半導体装置1を切りだす際に、封止樹脂107を切断するので、半導体チップ102及び半導体チップ104への悪影響(歪みや亀裂の発生など)を抑制できる。
要するに、この実施の形態に係る製造方法によれば、小型化の要求が強い携帯端末用途において、擬似ウェーハ100を使った半導体ウェーハの一括処理の製造方法のメリット(高密度、高信頼性、ローコスト)を生かしつつ、メモリ混載型のSiPの小型化が可能となる。
(効果例1)
例えば、半導体チップ102の端子面が半導体チップ104の背面と対向するよう(すなわち、半導体チップ102の端子面が図17中の下側を向くよう)に半導体チップ102を配置し、半導体チップ102と半導体チップ104を接合する場合がある。この場合には、半導体チップ102の端子面の所定の領域に、半導体チップ104の背面との接合面を設け、この領域に素子接着剤層105を形成するが、このとき、素子接着剤層105には半導体チップ102に形成された接続端子のショート防止のために絶縁性を有する接着材を使用する必要がある。
一方、半導体装置1のように半導体チップ102と半導体チップ104とを背中合わせに接合する場合には素子接着剤層105に銀ペーストのような導電性を有する接着剤を使用できる。銀ペーストを使用した場合、半導体チップ102を発生源とする電磁波(ノイズ)を吸収させることができ、電磁波による半導体チップ104の誤動作を防止することができる。
(効果例2)
同様に、半導体チップ102の端子面と半導体チップ104の背面とを対向させて接合する場合、ブリードによって半導体チップ102の端子面が汚染され、半導体チップ102に形成された接続端子の劣化や導通不良が起きる可能性がある。ブリードとは、素子接着剤層105に含まれる溶剤が端子面などに広がりながら染み出す現象である。
半導体チップ102と半導体チップ104とを背中合わせに接合する場合、ブリードが発生しても接続端子の劣化や導通不良を防止することができる。
(効果例3)
また、半導体チップ104の端子面と半導体チップ102の背面とを対向させて接合する場合がある。このとき、半導体チップ104が半導体チップ102より小さい場合、半導体チップ104の接続端子と再配線用端子101をワイヤ106で接続するためには、半導体チップ104と半導体チップ102の間にスペーサを挿入する必要がある。半導体チップ102と半導体チップ104とを背中合わせに接合する場合、スペーサを挿入する必要がなくなり、半導体装置1製造のためのコストを抑えることができる。
(変更例1)
次に図18〜図21を用いて、再配線用端子101形成方法の変更例1を説明する。図18〜図21は、変更例1にかかる再配線用端子101形成のプロセスを順に示す断面図である。
上記第1の実施の形態では、転写によって再配線用端子101を支持基板130上に形成したが、この変更例1では、凹板200を用いた印刷によって再配線用端子101を形成する。
具体的には、まず、凹板200の所定の位置に金属ペースト210を滴下する。例えば、図18の金属ペースト210を示す破線の位置に滴下する。金属ペースト210は、銀、銅、金、アルミの少なくとも1つの金属粉末を主原料とする。
その後、スクイージー220によって滴下した金属ペースト210をならす。この結果、凹板200に形成された凹部200aに金属ペースト210の一部が流入し、再配線用端子部材101aが形成される。凹部200aは、再配線用端子部材101aの厚みが10μm〜100μm程度になるような深さであることが望ましい。
次に、転写パット230を支持基板130上へ移動する。このとき、転写パット230には、再配線用端子部材101aが張り付いている。
図20に示すように再配線用端子部材101aが粘着シート120に接触するように転写パット230を支持基板130に接触させることにより、支持基板130上(粘着シート120上)に再配線用端子部材101aが印刷される。この印刷方法はパット印刷と呼ばれる。
なお、再配線用端子部材101aは、1回の工程で支持基板130上に印刷してもよいし、再配線用端子部材101aの支持基板130上での厚みが所定の厚みに達するまで印刷を繰り返し行ってもよい。
また、半導体装置1を複数製造する場合がある。この場合、製造する複数の半導体装置1に対応する複数の支持基板130に対して一括して再配線用端子部材101aの印刷を行ってもよく、また、複数の支持基板130に対して順次再配線用端子部材101aの印刷を行ってもよい。さらに、所定数の支持基板130をグループ分けし、グループ毎に再配線用端子部材101aを印刷してもよい。
上記の第1の実施の形態または変更例1では、転写用シート140を用いて粘着シート120上に再配線用端子101を転写し、または転写パット230を用いて再配線用端子部材101aを印刷したが、支持基板130そのものを転写用シート140または転写パット230の代わりにしてもよい。
すなわち、第1の実施の形態で説明した転写用シート140に替えて支持基板130の粘着シート120上に直接、再配線用端子101を形成してもよいし、変更例1で説明した凹板200に対して、転写パット230ではなく、支持基板130上の粘着シート120を接触させるようにしてよい。
この場合、転写用シート140や転写パット230を使用しなくて済み半導体装置1の製造にかかるコストを抑えることができる。また、支持基板130そのものを転写用シート140または転写パット230の代わりにすることで、再配線用端子101を形成するための工程数が少なくなり、半導体装置1を効率良く製造することができる。
再配線用端子101の形成方法はさらなる変更が可能である。次に図22〜図24を用いて、再配線用端子101形成の変更例3を説明する。図22〜図24は、変更例3にかかる再配線用端子101形成のプロセスを順に示す断面図である。
この変更例3では、スパッタ装置300を用いて再配線用端子101を形成する。スパッタ装置300で使用されるターゲット310は、例えば、金やアルミである。
まず、再配線用端子101を粘着シート120上の所定の位置に形成するための開口部320aを備えるマスク320を粘着シート120上に配置する。
マスク320は、粘着シート120から容易に剥離できる素材で形成するか、粘着シート120から容易に剥離できるような表面処理を施すことが望ましい。
スパッタ装置300において、高圧電圧の印加に伴ってイオン化した充填ガスがターゲット310に衝突し、この結果ターゲット310から金属粒子が飛び出し、金属の薄膜101bが形成される。具体的には、図23に示すように、マスク320の上に薄膜101bが形成される。また、開口部320aを通過した金属粒子によって粘着シート120上にも薄膜101bが形成される。
粘着シート120上に形成された薄膜101bが再配線用端子101として機能する。アルミ製の再配線用端子101を形成する場合、再配線用端子101の高さ方向の厚みが約200nm以上あれば、ワイヤ106の接続に必要なボンディング性を得ることができる。なお、薄膜101bの厚み、すなわち、再配線用端子101の厚みは、スパッタ装置300の操作により、適宜調整することができる。
以上説明したように、この変更例3によれば、スパッタ装置300を用いることにより再配線用端子101を形成することができる。
(その他の変更例)
上記変更例3において、再配線用端子101の形成のためにマスク320を用いたが、粘着シート120に張り付けられた図示しない剥離用フィルムをマスク320の代用品としてもよい。この場合、剥離用フィルムには、開口部320aに対応する開口を設けておく。そして、粘着シート120を支持基板130に張り付ける際に、この剥離用フィルムを粘着シート120のマスク用フィルムとしてそのまま残しておく。この状態でスパッタ装置300によるスパッタリングを行うことで、マスク320を用いたときと同様に再配線用端子101を粘着シート120に形成することができる。
保護フィルムをマスク320の代わりとすることで、粘着シート120へのマスク320の貼り付けや剥離する工程を省略でき、再配線用端子101を効率良く製造することができる。そして、再配線用端子101を効率良く製造することで、結果的に半導体装置1を効率よく製造することができる。また、保護フィルムをマスク320の代わりとすることで、マスク320にかかるコストを削減することができる。
Claims (5)
- 互いの端子面を有さない背面同士が接着剤層を介して接着された第1の半導体素子と第2の半導体素子と、
前記第2の半導体素子の端子面と同一面に設けられた端子部材と、
前記端子部材と前記第1の半導体素子の端子面とを接続する導電性ワイヤと
を備えることを特徴とする半導体装置。 - 粘着性を有するシート上に、第1の半導体素子と接続される端子部材を形成するステップと、
前記端子部材が形成された前記シート上に第2の半導体素子を搭載するステップと、
前記第2の半導体素子上に接着剤層を介して前記第1の半導体素子を搭載するステップと、
前記第1の半導体素子と、前記端子部材とをワイヤを介して接続するステップと、
前記第1、第2の半導体素子、端子部材、ワイヤを含む樹脂層を前記シート上に形成するステップと、
前記シートの粘着性を低下させるステップと、
前記粘着性が低下したシートから前記樹脂層を剥離するステップと
を備えることを特徴とする半導体装置の製造方法。 - 前記端子部材は、前記粘着シートより弱い粘着力の粘着フィルム上に形成され、前記粘着フィルムの裏面からの加圧により前記粘着シート上に転写することで前記端子部材が前記粘着シート上に形成されることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記端子部材の形状に対応する穴部を有する部材にペースト状の金属を流入させ、前記流入した金属を前記シートに印刷することで前記端子部材が前記シート上に形成されることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記端子部材の形状に対応する穴部を有するマスク部材を前記シート上に被せ、スパッタリングによって前記端子部材が前記シート上に形成されることを特徴とする請求項2記載の半導体装置の製造方法。
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JP2000294722A (ja) * | 1999-04-01 | 2000-10-20 | Nec Corp | 積層化チップ半導体装置 |
JP2002124625A (ja) * | 2000-10-16 | 2002-04-26 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002151643A (ja) * | 2000-11-16 | 2002-05-24 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2007324406A (ja) * | 2006-06-01 | 2007-12-13 | Sony Corp | 基板処理方法及び半導体装置の製造方法 |
JP2009117611A (ja) * | 2007-11-06 | 2009-05-28 | Shinko Electric Ind Co Ltd | 半導体パッケージ |
JP2010073893A (ja) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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US20110006417A1 (en) | 2011-01-13 |
JP5100715B2 (ja) | 2012-12-19 |
US8629001B2 (en) | 2014-01-14 |
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