CN110958782A - 基板与芯片的压合方法及其压合装置 - Google Patents
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Abstract
本发明提供一种基板与芯片的压合方法及其压合装置,在芯片压合至基板的压合制程中,借由设置于载台的防沾黏层接触该基板的防焊层,在完成该压合步骤后,借由该防沾黏层的防沾黏特性,使该防焊层不会沾黏于该防沾黏层,以避免该防焊层产生残留胶体于该压合装置,进而影响下一压合步骤的压合精密度。
Description
技术领域
本发明是关于一种基板与芯片的压合方法及其压合装置,特别是一种压合过程中避免基板的防焊层产生残留胶体的基板与芯片的压合方法及其压合装置。
背景技术
覆晶制程是半导体封装制程中常使用的一种制程,其是触压芯片及基板,以使该芯片的多个电极接合于该基板的多个导接垫。
在优化电子商品的市场需求,必增加该芯片的电子特性,且必需在该基板的两侧设置电路层,以使电子商品符合轻/薄/指令周期快等需求。
请参阅图1,其在现有的一种覆晶制程中将芯片10压合至基板20,并以载台30支撑该基板20,由于该基板20具有分别位于该基板20不同侧的第一防焊层21及第二防焊层22,因此在压合制程中,该第一防焊层21会接触该载台30,请参阅图1,在压合制程后,该第一防焊层21会产生残留胶体21a在该载台30上,该第一防焊层21所产生的该残留胶体21a会影响该载台30的平整度,当进行下一个压合制程时,残留在该载台30的该残留胶体21a将造成另一芯片的电极(图未绘出)与该基板的导接垫(图未绘出)产生错位,而使该芯片与该基板无法电性连接,此外,残留在该载台30的该残留胶体21a也可能在下一个压合制程中沾黏于该第一防焊层21,而污染该基板20。
发明内容
本发明的主要目的在于借由设置于载台的防沾黏层,在压合制程中,以该防沾黏层接触基板的防焊层,避免该防焊层在压合制程中在该载台上产生残留胶体。
本发明的一种基板与芯片的压合方法,包含提供基板,该基板包含本体、第一线路层、第二线路层、第一防焊层及第二防焊层,该本体具第一表面及第二表面,该第一线路层设置于该第一表面,该第一防焊层覆盖该第一线路层,该第二线路层设置于该第二表面,该第二防焊层覆盖该第二线路层,且该第二防焊层显露出该第二线路层的多个导接垫;提供芯片,该芯片具有多个电极;提供压合装置,该压合装置包含载台及防沾黏层,该防沾黏层设置于该载台;以及进行压合制程,首先,将该基板的至少一个待压合区域段移动至该载台,且使该第一防焊层的显露表面朝向该防沾黏层,并使该第二线路层的该多个导接垫位于该防沾黏层上方,接着,将该芯片压合至该基板,并使该多个电极压合至该导接垫,以使该芯片与该基板结合成一体,在压合制程中,以该防沾黏层支撑该基板,且以该防沾黏层接触该第一防焊层,最后,使该第一防焊层离开该防沾黏层。
进一步地,该防沾黏层选自于聚四氟乙烯(Polytetrafluoroethylene,PTFE)。
进一步地,该防沾黏层包含多个第一通道,该多个第一通道具有多个开口,该多个开口位于该防沾黏层的支撑表面,该支撑表面朝向该第一防焊层,借由该多个开口吸附该基板,以使该第一防焊层接触该防沾黏层,并使该基板暂时性地固定于该防沾黏层。
进一步地,该第一通道包含多个沟槽,该开口为该沟槽的开口。
进一步地,该多个沟槽为凹槽,该多个沟槽未贯穿该防沾黏层,该第一通道包含多个导通孔,该多个导通孔连通未贯穿该防沾黏层的该多个沟槽。
进一步地,该多个沟槽贯穿该防沾黏层。
进一步地,该多个沟槽相互连通,并使该防沾黏层区隔成为多个区块。
进一步地,该载台具有多个第二通道,各该第二通道连通各该第一通道。
进一步地,在该防沾黏层设置于该载台前,预先粗糙化该载台的表面,该防沾黏层设置于经粗糙化的该表面,以使该防沾黏层可固定附着于该载台。
进一步地,该防沾黏层设置于该载台的方法选自于网印(Screen Printing)、喷雾涂布(Spray Coating)滚轮涂布(Roller Coating)或薄膜贴附。
本发明的一种使用于基板与芯片压合方法的压合装置,包含载台及防沾黏层,该防沾黏层设置于该载台,该防沾黏层用以在芯片压合至基板的压合制程中支撑该基板,并以该防沾黏层接触该基板的防焊层。
进一步地,该防沾黏层选自聚四氟乙烯(Polytetrafluoroethylene,PTFE)。
进一步地,该防沾黏层包含多个第一通道,该多个第一通道具有多个开口,该多个开口位于该防沾黏层的支撑表面,该支撑表面朝向该防焊层,借由该多个开口吸附该基板以使该防焊层接触该防沾黏层,并使该基板暂时性地固定于该防沾黏层。
进一步地,该第一通道包含多个沟槽,该开口为该沟槽的开口。
进一步地,该多个沟槽为凹槽,该多个沟槽未贯穿该防沾黏层,该第一通道包含多个导通孔,该多个导通孔连通未贯穿该防沾黏层的该多个沟槽。
进一步地,该多个沟槽贯穿该防沾黏层。
进一步地,该多个沟槽相互连通,并使该防沾黏层区隔成为多个区块。
进一步地,该载台具有多个第二通道,各该第二通道连通各该第一通道。
进一步地,在该防沾黏层设置于该载台前,预先粗糙化该载台的表面,该防沾黏层设置于经粗糙化的该表面,以使该防沾黏层可固定附着于该载台。
进一步地,该防沾黏层设置于该载台的方法选自于网印(Screen Printing)、喷雾涂布(Spray Coating)滚轮涂布(Roller Coating)或薄膜贴附。
本发明借由设置于该载台的该防沾黏层,在该压合制程中接触该基板的该第一防焊层,并借由该防沾黏层的防沾黏特性,防止该防焊层在压合制程中产生残留胶体于该载台。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附图式的说明如下:
图1为现有技术的覆晶制程的示意图;
图2为现有技术的载台的示意图;
图3为本发明的压合方法的流程图;
图4A为本发明的压合方法的基板的示意图;
图4B为本发明的压合方法的芯片的示意图;
图4C为本发明的压合方法的压合装置的示意图;
图4D为本发明的压合方法的一压合制程的示意图;
图5A为本发明的压合方法的压合制程的示意图;
图5B为本发明的一防沾黏层的俯视图;
图6A为本发明的压合方法的另一压合制程的示意图;
图6B为本发明的另一防沾黏层的俯视图;
图7A为本发明的压合方法的又一压合制程的示意图;
图7B为本发明的又一防沾黏层的俯视图。
【主要元件符号说明】
10芯片 20基板
21第一防焊层 21a残留胶体
22第二防焊层 30载台
100基板 100a待压合区域段
110本体 110a第一表面
112b第二表面 120第一线路层
130第二线路层 131导接垫
140第一防焊层 140a显露表面
150第二防焊层 200芯片
210主动面 210电极
300压合装置 310载台
310a表面 311第二通道
320防沾黏层 321第一通道
321a开口 321b沟槽
321c导通孔 322支撑表面
330压合头 S1提供基板
S2提供芯片 S3提供压合装置
S4进行压合制程
具体实施方式
为了使本发明的叙述更加详尽与完备,下文针对了本发明的实施态样与具体实施例提出了说明性的描述;但这并非实施或运用本发明具体实施例的唯一形式。以下所揭露的各实施例,在有益的情形下可相互组合或取代,也可在一实施例中附加其他的实施例,而无须进一步的记载或说明。在以下描述中,将详细叙述许多特定细节以使读者能够充分理解以下的实施例。然而,可在无此等特定细节的情况下实践本发明的实施例。
兹将本发明的实施方式详细说明如下,但本发明并非局限在实施例范围。
请参阅图3,其为本发明的一实施例,一种基板与芯片的压合方法,包含:步骤S1、提供基板;步骤S2、提供芯片;步骤S3、提供压合装置及步骤S4、进行压合制程。
请参阅图3,在本实施例中,不限制该步骤S1、提供基板;该步骤S2、提供芯片及步骤S3、提供压合装置的先后顺序。
请参阅图3及图4A,在步骤S1中,所提供的基板100为卷带式基板,但本发明不以此为限,该基板100具有多个待压合区域段100a,该基板100包含本体110、第一线路层120、第二线路层130、第一防焊层140及第二防焊层150,该本体110具第一表面110a及第二表面110b,该第一线路层120设置于该第一表面110a,该第一防焊层140覆盖该第一线路层120,该第二线路层130设置于该第二表面110b,该第二防焊层150覆盖该第二线路层130,且该第二防焊层150显露出该第二线路层130的多个导接垫131,该多个导接垫131分别位于各该待压合区域段100a,该第一防焊层140及该第二防焊层150的材料选自于绿漆(Solder maskor Solder Resist)。
请参阅图3及图4B,在步骤S2中,所提供的芯片200具有多个电极210,各该电极210用以压合位各该待压合区域段100a的该多个导接垫131,使该芯片200与该基板100电性连接。
请参阅图3及图4C,在步骤S3中,所提供的压合装置300包含载台310、防沾黏层320及压合头330,该防沾黏层320设置于该载台310,较佳地,在该防沾黏层320设置于该载台310前,预先粗糙化该载台310的表面310a,该防沾黏层320设置于经粗糙化的该表面310a,以使该防沾黏层310a可固定附着于该载台310,该防沾黏层320具有支撑表面322,在本实施例中,该防沾黏层320选自于聚四氟乙烯(Polytetrafluoroethylene,PTFE),将该防沾黏层320设置于该载台310的方法选自于网印(Screen Printing)、喷雾涂布(Spray Coating)滚轮涂布(Roller Coating)或薄膜贴附,其中薄膜贴附方法是预先将该防沾黏层320形成为薄膜,并将该防沾黏层320贴附于该压合头330。
请参阅图5A及图5B,在不同的实施例中,该防沾黏层320包含多个第一通道321,该载台310具有多个第二通道311,各该第二通道311连通各该第一通道321,该多个第一通道321具有多个开口321a,该多个开口321a位于该防沾黏层320的该支撑表面322,该第一通道321及该第二通道311供气体通过。
请参阅图6A及图6B,在不同的实施例中,该第一通道321包含多个沟槽321b,该开口321a为该沟槽321b的开口,较佳地,该多个沟槽321b为凹槽,请参阅图6A,该多个沟槽321b未贯穿该防沾黏层320,该第一通道321包含多个导通孔321c,该多个导通孔321c连通未贯穿该防沾黏层320的该多个沟槽321b,较佳地,该多个沟槽321b相互连通,并使该防沾黏层320区隔成为多个区块。
请参阅图7A及图7B,在不同的实施例中,该多个沟槽321b贯穿该防沾黏层320,较佳地,该多个沟槽321b相互连通,并使该防沾黏层320区隔成为多个区块。
请参阅图3及图4D,在步骤S4中,可以在高于常温的压合环境中进行该压合制程,首先,将该基板100的至少一个待压合区域段100a移动至该载台310,且使该第一防焊层140的显露表面140a朝向该防沾黏层320的该支撑表面322,并使该第二线路层130的该多个导接垫131位于该防沾黏层320上方,接着,以该压合头330触压该芯片200,以使该第一防焊层140接触该防沾黏层320,并使该多个电极210压合至该导接垫131,以将该芯片200与该基板100结合成一体,在压合制程中,以该防沾黏层320支撑该基板100,且以该防沾黏层320接触该第一防焊层140。
请参阅图3、图5A、图6A及图7A,在该多个不同的实施例中,进行该压合制程的步骤S4时,是以各该第一通道321的各该开口321a吸附该基板100,以使该第一防焊层140接触该防沾黏层320,并使该基板100暂时性地固定于该防沾黏层320,以避免该芯片200的该多个电极210接触该多个导接垫131时,该基板100发生位移而导致该多个电极210与该导接垫131发生错位。
在完成压合制程的步骤S4后,使该第一防焊层140离开该防沾黏层320,请参阅图5A、图6A及图7A,较佳地,可提供气体通过该多个第一通道321及该多个第二通道311,并借由些开口321a提供气体,以使该基板100离开该防沾黏层320。
本发明借由设置于该载台310的该防沾黏层320具有防沾黏特性,在该压合制程中以该防沾黏层320接触该基板100的该第一防焊层140,以避免该防焊层140在压合制程中产生残留胶体,使该防沾黏层320的该支撑表面322具有一致的平整度,以避免该防焊层140产生残留胶体于该载台310而影响下一个压合制程,且可避免该防焊层140产生残留胶体而使该基板100被污染。
以上所述,仅是本发明的较佳实施例而已,并非对本发明做任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (20)
1.一种基板与芯片的压合方法,其特征在于,包含:
提供基板及提供芯片,该基板包含本体、第一线路层、第二线路层、第一防焊层及第二防焊层,该本体具有第一表面及第二表面,该第一线路层设置于该第一表面,该第一防焊层覆盖该第一线路层,该第二线路层设置于该第二表面,该第二防焊层覆盖该第二线路层,且该第二防焊层显露出该第二线路层的多个导接垫,该芯片具有多个电极;
提供压合装置,该压合装置包含载台及防沾黏层,该防沾黏层设置于该载台;以及
进行压合制程,首先,将该基板的至少一个待压合区域段移动至该载台,且使该第一防焊层的显露表面朝向该防沾黏层,并使该第二线路层的该多个导接垫位于该防沾黏层上方,接着,将该芯片压合至该基板,并使该多个电极压合至该导接垫,以将该芯片与该基板结合成一体,在压合制程中,以该防沾黏层支撑该基板,且以该防沾黏层接触该第一防焊层。
2.根据权利要求1所述的基板与芯片的压合方法,其特征在于,该防沾黏层选自于聚四氟乙烯。
3.根据权利要求1所述的基板与芯片的压合方法,其特征在于,该防沾黏层包含多个第一通道,该多个第一通道具有多个开口,该多个开口位于该防沾黏层的支撑表面,该支撑表面朝向该第一防焊层,借由该多个开口吸附该基板,以使该第一防焊层接触该防沾黏层,并使该基板暂时性地固定于该防沾黏层。
4.根据权利要求3所述的基板与芯片的压合方法,其特征在于,该第一通道包含多个沟槽,该开口为该沟槽的开口。
5.根据权利要求4所述的基板与芯片的压合方法,其特征在于,该多个沟槽为凹槽,该多个沟槽未贯穿该防沾黏层,该第一通道包含多个导通孔,该多个导通孔连通未贯穿该防沾黏层的该多个沟槽。
6.根据权利要求4所述的基板与芯片的压合方法,其特征在于,该多个沟槽贯穿该防沾黏层。
7.根据权利要求4所述的基板与芯片的压合方法,其特征在于,该多个槽相互连通,并使该防沾黏层区隔成为多个区块。
8.根据权利要求3所述的基板与芯片的压合方法,其特征在于,该载台具有多个第二通道,各该第二通道连通各该第一通道。
9.根据权利要求1所述的基板与芯片的压合方法,其特征在于,在该防沾黏层设置于该载台前,预先粗糙化该载台的表面,该防沾黏层设置于经粗糙化的该表面,以使该防沾黏层可固定附着于该载台。
10.根据权利要求1所述的基板与芯片的压合方法,其特征在于,该防沾黏层设置于该载台的方法选自于网印、喷雾涂布滚轮涂布或薄膜贴附。
11.一种使用于基板与芯片压合方法的压合装置,其特征在于,包含:
载台;以及
防沾黏层,设置于该载台,该防沾黏层用以在芯片压合至基板的压合制程中支撑该基板,并以该防沾黏层接触该基板的防焊层。
12.根据权利要求11所述的使用于基板与芯片压合方法的压合装置,其特征在于,该防沾黏层选自于聚四氟乙烯。
13.根据权利要求11所述的使用于基板与芯片压合方法的压合装置,其特征在于,该防沾黏层包含多个第一通道,该多个第一通道具有多个开口,该多个开口位于该防沾黏层的支撑表面,该支撑表面朝向该防焊层,借由该多个开口吸附该基板以使该防焊层接触该防沾黏层,并使该基板暂时性地固定于该防沾黏层。
14.根据权利要求13所述的使用于基板与芯片压合方法的压合装置,其特征在于,该第一通道包含多个沟槽,该开口为该沟槽的开口。
15.根据权利要求14所述的使用于基板与芯片压合方法的压合装置,其特征在于,该多个沟槽为凹槽,该多个沟槽未贯穿该防沾黏层,该第一通道包含多个导通孔,该多个导通孔连通未贯穿该防沾黏层的该多个沟槽。
16.根据权利要求14所述的使用于基板与芯片压合方法的压合装置,其特征在于,该多个沟槽贯穿该防沾黏层。
17.根据权利要求14所述的使用于基板与芯片压合方法的压合装置,其特征在于,该多个沟槽相互连通,并使该防沾黏层区隔成为多个区块。
18.根据权利要求13所述的使用于基板与芯片压合方法的压合装置,其特征在于,该载台具有多个第二通道,各该第二通道连通各该第一通道。
19.根据权利要求11所述的使用于基板与芯片压合方法的压合装置,其特征在于,在该防沾黏层设置于该载台前,预先粗糙化该载台的表面,该防沾黏层设置于经粗糙化的该表面,以使该防沾黏层可固定附着于该载台。
20.根据权利要求11所述的使用于基板与芯片压合方法的压合装置,其特征在于,该防沾黏层设置于该载台的方法选自于网印、喷雾涂布滚轮涂布或薄膜贴附。
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KR102204147B1 (ko) | 2021-01-18 |
TWI669794B (zh) | 2019-08-21 |
JP6716728B2 (ja) | 2020-07-01 |
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