TWI653739B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI653739B
TWI653739B TW104111011A TW104111011A TWI653739B TW I653739 B TWI653739 B TW I653739B TW 104111011 A TW104111011 A TW 104111011A TW 104111011 A TW104111011 A TW 104111011A TW I653739 B TWI653739 B TW I653739B
Authority
TW
Taiwan
Prior art keywords
potential
region
semiconductor substrate
type
diffusion layer
Prior art date
Application number
TW104111011A
Other languages
English (en)
Other versions
TW201601287A (zh
Inventor
古田智之
Original Assignee
日商精工愛普生股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商精工愛普生股份有限公司 filed Critical 日商精工愛普生股份有限公司
Publication of TW201601287A publication Critical patent/TW201601287A/zh
Application granted granted Critical
Publication of TWI653739B publication Critical patent/TWI653739B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

本半導體裝置具備：第1導電型半導體基板；第2導電型嵌入式擴散層，其設置於半導體基板內；第2導電型雜質擴散區域，其係於半導體基板內，連接於嵌入式擴散層並與嵌入式擴散層一併包圍半導體基板之第1區域，藉此使半導體基板之第1區域與第2區域分離；第2導電型之第1井及第2井，其等係於半導體基板之第1區域內，至少介隔第1導電型半導體層而設置於嵌入式擴散層上；及複數個電晶體，其等設置於半導體基板。

Description

半導體裝置
本發明係關於一種將複數個MOS(Metal Oxide Semiconductor，金屬氧化物半導體)場效電晶體或LD(Lateral Double-diffused，橫向擴散)MOS場效電晶體混載於同一基板上之半導體裝置等。
一般而言，於將複數個MOS場效電晶體或LDMOS場效電晶體混載於同一半導體基板而構成電子電路之情形時，將第1導電型半導體基板之電位設為基準電位(0V)，對形成電晶體之第2導電型井，供給相對於基準電位之正電位或負電位。
例如，於使用P型半導體基板之情形時，將P型半導體基板之電位設為基準電位(0V)，藉由對設置於P型半導體基板內之N井供給正電位，PN接面被施加逆向偏壓。藉此，可使電流不會自P型半導體基板朝向N井流動。又，即便於在P型半導體基板內設置複數個N井之情形時，亦可對複數個N井供給各不相同之電位，但必須將其等之電位設為正電位。
作為相關技術，於專利文獻1中，揭示有具有SRAM(Static Random Access Memory，靜態隨機存取記憶體)之半導體積體電路裝置，該SRAM能設置α射線軟性誤差對策之嵌入式雜質層，並且減少每個單元之接地用分接頭。該半導體積體電路裝置具備：第2導電型嵌入式雜質層，其作為中間層而配設於第1導電型半導體基板；第1導 電型井區域，其不與嵌入式雜質層接觸而以特定深度設置於半導體基板；第2導電型井區域，其不與嵌入式雜質層接觸而以特定深度設置於半導體基板；及積體電路元件，其於第1導電型井區域及第2導電型井區域之各者設置元件並使其等相互關聯。
若參照專利文獻1之圖1，則對P井區域及N井區域與N型嵌入式雜質層之間之P型半導體基板，供給接地電位VSS。藉此，可於設置有軟性誤差對策之N型嵌入式雜質層之狀態下，不使P井區域浮動。另一方面，對N井區域，供給正電源電位VDD。因此，形成於P井區域及N井區域之電晶體於接地電位VSS與電源電位VDD之間之電壓範圍內動作。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2003-60071號公報(段落0018-0020，圖1)
然而，根據電子電路，存在能使用於基準電位以上之電壓範圍內動作之電晶體、與於基準電位以下之電壓範圍內動作之電晶體兩者之情況。於此種情形時，期望將兩種電晶體混載於同一半導體基板而構成電子電路。
因此，鑒於上述方面，本發明之目的之一係提供一種將於基準電位以上之電壓範圍內動作之電晶體、與於基準電位以下之電壓範圍內動作之電晶體兩者混載於同一半導體基板而成之半導體裝置等。
為了解決以上問題，本發明之一態樣之半導體裝置具備：第1導電型半導體基板；第2導電型嵌入式擴散層，其設置於半導體基板 內；第2導電型雜質擴散區域，其係於半導體基板內，連接於嵌入式擴散層並與嵌入式擴散層一併包圍半導體基板之第1區域，藉此使半導體基板之第1區域與第2區域分離；第2導電型之第1井及第2井，其等係於半導體基板之第1區域內，至少介隔第1導電型半導體層而設置於嵌入式擴散層上；及複數個電晶體，其等設置於半導體基板。於本案中，可為第1導電型為P型、第2導電型為N型，亦可為第1導電型為N型、第2導電型為P型。
根據本發明之一態樣，於第1導電型半導體基板內，設置包圍半導體基板之第1區域之第2導電型嵌入式擴散層及雜質擴散區域，藉此可使半導體基板之第1區域與第2區域電性分離。因此，可於半導體基板之第1區域設定與第2區域之電位不同之電位，或者可擴大於第1區域內之第1及第2N井所能設定之電位之範圍。其結果為，能將於基準電位以上之電壓範圍內動作之電晶體、與於基準電位以下之電壓範圍內動作之電晶體兩者混載於同一半導體基板。
此處，亦可使半導體裝置進而具備：第1電源端子，其對半導體基板之第1區域供給電位；及第2電源端子，其對半導體基板之第2區域供給電位。藉此，可自半導體裝置之外部經由第1及第2電源端子而對半導體基板之第1及第2區域供給不同之電位。
於該情形時，亦可使半導體裝置進而具備：第3電源端子，其對雜質擴散區域及嵌入式擴散層供給電位；或第4電源端子，其對第1或第2井供給電位。藉此，可自半導體裝置之外部經由第3或第4電源端子，對雜質擴散區域及嵌入式擴散層、或者第1或第2井供給所需之電位。
又，亦可使半導體裝置進而具備第1導電型之第3井，該第1導電型之第3井係於半導體基板之第1區域內，至少介隔第1導電型半導體層而設置於嵌入式擴散層上。可藉由例如交替地配置第2導電型井與 第1導電型井，而減小設置於該等井之複數個電晶體間之漏電流。
於該情形時，亦可使第1電源端子電性連接於第3井，而自第1電源端子經由第3井而對半導體基板之第1區域供給電位。藉此，可省略電性連接於半導體基板之第1區域之配線。
於以上，亦可對P型半導體基板之第2區域供給基準電位，對N型雜質擴散區域及嵌入式擴散層供給基準電位以上之第1電位，對P型半導體基板之第1區域供給低於第1電位之第2電位，對N型第1及第2井供給高於第2電位之電位。藉此，可使半導體基板內之PN接面被施加逆向偏壓，而不使多餘之電流於PN接面流動。
於該情形時，亦可對P型半導體基板之第1區域供給低於基準電位之第2電位。藉此，可將於基準電位以下之電壓範圍內動作之N通道電晶體設置於第1區域，並且將於基準電位以上之電壓範圍內動作之N通道電晶體設置於第2區域。
又，亦可對N型之第1井供給高於基準電位之電位，對N型之第2井供給基準電位以下之電位。藉此，可將於基準電位以上之電壓範圍內動作之P通道電晶體設置於第1N井，並且將於基準電位以下之電壓範圍內動作之P通道電晶體設置於第2N井。
於以上，亦可使半導體基板之第1區域內之第1導電型半導體層包含第1導電型之第2嵌入式擴散層，該第1導電型之第2嵌入式擴散層設置於嵌入式擴散層上，且至少與第1及第2井相接。藉此，可減小於半導體基板之第1區域內流動之漏電流。
10‧‧‧半導體基板
10a‧‧‧半導體基板之第1區域
10b‧‧‧半導體基板之第2區域
11‧‧‧基底基板
12‧‧‧磊晶層
12a‧‧‧P型接觸區域
12b‧‧‧P型接觸區域
20‧‧‧N型嵌入式擴散層
30‧‧‧N型雜質擴散區域(N插栓)
30a‧‧‧N型接觸區域
41‧‧‧N井
41a‧‧‧N型接觸區域
42‧‧‧N井
42a‧‧‧N型接觸區域
43‧‧‧N井
44‧‧‧N井
45‧‧‧N井
46‧‧‧N井
47‧‧‧N井
48‧‧‧N井
51~53‧‧‧P井
51a‧‧‧P型接觸區域
60‧‧‧P型嵌入式擴散層
70‧‧‧P型雜質擴散區域(P插栓)
70a‧‧‧P型接觸區域
80‧‧‧P型嵌入式擴散層
90‧‧‧P型雜質擴散區域(P插栓)
90a‧‧‧P型接觸區域
B‧‧‧本體區域
D‧‧‧汲極區域
G‧‧‧閘極電極
QL1‧‧‧N通道LDMOS場效電晶體
QL2‧‧‧N通道LDMOS場效電晶體
QL3‧‧‧N通道LDMOS場效電晶體
QL4‧‧‧N通道LDMOS場效電晶體
QN1‧‧‧N通道MOS場效電晶體
QN2‧‧‧N通道MOS場效電晶體
QN3‧‧‧N通道MOS場效電晶體
QP1‧‧‧P通道MOS場效電晶體
QP2‧‧‧P通道MOS場效電晶體
QP3‧‧‧P通道MOS場效電晶體
QP4‧‧‧P通道MOS場效電晶體
S‧‧‧源極區域
T0~T27‧‧‧電源端子
TB1‧‧‧本體端子
TB2‧‧‧本體端子
TB3‧‧‧本體端子
TB4‧‧‧本體端子
圖1係模式性地表示本發明之第1實施形態之半導體裝置之主要部分之剖視圖。
圖2係模式性地表示本發明之第2實施形態之半導體裝置之主要部分之剖視圖。
圖3(a)、(b)係模式性地表示本發明之第3實施形態之半導體裝置之第1部分之圖。
圖4(a)、(b)係模式性地表示本發明之第3實施形態之半導體裝置之第2部分之圖。
以下，一面參照圖式，一面對本發明之實施形態詳細地進行說明。再者，對同一構成要素標註同一參照編號，並省略重複之說明。
<第1實施形態>
圖1係模式性地表示本發明之第1實施形態之半導體裝置之主要部分之剖視圖。如圖1所示，該半導體裝置包括：P型半導體基板10；N型嵌入式擴散層20，其設置於半導體基板10內；N型雜質擴散區域(N插栓)30；N井41及42；及複數個電晶體QN1、QN2、QP1、QP2，其等設置於半導體基板10。
例如，半導體基板10包括：P型基底基板11，其向表層部注入N型雜質而設置有N型嵌入式擴散層20；及P型磊晶層12，其係藉由在基底基板11上使P型半導體磊晶成長而設置。此處，磊晶層12成為形成電晶體等元件之元件形成區域。作為基底基板11及磊晶層12之材料，可使用例如矽(Si)。或者，亦可藉由在半導體基板10內形成深井，而於半導體基板10內之特定之深度配設嵌入式擴散層20，從而省略磊晶層12。
N插栓30係於半導體基板10內，連接於N型嵌入式擴散層20並與N型嵌入式擴散層20一併包圍半導體基板之第1區域10a，藉此使半導體基板之第1區域10a與第2區域10b分離。N井41及42於半導體基板之第1區域10a內，至少介隔P型半導體層而設置於N型嵌入式擴散層20上。
於半導體基板之第1區域10a，設置有N通道MOS場效電晶體 QN1，於半導體基板之第2區域10b，設置有N通道MOS場效電晶體QN2。電晶體QN1及QN2之各者包括：N型之源極區域(S)及汲極區域(D)，其等設置於半導體基板內；及閘極電極(G)，其介隔閘極絕緣膜而設置於半導體基板上。
於N井41，設置有P通道MOS場效電晶體QP1，於N井42，設置有P通道MOS場效電晶體QP2。電晶體QP1及QP2之各者包括：P型之源極區域(S)及汲極區域(D)，其等設置於N井內；及閘極電極(G)，其介隔閘極絕緣膜而設置於N井上。
又，半導體裝置亦可包括電源端子(焊墊)T1~T5。電源端子T1電性連接於被設置在半導體基板之第1區域10a內之P型接觸區域12a，對半導體基板之第1區域10a供給電位。電源端子T2電性連接於被設置在半導體基板之第2區域10b內之P型接觸區域12b，對半導體基板之第2區域10b供給電位。藉此，可自半導體裝置之外部經由電源端子T1及T2，而對半導體基板之第1區域10a及第2區域10b供給不同之電位。
電源端子T3電性連接於被設置在N插栓30內之N型接觸區域30a，對N插栓30及N型嵌入式擴散層20供給電位。藉此，可自半導體裝置之外部經由電源端子T3，而對N插栓30及N型嵌入式擴散層20供給所需之電位。再者，於供給至N插栓30之電位與供給至半導體基板之第2區域10b之電位相同之情形時，亦可藉由將接觸區域30a電性連接於電源端子T2，而省略電源端子T3。
電源端子T4電性連接於被設置在N井41內之N型接觸區域41a，對N井41供給電位。又，電源端子T5電性連接於被設置在N井42內之N型接觸區域42a，對N井42供給電位。
藉此，可自半導體裝置之外部經由電源端子T4及T5，而對N井41及42供給所需之電位。再者，於供給至N井41或N井42之電位與供給至N插栓30之電位相同之情形時，亦可藉由使接觸區域41a或42a電性 連接於電源端子T3，而省略電源端子T4或T5。
其次，對供給至圖1所示之半導體裝置之各部之電位之一例進行說明。藉由對電源端子T2施加基準電位(0V)，而自電源端子T2對半導體基板之第2區域10b供給基準電位。藉由對電源端子T3施加基準電位以上之第1電位(例如+5V)，而自電源端子T3對N插栓30及N型嵌入式擴散層20供給第1電位。藉由對電源端子T1施加低於第1電位之第2電位(例如-5V)，而自電源端子T1對半導體基板之第1區域10a供給第2電位。
又，藉由對電源端子T4施加高於第2電位之第3電位(例如+5V)，而自電源端子T4對N井41供給第3電位。藉由對電源端子T5施加高於第2電位之第4電位(例如0V)，而自電源端子T5對N井42供給第4電位。藉此，可使半導體基板內之PN接面被施加逆向偏壓，而不使多餘之電流於PN接面流動。
於上述例中，對半導體基板之第1區域10a供給低於基準電位之第2電位(-5V)。於該情形時，可對設置於半導體基板之第1區域10a之電晶體QN1之源極及汲極施加第2電位(-5V)以上之電位。例如，電晶體QN1於基準電位以下之0V~-5V之電壓範圍內動作。
又，可對設置於被供給基準電位(0V)之半導體基板之第2區域10b之電晶體QN2之源極及汲極施加基準電位(0V)以上之電位。例如，電晶體QN2於基準電位以上之0V~+5V之電壓範圍內動作。
於上述例中，對N井41供給高於基準電位之第3電位(+5V)。於該情形時，可對設置於N井41之電晶體QP1之源極及汲極施加第3電位(+5V)以下之電位。例如，電晶體QP1於基準電位以上之0V~+5V之電壓範圍內動作。
又，對N井42供給基準電位以下之第4電位(0V)。於該情形時，可對設置於N井42之電晶體QP2之源極及汲極施加第4電位(0V)以下之 電位。例如，電晶體QP2於基準電位以下之0V~-5V之電壓範圍內動作。
根據本發明之第1實施形態，於P型半導體基板10內，設置包圍半導體基板之第1區域10a之N型嵌入式擴散層20及N插栓30，藉此使半導體基板之第1區域10a與第2區域10b電性分離。因此，可於半導體基板之第1區域10a設定與第2區域10b之電位不同之電位，或者可擴大於第1區域10a內之N井41及42所能設定之電位之範圍。其結果為，可將於基準電位以上之電壓範圍內動作之電晶體、與於基準電位以下之電壓範圍內動作之電晶體兩者混載於同一半導體基板。再者，亦可於形成電晶體QN1及/或QN2之區域設置P井，而提高電晶體之閾值電壓等特性之控制性。
<第2實施形態>
圖2係模式性地表示本發明之第2實施形態之半導體裝置之主要部分之剖視圖。如圖2所示，該半導體裝置進而具備P井51，該P井51於半導體基板之第1區域10a內，至少介隔P型半導體層而設置於N型嵌入式擴散層20上。藉此，電晶體QN1設置於P井51。藉由例如交替地配置N井與P井，可減小設置於該等井之複數個電晶體間之漏電流。
於設置電性連接於被設置在P井51內之P型接觸區域51a之電源端子T0之情形時，若對電源端子T0施加電位，則自電源端子T0經由P井51而對半導體基板之第1區域10a供給電位。因此，亦可省略對半導體基板之第1區域10a直接供給電位之電源端子T1(圖1)。藉此，可省略電性連接於半導體基板之第1區域10a之配線。另一方面，於不設置電源端子T0之情形時，自電源端子T1經由半導體基板之第1區域10a而對P井51供給電位。
又，如圖2所示，亦可使半導體基板之第1區域10a內之P型半導 體層包含P型嵌入式擴散層60，該P型嵌入式擴散層60設置於N型嵌入式擴散層20上且至少與N井41及42相接。藉此，可減小於半導體基板之第1區域10a內流動之漏電流。再者，P型嵌入式擴散層60還可亦配設至較N型嵌入式擴散層20深之區域。
P型嵌入式擴散層60亦與P井51相接。因此，若對電源端子T0施加電位，則自電源端子T0經由P井51而對P型嵌入式擴散層60供給電位。另一方面，亦可設置連接於P型嵌入式擴散層60之P型雜質擴散區域(P插栓)70，並將電源端子T1電性連接於被設置在P插栓70內之P型接觸區域70a。於該情形時，若對電源端子T1施加電位，則自電源端子T1經由P插栓70及P型嵌入式擴散層60而對P井51供給電位。因此，亦可省略對P井51直接供給電位之電源端子T0。
<第3實施形態>
於本發明之第3實施形態之半導體裝置中，於半導體裝置之第1部分設置複數個MOS場效電晶體，於半導體裝置之第2部分設置複數個LDMOS場效電晶體。
圖3係模式性地表示本發明之第3實施形態之半導體裝置之第1部分之圖。圖3(a)係表示半導體裝置之第1部分之俯視圖，圖3(b)係表示半導體裝置之第1部分之剖視圖。於第3實施形態中亦與第1及第2實施形態同樣地，於半導體基板10內，使N型嵌入式擴散層20及N插栓30包圍半導體基板之第1區域10a，藉此使半導體基板之第1區域10a與第2區域10b分離。
該半導體裝置亦可於半導體基板之第1區域10a包含：P型嵌入式擴散層60，其設置於N型嵌入式擴散層20上且與N井41~44及P井51~53相接；及P型雜質擴散區域(P插栓)70，其連接於P型嵌入式擴散層60。
又，半導體裝置亦可於半導體基板之第2區域10b包括：P型嵌入 式擴散層80，其沿N插栓30之外周而設置；及P型雜質擴散區域(P插栓)90，其連接於P型嵌入式擴散層80。藉此，於在半導體基板10內設置複數個N型嵌入式擴散層20之情形時，可減小該等N型嵌入式擴散層20間之漏電流。
該半導體裝置於半導體基板之第1區域10a包括：N井41~44及P井51~53，其等係介隔P型嵌入式擴散層60而設置於N型嵌入式擴散層20上；P通道MOS場效電晶體QP1~QP4，其等分別設置於N井41~44；N通道MOS場效電晶體QN1~QN3，其等分別設置於P井51~53；及電源端子T11~T17。
電源端子T11電性連接於被設置在P插栓70內之P型接觸區域70a，對包含P插栓70及P型嵌入式擴散層60之半導體基板之第1區域10a供給電位。供給至P型嵌入式擴散層60之電位亦被供給至P井51~53。電源端子T12電性連接於被設置在P插栓90之P型接觸區域90a，對包含P插栓90及P型嵌入式擴散層80之半導體基板之第2區域10b供給電位。
電源端子T13電性連接於被設置在N插栓30內之N型接觸區域30a，對N插栓30及N型嵌入式擴散層20供給電位。電源端子T14~T17分別電性連接於被設置在N井41~44內之N型接觸區域，對N井41~44供給電位。
其次，對供給至圖3所示之半導體裝置之各部之電位之一例進行說明。藉由對電源端子T12施加基準電位(0V)，而自電源端子T12對半導體基板之第2區域10b供給基準電位。藉由對電源端子T13施加基準電位以上之第1電位(例如+2V)，而自電源端子T13對N插栓30及N型嵌入式擴散層20供給第1電位。藉由對電源端子T11施加低於第1電位之第2電位(例如-8V)，而自電源端子T11對半導體基板之第1區域10a供給第2電位。第2電位亦被供給至P井51~53。
又，藉由對電源端子T14施加高於第2電位之第3電位(例如+5V)，而自電源端子T14對N井41供給第3電位。於該情形時，可對設置於N井41之電晶體QP1之源極及汲極施加第3電位(+5V)以下之電位。例如，電晶體QP1於基準電位以上之0V~+5V之電壓範圍內動作。
藉由對電源端子T15施加高於第2電位之第4電位(例如+3V)，而自電源端子T15對N井42供給第4電位。於該情形時，可對設置於N井42之電晶體QP2之源極及汲極，施加第4電位(+3V)以下之電位。例如，電晶體QP2於基準電位以上之0V~+3V之電壓範圍內動作。
藉由對電源端子T16施加第5電位(例如-5V)，而自電源端子T16對N井43供給第5電位。於該情形時，可對設置於N井43之電晶體QP3之源極及汲極，施加第5電位(-5V)以下之電位。例如，電晶體QP3於基準電位以下之-5V~-8V之電壓範圍內動作。
藉由對電源端子T17施加第6電位(例如-3V)，而自電源端子T17對N井44供給第6電位。於該情形時，可對設置於N井44之電晶體QP4之源極及汲極，施加第6電位(-3V)以下之電位。例如，電晶體QP4於基準電位以下之-3V~-8V之電壓範圍內動作。
又，自電源端子T11對P井51~53供給低於第1電位之第2電位(例如-8V)。於該情形時，可對設置於P井51~53之電晶體QN1~QN3之源極及汲極施加第2電位(-8V)以上之電位。例如，電晶體QN1於基準電位以上之0V~+5V之電壓範圍內動作，電晶體QN2於基準電位以上之0V~+3V之電壓範圍內動作。又，電晶體QN3於基準電位以下之-5V~-8V之電壓範圍內動作。再者，電晶體QN1~QN3之動作電壓範圍可為第2電位(-8V)以上，亦可為-3V~-8V。
圖4係模式性地表示本發明之第3實施形態之半導體裝置之第2部分之圖。圖4(a)係表示半導體裝置之第2部分之俯視圖，圖4(b)係表示半導體裝置之第2部分之剖視圖。於半導體裝置之第2部分，亦與第1 部分同樣地，於半導體基板10內，N型嵌入式擴散層20及N插栓30包圍半導體基板之第1區域10a，藉此使半導體基板之第1區域10a與第2區域10b分離。
該半導體裝置亦可於半導體基板之第1區域10a包括：P型嵌入式擴散層60，其設置於N型嵌入式擴散層20上且與N井45~48相接；及P型雜質擴散區域(P插栓)70，其連接於P型嵌入式擴散層60。又，半導體裝置亦可於半導體基板之第2區域10b包括：P型嵌入式擴散層80，其沿N插栓30之外周而設置；及P型雜質擴散區域(P插栓)90，其連接於P型嵌入式擴散層80。
該半導體裝置於半導體基板之第1區域10a內包括：N井45~48，其等介隔P型嵌入式擴散層60而設置於N型嵌入式擴散層20上；N通道LDMOS場效電晶體QL1~QL4，其等分別設置於N井45~48；電源端子T21~T27；及本體端子TB1~TB4。
電晶體QL1~QL4之各者包括：N型汲極區域(D)及P型本體區域(B)，其等設置於N井內；N型源極區域(S)，其設置於本體區域(B)內；閘極絕緣膜及場氧化膜(亦被稱為「偏移絕緣膜」)，其等設置於N井上；及閘極電極(G)，其設置於閘極絕緣膜及場氧化膜之表面之一部分。
場氧化膜之膜厚大於閘極絕緣膜之膜厚，於場氧化膜之表面上之接近於汲極區域(D)之區域，未設置閘極電極(G)。藉此，汲極區域(D)與閘極電極(G)之間之電場強度被緩和，因此可提高電晶體之耐壓。
電源端子T21電性連接於被設置在P插栓70內之P型接觸區域70a，對包含P插栓70及P型嵌入式擴散層60之半導體基板之第1區域10a供給電位。電源端子T22電性連接於被設置在P插栓90之P型接觸區域90a，對包含P插栓90及P型嵌入式擴散層80之半導體基板之第2區 域10b供給電位。電源端子T23電性連接於被設置在N插栓30內之N型接觸區域30a，對N插栓30及N型嵌入式擴散層20供給電位。
電源端子T24~T27分別電性連接於被設置在N井45~48之電晶體QL1~QL4之汲極區域(D)，對電晶體QL1~QL4之汲極區域(D)供給電位。本體端子TB1~TB4分別電性連接於被設置在電晶體QL1~QL4之本體區域(B)內之P型接觸區域，對電晶體QL1~QL4之本體區域(B)供給電位。
其次，對供給至圖4所示之半導體裝置之各部之電位之一例進行說明。藉由對電源端子T22施加基準電位(0V)，而自電源端子T22對半導體基板之第2區域10b供給基準電位。藉由對電源端子T23施加基準電位以上之第1電位(例如+2V)，而自電源端子T23對N插栓30及N型嵌入式擴散層20供給第1電位。藉由對電源端子T21施加低於第1電位之第2電位(例如-58V)，而自電源端子T21對半導體基板之第1區域10a供給第2電位。
藉由對電源端子T24施加高於第2電位之第3電位(例如+50V以下)，而自電源端子T24對電晶體QL1之汲極及N井45供給第3電位。對電晶體QL1之本體端子TB1，供給例如基準電位(0V)。於該情形時，電晶體QL1於基準電位以上之0V~+50V之電壓範圍內動作。
藉由對電源端子T25施加高於第2電位之第4電位(例如+20V)，而自電源端子T25對電晶體QL2之汲極及N井46供給第4電位。對電晶體QL2之本體端子TB2，供給例如基準電位(0V)。於該情形時，電晶體QL2於基準電位以上之0V~+20V之電壓範圍內動作。
藉由對電源端子T26施加高於第2電位之第5電位(例如-50V)，而自電源端子T26對電晶體QL3之汲極及N井47供給第5電位。對電晶體QL3之本體端子TB3，供給例如第2電位(-58V)。於該情形時，電晶體QL3於基準電位以下之-50V~-58V之電壓範圍內動作。
藉由對電源端子T27施加高於第2電位之第6電位(例如-20V)，而自電源端子T27對電晶體QL4之汲極及N井48供給第6電位。對電晶體QL4之本體端子TB4，供給例如第2電位(-58V)。於該情形時，電晶體QL4於基準電位以下之-20V~-58V之電壓範圍內動作。
於以上實施形態中，對使用P型半導體基板之例進行了說明，但亦可使用N型半導體基板。進而，本發明不僅可應用於具備N通道之LDMOS場效電晶體之半導體裝置，亦可應用於具備P通道之LDMOS場效電晶體之半導體裝置。如此，本發明並非受以上所說明之實施形態限定者，可由具有該技術領域內之通常知識者於本發明之技術性思想內進行較多變化。

Claims (9)

  1. 一種半導體裝置，其具備：第1導電型半導體基板；第2導電型之第1嵌入式擴散層，其設置於上述半導體基板內；第2導電型之第1雜質擴散區域，其係於上述半導體基板內，連接於上述第1嵌入式擴散層並與上述第1嵌入式擴散層一併包圍上述半導體基板之第1區域，藉此使上述半導體基板之第1區域與第2區域分離；第1導電型之第2嵌入式擴散層，其係於上述半導體基板內，設置於上述第1嵌入式擴散層上；第1導電型之第2雜質擴散區域，其係於上述半導體基板之第1區域內，連接於上述第2嵌入式擴散層；第1導電型之複數個第1井及第2導電型之複數個第2井，其等係於上述半導體基板之第1區域內，與上述第2嵌入式擴散層相接而設置；電源端子，其電性連接於上述第2雜質擴散區域，經由上述第2雜質擴散區域及上述第2嵌入式擴散層而對上述複數個第1井供給電位；及複數個電晶體，其等設置於上述複數個第1井及上述複數個第2井。
  2. 如請求項1之半導體裝置，其進而包括第2電源端子，其對上述半導體基板之第2區域供給電位。
  3. 如請求項2之半導體裝置，其進而包括第3電源端子，其對上述第1雜質擴散區域及上述第1嵌入式擴散層供給電位。
  4. 如請求項2之半導體裝置，其進而包括第4電源端子，其對上述複數個第2井中之至少一者供給電位。
  5. 如請求項3之半導體裝置，其進而包括第4電源端子，其對上述複數個第2井中之至少一者供給電位。
  6. 如請求項1至5中任一項之半導體裝置，其中上述第1導電型為P型，對上述半導體基板之第2區域供給基準電位；上述第2導電型為N型，對上述第1雜質擴散區域及上述第1嵌入式擴散層供給基準電位以上之第1電位；對上述複數個第1井供給低於第1電位之第2電位；對上述複數個第2井供給高於第2電位之電位。
  7. 如請求項6之半導體裝置，其中上述複數個第1井包括被供給低於基準電位之電位之井。
  8. 如請求項6之半導體裝置，其中上述複數個第2井包括被供給高於基準電位之電位之井、及被供給基準電位以下之電位之井。
  9. 如請求項7之半導體裝置，其中上述複數個第2井包括被供給高於基準電位之電位之井、及被供給基準電位以下之電位之井。
TW104111011A 2014-04-07 2015-04-02 半導體裝置 TWI653739B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-078333 2014-04-07
JP2014078333A JP6364898B2 (ja) 2014-04-07 2014-04-07 半導体装置

Publications (2)

Publication Number Publication Date
TW201601287A TW201601287A (zh) 2016-01-01
TWI653739B true TWI653739B (zh) 2019-03-11

Family

ID=54210430

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104111011A TWI653739B (zh) 2014-04-07 2015-04-02 半導體裝置

Country Status (4)

Country Link
US (1) US9412738B2 (zh)
JP (1) JP6364898B2 (zh)
CN (1) CN104979349B (zh)
TW (1) TWI653739B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6641958B2 (ja) 2015-12-11 2020-02-05 セイコーエプソン株式会社 半導体装置及びその製造方法
JP6645280B2 (ja) * 2016-03-14 2020-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法
JP6843799B2 (ja) * 2018-06-11 2021-03-17 三菱電機株式会社 半導体装置及び電力変換システム
JP7030637B2 (ja) * 2018-07-23 2022-03-07 三菱電機株式会社 半導体装置の製造方法
JP7143734B2 (ja) 2018-11-15 2022-09-29 富士電機株式会社 半導体集積回路
JP2020108087A (ja) 2018-12-28 2020-07-09 セイコーエプソン株式会社 振動デバイス、電子機器および移動体
US11562995B2 (en) 2019-04-11 2023-01-24 Fuji Electric Co., Ltd. Semiconductor integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140496A (ja) 2004-11-12 2006-06-01 Taiwan Semiconductor Manufacturing Co Ltd 多種動作電圧を有する集積回路絶縁用半導体構造
JP2006179864A (ja) 2004-12-21 2006-07-06 Taiwan Semiconductor Manufacturing Co Ltd 半導体デバイス

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335837A (ja) 1994-06-03 1995-12-22 Hitachi Ltd 半導体装置および論理回路
JPH0955483A (ja) 1995-06-09 1997-02-25 Mitsubishi Electric Corp 半導体記憶装置
JPH11251447A (ja) * 1998-02-27 1999-09-17 Nippon Foundry Inc 半導体装置及びその製造方法
JP2003060071A (ja) 2001-08-08 2003-02-28 Seiko Epson Corp 半導体集積回路装置
JP2003197790A (ja) 2001-12-28 2003-07-11 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2004247400A (ja) * 2003-02-12 2004-09-02 Renesas Technology Corp 半導体装置
JP2008270367A (ja) 2007-04-17 2008-11-06 Denso Corp 半導体装置
CN203071073U (zh) * 2012-12-18 2013-07-17 江南大学 一种纵向npn触发的高维持电压的高压esd保护器件
JP6070333B2 (ja) * 2013-03-25 2017-02-01 セイコーエプソン株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140496A (ja) 2004-11-12 2006-06-01 Taiwan Semiconductor Manufacturing Co Ltd 多種動作電圧を有する集積回路絶縁用半導体構造
JP2006179864A (ja) 2004-12-21 2006-07-06 Taiwan Semiconductor Manufacturing Co Ltd 半導体デバイス

Also Published As

Publication number Publication date
JP6364898B2 (ja) 2018-08-01
US20150287719A1 (en) 2015-10-08
US9412738B2 (en) 2016-08-09
CN104979349B (zh) 2019-07-16
CN104979349A (zh) 2015-10-14
TW201601287A (zh) 2016-01-01
JP2015201500A (ja) 2015-11-12

Similar Documents

Publication Publication Date Title
TWI653739B (zh) 半導體裝置
US8338864B2 (en) Semiconductor device
US8324707B2 (en) Power amplifier
JP2016508671A5 (zh)
CN107611166B (zh) 用于显示驱动器ic结构的半导体器件
JP2010016177A (ja) 静電気放電保護素子
US20120061761A1 (en) Semiconductor integrated circuit device and manufacturing method for semiconductor integrated circuit devices
US7868423B2 (en) Optimized device isolation
US9899471B2 (en) Compact CMOS device isolation
US10121891B2 (en) P-N bimodal transistors
JP4864344B2 (ja) 半導体装置
US10192885B2 (en) Semiconductor on insulator (SOI) block with a guard ring
US8110454B2 (en) Methods of forming drain extended transistors
US10381347B2 (en) Semiconductor apparatus
JP5241109B2 (ja) 半導体集積回路装置
TWI780477B (zh) 開關裝置
US11616506B2 (en) High speed buffer circuit
US20060081940A1 (en) Semiconductor device
JP7116275B2 (ja) 堅牢なサブスレッショルド動作を備えるｍｏｓｆｅｔトランジスタ
US20130015516A1 (en) Asymmetrical non-volatile memory cell and method for fabricating the same
US9385184B2 (en) Active device and semiconductor device with the same
US20210167060A1 (en) Protection circuit
US20070290291A1 (en) High voltage devices
TW201539713A (zh) 半導體裝置及其製造方法