TWI780477B - 開關裝置 - Google Patents

開關裝置 Download PDF

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TWI780477B
TWI780477B TW109130710A TW109130710A TWI780477B TW I780477 B TWI780477 B TW I780477B TW 109130710 A TW109130710 A TW 109130710A TW 109130710 A TW109130710 A TW 109130710A TW I780477 B TWI780477 B TW I780477B
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gate structure
type well
well
voltage
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陳志欣
王世辰
賴宗沐
景文澔
羅俊元
張緯宸
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力旺電子股份有限公司
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Abstract

開關裝置包含P型基底、第一閘極結構、第一N型井、淺溝槽隔離結構、第一P型井、第二閘極結構、第一N型摻雜區、第二P型井及第二N型摻雜區。第一N型井形成於P型基底上,且有部分設置在第一閘極結構的下方。淺溝槽隔離結構形成於第一N型井,且設置在第一閘極結構的第一側下方。第一P型井形成於P型基底上,且設置在第一閘極結構下方。第一N型摻雜區形成於P型基底,且設置在第一閘極結構及第二閘極結構之間。第二P型井形成於P型基底,且設置在第二閘極結構下方。第二N型摻雜區形成於第二P型井,且設置在第二閘極結構下方。

Description

開關裝置
本發明是有關於一種開關裝置,特別是一種耐高壓的開關裝置。
由於電子裝置對於低耗能的要求越來越高,因此積體電路的電能規格也被重新規劃成能夠在低壓的環境下操作以減少電能損耗。舉例來說,過去積體電路常見的電壓規格是5V,現在則已降至3.3V或甚至低於2V。在此情況下,積體電路也大多以低壓製程來製造以減少製造成本。
然而,在有些情況下,高壓的操作仍無法避免。舉例來說,快閃記憶體就需要透過高電壓來執行寫入操作及清除操作。在此情況下,低耗能的積體電路中,仍有部分的元件須以高壓製程來製作以承受高壓操作。然而,這樣的做法將導致製程變得複雜,甚至使得良率降低。
本發明的一實施例提供一種開關裝置,開關裝置包含P型基底、第一閘極結構、第一N型井、淺溝槽隔離結構、第一P型井、第二閘極結構、第一N型摻雜區、第二P型井及第二N型摻雜區。
第一N型井形成於P型基底上,且有部分設置在第一閘極結構的第一側下方。淺溝槽隔離結構形成於第一N型井,且有部分設置在第一閘極結構的第 一側下方。第一P型井形成於P型基底上,且設置在第一閘極結構下方。第一N型摻雜區形成於P型基底,且設置在第一閘極結構的第二側及第二閘極結構的第一側之間。第二P型井形成於P型基底,且設置在第二閘極結構下方。第二N型摻雜區形成於第二P型井,且有部分設置在第二閘極結構下方。
本發明的另一實施例提供一種開關裝置,開關裝置包含基底、第一閘極結構、第一井、隔離結構、第二井、第二閘極結構、第一摻雜區及第二摻雜區。
第一井具有第一類型的載子,形成於基底上,且有部分設置在第一閘極結構的第一側下方。第二井具有第二類型的載子,形成於基底,且設置在第一閘極結構及第二閘極結構的下方。第一摻雜區具有第一類型的載子,形成於第二井,且設置在第一閘極結構的第二側及第二閘極結構的第一側。第二摻雜區具有第一類型的載子,形成於第二井,且鄰接於第二閘極結構的第二側。 第一類型的載子及第二類型的載子具有相異的極性。
100、200、300:開關裝置
110:第一電晶體
120:第二電晶體
P-sub:P型基底
NW1、NW2:N型井
PW1、PW2:P型井
G1、G2:閘極結構
ND1、ND2、ND3:N型摻雜區
STI1:淺溝渠隔離結構
VR1:第一參考電壓
VR2:第二參考電壓
VDD:第一操作電壓
VPP:第二操作電壓
VIN:輸入電壓
VOUT:輸出電壓
LPW1、LPW2:輕摻雜P型井
Sub:基底
W1、W2:井
D1、D2、D3:摻雜區
I1:隔離結構
VR3:第三參考電壓
VR4:第四參考電壓
VI1:第一輸入電壓
VI2:第二輸入電壓
第1圖是本發明一實施例的開關裝置的電路圖。
第2圖是本發明一實施例之第1圖的開關裝置結構圖。
第3圖是第2圖的開關裝置在第二狀態時所接收到的電壓示意圖。
第4圖是本發明一實施例的開關裝置的結構圖。
第5圖本發明一實施例的開關裝置的結構圖。
第6圖是第5圖的開關裝置在第二狀態時所接收到的電壓示意圖。
第1圖是本發明一實施例的開關裝置100的電路圖。開關裝置100可包含第一電晶體110及第二電晶體120。
第一電晶體110具有第一端、第二端及控制端。第二電晶體120具有第一端、第二端及控制端,而第二電晶體120的第二端可耦接至第一電晶體110的第一端。
第2圖是本發明一實施例的開關裝置100的結構圖。在有些實施例中,第1圖中的電晶體110及120可以是N型電晶體或P型電晶體,而在第2圖中是以電晶體110及120皆為N型電晶體為例。開關裝置100包含P型基底P-sub、閘極結構G1、N型井NW1、淺溝槽隔離(shallow trench isolation,STI)結構STI1、P型井PW1、閘極結構G2、N型摻雜區ND1、P型井PW2及N型摻雜區ND2。
N型井NW1可形成於P型基底P-sub,且有部分設置於閘極結構G1的第一側下方。淺溝槽隔離結構STI1可形成於N型井NW1,並且可設置在閘極結構G1的第一側下方。P型井PW1可形成於P型基底P-sub,並且可設置在閘極結構G1下方。在有些實施例中,P型井PW1與N型井NW1可互不相接觸。
N型摻雜區ND1可形成於P型基底P-sub,並可設置在閘極結構G1的第二側及閘極結構G2的第一側之間。P型井PW2可形成於P型基底P-sub,並可設置在閘極結構G2下方。N型摻雜區ND2可形成於P型井PW2,並有部分設置於閘極結構G2的下方。
在有些實施例中,N型井NW1可視為第一電晶體110的第二端(或源極/汲極),而閘極結構G1可以視為第一電晶體110的控制端(或閘極)。在第2圖中,開關裝置100還可包含N型摻雜區ND3以作為第一電晶體110的源極的耦接端。N型摻雜區ND3可形成於N型井NW1,並可與淺溝槽隔離結構STI1相鄰接,且未被閘極結構G1所掩蓋。
在此情況下,自第一電晶體110的第二端流入或流出的電流將會因為 淺溝槽隔離結構STI1的阻擋,而採取繞道路徑而沿著N型井NW1行進。由於N型摻雜區ND3的摻雜濃度大於N型井NW1的摻雜濃度,因此N型井NW1的電阻值會大於N型摻雜區ND3的電阻值。在此情況下,N型井NW1可以在第一電晶體110的第二端在形成一段高阻值的路徑,使得第一電晶體110耐受高壓的能力獲得提升。此外,由於N型井NW1可形成於P型基底P-sub,且P型基底P-sub的摻雜濃度小於P型井PW1,因此第一電晶體110也會具有較高的接面崩潰電壓。也就是說,第一電晶體110的汲極-源極崩潰電壓(drain-source breakdown voltage,BVDSS)可被提升。
在有些實施例中,第一電晶體110的第一端(或汲極/源極)及第二電晶體120的第二端(或汲極/源極)可形成於相同的N型摻雜區ND1。此外,N型摻雜區ND2可以視為第二電晶體120的第一端(或汲極/源極),而閘極結構G2則可視為第二電晶體120的控制端(或閘極)。
在第2圖中,開關裝置100還可包含形成於P型基底P-sub的N型井NW2,而N型摻雜區ND1可形成於N型井NW2中。在有些實施例中,N型摻雜區ND1的摻雜濃度可大於N型井NW2的摻雜濃度。在第2圖中,N型井NW2的第一部分可設置在閘極結構G1的下方,而N型井NW2的第二部分可設置在閘極結構G2的下方。由於N型井NW2的摻雜濃度小於N型摻雜區ND1的摻雜濃度,因此N型井NW2及P型基底P-sub之間的接面崩潰電壓較高,進而可以提升第一電晶體110及第二電晶體120的耐壓能力。
在第2圖中,開關裝置100是處在第一狀態。在第一狀態中,N型摻雜區ND2及閘極結構G2可接收第一參考電壓VR1。閘極結構G1可接收第一操作電壓VDD,而N型井NW1可經由N型摻雜區ND3接收第二操作電壓VPP。在有些實施例中,第二操作電壓VPP可大於第一操作電壓VDD,而第一操作電壓VDD可大於第一參考電壓VR1。舉例來說,第二操作電壓VPP可以快閃記憶體執行寫入 操作時所需的高壓,第一操作電壓VDD可以是系統中的常規操作電壓,而第一參考電壓VR1可以是地電壓。此外,P型井PW1及P型井PW2可以接收第二參考電壓VR2,而第二參考電壓VR2可以等於或小於第一參考電壓VR1。
在此情況下。閘極結構G2下方的通道將被截止,亦即第二電晶體120會被截止。在有些實施例中,當開關裝置100的兩端電壓差較大時,第一電晶體110及第二電晶體120就可能會產生閘極引致汲極漏電流(gate-induced drain leakage,GIDL)。舉例來說,在第2圖中,由於N型摻雜區ND3所接收到的第二操作電壓VPP較大,因此若直接對閘極結構G1施加較低的電壓,例如第一參考電壓VR1,來截止第一電晶體110,就可能會產生閘極引致汲極漏電流(gate-induced drain leakage,GIDL)。然而,在此實施例中,閘極結構G1可接收第一操作電壓VDD,而閘極結構G2可接收第一參考電壓VR1,因此可以降低第一電晶體110及第二電晶體120的閘極至汲極電壓,進而也減少了閘極引致汲極漏電流。
第3圖是開關裝置100在第二狀態時所接收到的電壓示意圖。在第3圖中,N型摻雜區ND2可接收輸入電壓VIN,而閘極結構G1及G2可接收第一操作電壓VDD。在有些實施例中,第一操作電壓VDD可大於或等於輸入電壓VIN。如此一來,閘極結構G1及G2下方的通道將被導通,亦即第一電晶體110及第二電晶體120將被導通,而第一電晶體110將可根據輸入電壓VIN而自第二端輸出輸出電壓VOUT。
此外,在有些實施例中,當開關裝置100在第二狀態時,P型井PW1及PW2可接收第二參考電壓VR2。也就是說,第一電晶體110及第二電晶體120的基體端可同樣接收第二參考電壓VR2以減少開關裝置100在第二狀態下產生的漏電流。
在第1圖中,N型井NW1可直接形成於P型基底P-sub,然而,在有些 其他實施例中,N型井NW1也可形成於輕摻雜P型井中。
第4圖是本發明一實施例的開關裝置200的結構圖。開關裝置200與開關裝置100可具有相似的結構,並可根據相同的原理操作。然而,開關裝置200還可包含輕摻雜P型井LPW1及LPW2。輕摻雜P型井LPW1可形成於P型基底P-sub,而N型井NW1可形成於輕摻雜P型井LPW1。此外,輕摻雜P型井LPW2可形成於P型基底P-sub,而N型井NW2可形成於輕摻雜P型井LPW2。
在有些實施例中,輕摻雜P型井LPW1的摻雜濃度可小於P型井PW1的摻雜濃度。此外,輕摻雜P型井LPW1可具有摻雜濃度梯度。舉例來說,輕摻雜P型井LPW1的摻雜濃度可自與P型基底P-sub的交界處至與N型井NW1的交界處遞減,因此輕摻雜P型井LPW1在靠近N型井NW1的部分會具有較低的摻雜濃度。
相似地,輕摻雜P型井LPW2的摻雜濃度可小於P型井PW2的摻雜濃度。此外,輕摻雜P型井LPW2可具有摻雜濃度梯度。舉例來說,輕摻雜P型井LPW2的摻雜濃度可自與P型基底P-sub的交界處至與N型井NW2的交界處遞減,因此輕摻雜P型井LPW2在靠近N型井NW2的部分會具有較低的摻雜濃度。
在有些實施例中,由於輕摻雜P型井LPW1及N型井NW1的接面崩潰電壓及輕摻雜P型井LPW2及N型井NW2的接面崩潰電壓較大,因此可以進一步提升開關裝置200的耐高壓能力。此外,由於開關裝置100及200可以利用低壓製程來製作,因此讓積體電路的設計更有彈性。
再者,在有些實施例中,考量到N型摻雜區ND1及ND2與P型井PW1及PW2的電氣特性,第2圖中開關裝置100的N型井NW2可被省略。第5圖本發明一實施例的開關裝置300的結構圖。開關裝置300與開關裝置100可具有相似的結構,並可根據相同的原理操作。
開關裝置300可包含基底Sub、閘極結構G1、具有第一類型載子的井 W1、閘極結構G2、具有第二類型載子的井W2、具有第一類型載子的摻雜區D1及具有第一類型載子的摻雜區D2。
井W1可形成於基底Sub,並有部分設置於閘極結構G1的第一側下方。井W2可形成於基底Sub,並且可設置在閘極結構G1及G2下方。摻雜區D1可形成於井W2,並可設置在閘極結構G1的第二側及閘極結構G2的第一側之間。摻雜區D2可形成於井W2,並可臨接閘極結構G2的第二側。在有些實施例中,第一摻雜類型的載子及第二摻雜類型的載子可具有相異的極性。舉例來說,第一摻雜類型的載子可以是N型載子,而第二摻雜類型的載子可以是P型載子。
在第5圖中,開關裝置300還可包含以介電材料填充的隔離結構I1,隔離結構I1可形成於井W1,並且可設置在閘極結構G1的第一側下方,因此自第一電晶體110的第二端流入或流出的電流會沿著井W1採取繞道的方式行進。在此情況下,井W1可以在第一電晶體110的第二端在形成一段高阻值的路徑,使得第一電晶體110耐受高壓的能力獲得提升。
第5圖進一步描述開關裝置300在第一狀態下所接收到的電壓。在第5圖中,基底Sub及井W2可接收第一參考電壓VR1,摻雜區D2可接收第二參考電壓VR2,閘極結構G2可接收第三參考電壓VR3,閘極結構G1可接收第一操作電壓VDD,而井W1可接收第二操作電壓VPP。
在有些實施例中,第二操作電壓VPP及第一參考電壓VR1之間的壓差絕對值可大於第一操作電壓VDD及第一參考電壓VR1之間的壓差絕對值。第一操作電壓VDD及第一參考電壓VR1之間的壓差絕對值可大於或等於第三參考電壓VR3及第一參考電壓VR1之間的壓差絕對值,而第三參考電壓VR3及第一參考電壓VR1之間的壓差絕對值則可大於或等於第二參考電壓VR2及第一參考電壓VR1之間的壓差絕對值,且第二參考電壓VR2及第一參考電壓VR1之間的壓差絕對值大於或等於零。在此情況下,井W1與基底Sub可進入逆向偏壓的狀態,且 閘極結構G2下方的通道將被截止,亦即第二電晶體120會被截止。
再者,由於閘極結構G1可接收第一操作電壓VDD,而閘極結構G2可接收第三參考電壓VR3,因此可以降低第一電晶體110及第二電晶體120的閘極至汲極電壓,進而也減少了閘極引致汲極漏電流。
第6圖是開關裝置300在第二狀態時所接收到的電壓示意圖。在第6圖中,井W2可接收第四參考電壓VR4,摻雜區D2可接收第一輸入電壓VI1,閘極結構G2可接收第二輸入電壓VI2,而閘極結構G1可接收第一操作電壓VDD。在有些實施例中,第二輸入電壓VI2與第四參考電壓VR4之間的壓差絕對值及第一操作電壓VDD與第四參考電壓VR4之間的壓差絕對值可大於第一輸入電壓VI1及第四參考電壓VR4之間的壓差絕對值,且第一輸入電壓VI1及第四參考電壓VR4之間的壓差絕對值大於或等於零。在此情況下,閘極結構G1及G2下方的通道將被導通,亦即第一電晶體110及第二電晶體120可被導通。
綜上所述,本發明的實施例所提供的開關裝置可包含兩個電晶體以提升耐受高壓的能力。此外,透過在電晶體的汲極/源極端設置淺溝槽隔離結構,可以提升電晶體的崩潰電壓,進而使得開關裝置能夠操作在較高的電壓條件下,而無須以高壓製程製造。以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100:開關裝置
110:第一電晶體
120:第二電晶體
P-sub:P型基底
NW1、NW2:N型井
PW1、PW2:P型井
G1、G2:閘極結構
ND1、ND2、ND3:N型摻雜區
STI1:淺溝渠隔離結構
VR1:第一參考電壓
VR2:第二參考電壓
VDD:第一操作電壓
VPP:第二操作電壓

Claims (22)

  1. 一種開關裝置,包含:一P型基底;一第一閘極結構;一第一N型井,形成於該P型基底上,且有部分設置在該第一閘極結構的一第一側下方;一淺溝槽隔離(shallow trench isolation,STI)結構,形成於該第一N型井,且有部分設置在該第一閘極結構的該第一側下方;一第一P型井,形成於該P型基底上,且設置在該第一閘極結構下方;一第二閘極結構;一第一N型摻雜區,形成於該P型基底,且設置在該第一閘極結構的一第二側及該第二閘極結構的一第一側之間;一第二P型井,形成於該P型基底,且設置在該第二閘極結構下方;一第二N型摻雜區,形成於該第二P型井,且有部分設置在該第二閘極結構下方。
  2. 如請求項1所述之開關裝置,另包含一第三N型摻雜區,形成於該第一N型井,且未被該第一閘極結構所掩蓋,其中該第三N型摻雜區的摻雜濃度大於該第一N型井的摻雜濃度。
  3. 如請求項1所述之開關裝置,其中該第一N型井具有摻雜濃度梯度。
  4. 如請求項1所述之開關裝置,另包含一第一輕摻雜P型井,形成於該P型基底,其中:該第一N型井是形成於該第一輕摻雜P型井;及該第一輕摻雜P型井的摻雜濃度小於該第一P型井的摻雜濃度。
  5. 如請求項4所述之開關裝置,其中該第一輕摻雜P型井具有摻雜濃度梯度。
  6. 如請求項5所述之開關裝置,其中該第一輕摻雜P型井靠近該第一N型井的部分具有較小的摻雜濃度。
  7. 如請求項1所述之開關裝置,另包含一第二N型井,形成於該P型基底,其中該第二N型井的一第一部份是設置於該第一閘極結構下方,該第二N型井的一第二部份是設置於該第二閘極結構下方,及該第一N型摻雜區是形成於該第二N型井。
  8. 如請求項7所述之開關裝置,其中該第一N型井及該第二N型井具有摻雜濃度梯度。
  9. 如請求項7所述之開關裝置,另包含一第二輕摻雜P型井,形成於該P型基底,其中:該第二N型井是形成於該第二輕摻雜P型井;及該第二輕摻雜P型井的摻雜濃度小於該第二P型井的摻雜濃度。
  10. 如請求項9所述之開關裝置,其中該第二輕摻雜P型井具有摻雜濃度梯度。
  11. 如請求項10所述之開關裝置,其中該第二輕摻雜P型井靠近該第二N型井的部分具有較小的摻雜濃度。
  12. 如請求項7所述之開關裝置,其中該第一N型井的摻雜濃度大於該第二N型井的摻雜濃度。
  13. 如請求項1所述之開關裝置,其中當該開關裝置在一第一狀態時:該第二N型摻雜區接收一第一參考電壓;該第二閘極結構接收該第一參考電壓;該第一閘極結構接收一第一操作電壓;及該第一N型井接收一第二操作電壓;其中該第二操作電壓大於該第一操作電壓,及該第一操作電壓大於該第一參考電壓。
  14. 如請求項13所述之開關裝置,其中:當該開關裝置是在該第一狀態時,該第一P型井及該第二P型井接收一第二參考電壓;及該第二參考電壓小於或等於該第一參考電壓。
  15. 如請求項1所述之開關裝置,其中當該開關裝置在一第二狀態時:該第二N型摻雜區接收一輸入電壓;及 該第一閘極結構及該第二閘極結構接收一操作電壓;其中該操作電壓大於或等於該輸入電壓。
  16. 如請求項15所述之開關裝置,其中:當該開關裝置是在該第二狀態時,該第一P型井及該第二P型井接收一參考電壓;及該操作電壓大於該參考電壓。
  17. 一種開關裝置,包含:一基底;一第一閘極結構;一第一井,具有一第一類型的載子,形成於該基底上,且有部分設置在該第一閘極結構的一第一側下方;一第二閘極結構;一第二井,具有一第二類型的載子,形成於該基底,且設置在該第一閘極結構及該第二閘極結構的下方;一第一摻雜區,具有該第一類型的載子,形成於該第二井,且設置在該第一閘極結構的一第二側及該第二閘極結構的一第一側;及一第二摻雜區,具有該第一類型的載子,形成於該第二井,且鄰接於該第二閘極結構的一第二側;其中該第一類型的載子及該第二類型的載子具有相異的極性。
  18. 如請求項17所述之開關裝置,另包含:一隔離結構,以介電材料填充,形成於該第一井,且設置在該第一閘極結 構的該第一側下方。
  19. 如請求項17所述之開關裝置,其中當該開關裝置在一第一狀態時:該基底及該第二井接收一第一參考電壓;該第二摻雜區接收一第二參考電壓;該第二閘極結構接收一第三參考電壓;該第一閘極結構接收一第一操作電壓;及該第一井接收一第二操作電壓;其中該第二操作電壓及該第一參考電壓之間的一第一壓差絕對值大於該第一操作電壓及該第一參考電壓之間的一第二壓差絕對值,該第二壓差絕對值大於或等於該第三參考電壓及該第一參考電壓之間的一第三壓差絕對值,該第三壓差絕對值大於或等於該第二參考電壓及該第一參考電壓之間的一第四壓差絕對值,及該第四壓差絕對值大於或等於零。
  20. 如請求項19所述之開關裝置,其中當該開關裝置在該第一狀態時,該第二閘極結構下方的一通道被截止。
  21. 如請求項17所述之開關裝置,其中當該開關裝置在一第二狀態時:該第二井接收一第四參考電壓;該第二摻雜區接收一第一輸入電壓;該第二閘極結構接收一第二輸入電壓;及該第一閘極結構接收一操作電壓; 其中該第二輸入電壓及該第四參考電壓之間的一第五壓差絕對值及該操作電壓及該第四參考電壓之間的一第六壓差絕對值大於該第一輸入電壓及該第四參考電壓之間的一第七壓差絕對值,及該第七壓差絕對值大於或等於零。
  22. 如請求項21所述之開關裝置,其中當該開關裝置在該第二狀態時,該第一閘極結構下方的通道及該第二閘極結構下方的通道被導通。
TW109130710A 2019-09-11 2020-09-08 開關裝置 TWI780477B (zh)

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508843B (zh) * 2019-01-31 2023-07-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750489B1 (en) * 2002-10-25 2004-06-15 Foveon, Inc. Isolated high voltage PMOS transistor
US6876035B2 (en) * 2003-05-06 2005-04-05 International Business Machines Corporation High voltage N-LDMOS transistors having shallow trench isolation region
TWI336947B (en) * 2007-08-10 2011-02-01 United Microelectronics Corp High-voltage mos transistor device
TWI500156B (zh) * 2012-12-03 2015-09-11 Macronix Int Co Ltd 用於高電壓靜電放電防護的雙向雙極型接面電晶體
TWI525813B (zh) * 2012-06-18 2016-03-11 聯華電子股份有限公司 電晶體裝置及其製造方法
TWI671854B (zh) * 2017-08-31 2019-09-11 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1019964B1 (de) * 1997-09-30 2002-06-05 Infineon Technologies AG Integrierte halbleiterschaltung mit schutzstruktur zum schutz vor elektrostatischer entladung
US7307319B1 (en) * 2004-04-30 2007-12-11 Lattice Semiconductor Corporation High-voltage protection device and process
US7420250B2 (en) * 2004-08-30 2008-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection device having light doped regions
US20080246080A1 (en) 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
TWI368980B (en) * 2006-10-13 2012-07-21 Macronix Int Co Ltd Electrostatic discharge device for pad and method and structure thereof
US8101479B2 (en) * 2009-03-27 2012-01-24 National Semiconductor Corporation Fabrication of asymmetric field-effect transistors using L-shaped spacers
KR101604380B1 (ko) * 2010-04-22 2016-03-18 삼성전자 주식회사 반도체 집적 회로 장치
JP2013187534A (ja) * 2012-03-08 2013-09-19 Ememory Technology Inc 消去可能プログラマブル単一ポリ不揮発性メモリ
US10096544B2 (en) * 2012-05-04 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor interconnect structure
US9018691B2 (en) * 2012-12-27 2015-04-28 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
CN104362149A (zh) * 2014-09-18 2015-02-18 成都星芯微电子科技有限公司 基于螺旋状多晶硅式场效应管充电的半导体启动器件及制造工艺
CN109742071B (zh) * 2019-01-07 2021-04-13 中国科学院微电子研究所 一种soi功率开关的esd保护器件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750489B1 (en) * 2002-10-25 2004-06-15 Foveon, Inc. Isolated high voltage PMOS transistor
US6876035B2 (en) * 2003-05-06 2005-04-05 International Business Machines Corporation High voltage N-LDMOS transistors having shallow trench isolation region
US7297582B2 (en) * 2003-05-06 2007-11-20 International Business Machines Corporation Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions
TWI336947B (en) * 2007-08-10 2011-02-01 United Microelectronics Corp High-voltage mos transistor device
TWI525813B (zh) * 2012-06-18 2016-03-11 聯華電子股份有限公司 電晶體裝置及其製造方法
TWI500156B (zh) * 2012-12-03 2015-09-11 Macronix Int Co Ltd 用於高電壓靜電放電防護的雙向雙極型接面電晶體
TWI671854B (zh) * 2017-08-31 2019-09-11 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

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