FI336947 • 九、發明說明： *； . 【發明所屬之技術領域】 本發明係關於一種高壓MOS電晶體，特別是一種具有複數個 第.一場電極環之高壓MOS電晶體，並藉由施加一主動電壓於至少 一該第一場電極環，以緩和該高壓MOS電晶體内之電場變化，以 防止該高壓MOS電晶體的周邊崩潰。 | 【先前技術】 今曰的電力系統所供給的電大多是頻率為5〇Hz或6〇Hz、電 ' 壓從100V到240V不等的交流電壓源，由於機電設備所需的電 • 壓、頻率不一，因此在機電設備内常利用電子元件的開關動作， 配合電感、電容、電阻、變壓器等被動元件，以達到電源轉換及 控制的目的，以供給機電設備所需的電壓及頻率。例如，新型的 空調系統採用主導低壓輸出給内部電子設備的供電系統，此一供 電系統係由一個内部的電源開關調控欲輸出的電壓大小，將來自 1外部的電壓大小降至内部機電設備的運作，以供機電設備利用電 壓，同時該理想的電源開關必須具備效率高、重量輕、尺寸小、 待機功耗低等多個重要特性。 由於尚壓金氧半導體（high-voltage metal-oxide semiconductor，以下簡稱HVM〇s)電晶體具有開關的特性故已 被廣地應用在中央處理器電源供衂^^⑽⑽⑽小電管理系 統(power management system)、直流/交流轉換器(ac/dc 、 6 Ί336947 r converter)、LCD與電漿電視驅動器、車用電子、電腦週邊、小尺 寸直流馬達控制器、以及消費性電子產品等領域。 一般來說，來自HVMOS電晶體外部的電源多以交流電的形 式供應，考量到交流電的振幅變化，平均電壓為24〇v的交流電源 在瞬間的電壓差將可能高達600V或以上，將超過大多數現存取 M〇S電晶體的崩潰電壓(breakdown voltage)，而造成HVMOS電 馨 晶體的損壞，因此，當務之急必須設計出在高壓環境下仍可正常 運作的HVMOS電晶體，以符合實務上的需求。 【發明内容】 本發明係關於一種高壓MOS電晶體，特別是一種在基底上方 設有複數個場電極環之高壓M0S電晶體，並藉由施加主動電壓於 至少一該場電極環，以改變基底内之電場，以防止高壓M〇s電晶 體的周邊崩潰。 為達上述目的，本發明係提供一高壓M〇s電晶體，其包含一 具有-第-導電性之基底、一具有一第二導電性之源極摻雜區 (S〇Urce)、一具有該第二導電性之汲極摻雜區(drain)、至少一第二 乜雜區以及包圍該第二摻雜區之第三離子井。此外，高壓 電晶體另包含有-絕緣物設於部分之該第三離子井上以及一閘極 介電層設於該源極摻雜區與該絕緣物間之該基底表面，且該閘極 介電層表面設有延伸到該絕緣物上之一閘極。該高壓M〇s電晶體 f1336947 :另包含-第-介電層’覆蓋該閘極、該轉雜及該絕緣物，同 時該第介電層上設置有複數個第一場電極環(脇p丨批麵)以 •及橫越該等第一場電極環之一第-導電層(first conductive 一）， 其中。亥第-導電層具有—第—端電連接該沒極摻_、一第二端 與至J 一该第一場電極環電連接以及一第三端電連接一連接墊。 本發明的特點在於藉由第一導電層、汲極、和第一場電極環 籲間的電連接’使第一場電極產生電場，緩和高壓MOS電晶體在運 作時，基底内第二摻雜區與第三離子井間鄰近汲極之交界面附近 電％過於集中的現象，因此本發明之高壓M〇s電晶體之崩潰電壓 可達700伏特(V)以上，並具有超越習知HVMOS電晶體承載電壓 的能力。 【實施方式】 為使貴審查委員與熟習該項技藝者能更進一步了解本發 ⑩明’以下列舉出具體實例，並配合圖示、元件符號等，仔細說明 本發明的構成内容及所欲達成之功效。 請參閱第1圖及第2圖，第1圖及第2圖係依據本發明之一 第一較佳實施例所繪示之高壓MOS電晶體的結構示意圖，其中第 1圖為南壓MOS電晶體的剖面示意圖，第2圖為高壓m〇S電晶 體的俯視圖，且第1圖中A-A,的位置係與第2圖中A-A，相對 - 應。高壓MOS電晶體100係製作於一基底40上，例如一 p型矽 ，1336947 :基底’與相鄰之其他電子元件間係由至少一絕緣物所隔絕 >例如 場氧化層42或至少一;|溝隔離(STI，圖未示）。高壓M〇s電晶 體100包含一源極摻雜區44、-閘極46以及一没極摻雜區48， 其中源極摻雜區44係為一高濃度N型摻雜區，其緊鄰於一高濃度 P型第-摻雜區50，且源極摻雜區44與高濃度p型第一換雜區 50白叹於p型第一離子井52巾，在場氧化層42下方緊鄰p型 離子井52處則β又有-局麼p型離子井(high v〇丨邮e p咖以weu) • %。另外’沒極播雜區48係為一高濃度的N型摻雜區，沒極摻雜 區48係設於-N型第；子井5〇，且N型第二離子井％又 ，設於1 N型第三離子井56中，如此，構成三重的梯度井結構。 .如第1圖所示，高壓MOS電晶體1〇〇設有一絕緣物，其位於部分 之深N型第二離子井56上’並緊鄰於N型第二離子井％，且該 絕緣物可喊-場氧化層58歧至少—淺溝隔糊未示）；場氧 化層58的下方至少設有一 p型第二摻雜區6〇，其位於p型第一 Φ離子井52與N型第二離子井54之間，為簡化說明，第1圖僅緣 不-個P型第二雜區6G作為代表，然而本發明之實施並不偈限 於此，亦可在p型第-離子井52與N型第二離子井54之間設置 複數個P型第二摻雜區60。此外，在源極摻雜區从與場氧化層 58間之基底4〇表面設有—閘極介電層&，例如以沉積或熱氧化 製程形成之-氧化珍層，而高壓则電晶體丨⑻之閘極％即設 置在閉極介電層62上，並且延伸到場氧化層％上方；同時，高 .壓则電晶體1〇0具有一第一介電層64披覆間極46、該等摻雜 區、該專離子井及場氧化層58。 『1336947 • 如第1圖所示’設於高壓MOS電晶體100之基底40的P型 第二摻雜區60在與深N掣第三離子井56鄰接的交界處，因彼此 電性上的差異，在P型第二換雜區的右側、左側以及底部分別 形成PN介面(PNjunction) ’經觀察發現，高壓M〇s電晶體1〇〇 在運作時，位於P型第二摻雜區6〇左右兩側的pn介面附近會有 電場過度集中的現象，尤以位於P型第二摻雜區6〇右側的pN介 面附近特別嚴重，很容易在此處發生電晶體的崩潰效應。為避免 • 崩潰效應發生’本發明之高壓MOS電晶體1〇〇另包含複數個第一 場電極環70a、70b、70c、70d、70e以及一橫跨第一場電極環7〇a_e '第一導電層68設於第一介電層64之上；在此，請一併參考第j 圖及第2圖’其中第2圖係输示高壓M〇s電晶體1〇〇 _面示意 圖，為簡化說明，本較佳實施例中係以五個相同線寬大小、呈同 心圓狀排列的第一場電極環70a、7〇b、7〇c、7〇d、7〇e作代表且 各場電極環70a-e的線寬大小、間距及數量可依產品需求更動，在 •此不另作限制。如第2圖所示，第一導電層68具有至少三個端點 分別與向壓MOS電晶體1〇〇内的元件或其周邊的電路系統電 接’例如連接汲極48之一第一端76、連接第一場電極環、期之一 第二端78以及連接-連接塾8〇之第三端82，其中連接第一場電 極環70d之第二端78，恰位於N型第三離子井％與p型第二摻 雜區60接近源極44處的交界面上方，除了與第一導電層68電連 接的場電極環期外，其他的第—場電極環施、爲n . 白可視為浮置(floating)的元件。 Π336947 請同時參考第1圖及第2圖，第-導電層68在第一端76藉 由-第-端點插塞84自祕48導人_主動賴，再由電連接第 -場電極環70d之第二端78對第一場電極環7()d施予該主動電 壓利用導電體間的耗合(c〇upling)，對於p型第二推雜區⑹左側 接近源極44的PN界面以及位於p型第二摻雜區6〇右側接近汲極 仙的PN界面都可發揮其效用，有效緩和兩處電場過於集中的現 象以避免朋潰(breakdown)效應發生。FI336947 • Nine, invention description: *; . Technical Field of the Invention The present invention relates to a high voltage MOS transistor, in particular to a high voltage MOS transistor having a plurality of first field ring, and by applying an active A voltage is applied to at least one of the first field electrode rings to mitigate an electric field change in the high voltage MOS transistor to prevent collapse of a periphery of the high voltage MOS transistor. [Prior Art] Most of the power supplied by the current power system is an AC voltage source with a frequency of 5 Hz or 6 Hz and an electric voltage of 100 V to 240 V. Due to the voltage and voltage required for electromechanical equipment, The frequency is different. Therefore, in the electromechanical equipment, the switching action of the electronic components is often used, and passive components such as inductors, capacitors, resistors, and transformers are matched to achieve the purpose of power conversion and control to supply the voltage and frequency required by the electromechanical device. For example, the new air conditioning system uses a power supply system that directs low-voltage output to internal electronic equipment. This power supply system regulates the voltage to be output by an internal power switch, reducing the voltage from outside 1 to the operation of internal electromechanical equipment. In order to use voltage for electromechanical equipment, the ideal power switch must have many important characteristics such as high efficiency, light weight, small size, and low standby power consumption. Due to the switching characteristics of high-voltage metal-oxide semiconductor (HVM〇s) transistors, they have been widely used in central processor power supply. ^^(10)(10)(10) small power management system (power management) System), DC/AC converters (ac/dc, 6 Ί336947 r converter), LCD and plasma TV drivers, automotive electronics, computer peripherals, small size DC motor controllers, and consumer electronics. Generally speaking, the power supply from the outside of the HVMOS transistor is mostly supplied in the form of alternating current. Considering the amplitude change of the alternating current, the alternating voltage of the average voltage of 24 〇v will be as high as 600V or more in an instant, which will exceed most The breakdown voltage of the M〇S transistor is now accessed, which causes damage to the HVMOS enamel crystal. Therefore, it is imperative to design a HVMOS transistor that can still operate normally under a high voltage environment to meet practical requirements. SUMMARY OF THE INVENTION The present invention is directed to a high voltage MOS transistor, and more particularly to a high voltage MOS transistor having a plurality of field electrode rings disposed above a substrate, and changing the substrate by applying an active voltage to at least one of the field electrode rings. The electric field inside prevents the collapse of the periphery of the high voltage M〇s transistor. To achieve the above object, the present invention provides a high voltage M〇s transistor comprising a substrate having a first conductivity, a source doped region having a second conductivity (S〇Urce), and having The second conductive drain doped region, the at least one second doped region, and the third ion well surrounding the second doped region. In addition, the high voltage transistor further includes an insulator disposed on the portion of the third ion well and a gate dielectric layer disposed on the surface of the substrate between the source doped region and the insulator, and the gate The surface of the dielectric layer is provided with a gate extending to the insulator. The high voltage M〇s transistor f1336947: further comprising a -first dielectric layer covering the gate, the turns and the insulator, and the plurality of first field electrode rings are disposed on the dielectric layer丨 batching) and traversing one of the first field electrode rings (first conductive one), where. The Haidi-conductive layer has a first-stage electrical connection to the immersion-doped, a second end electrically connected to the first field electrode ring and a third end electrically connected to a connection pad. The invention is characterized in that the first field electrode generates an electric field by the electrical connection between the first conductive layer, the drain and the first field electrode ring, and the second doping in the substrate is moderated during operation of the high voltage MOS transistor. The electric power near the interface between the zone and the third ion well is too concentrated. Therefore, the high voltage M〇s transistor of the present invention has a breakdown voltage of 700 volts (V) or more and has a higher HVMOS power than the conventional HVMOS. The ability of a crystal to carry a voltage. [Embodiment] In order to enable the reviewing committee and those skilled in the art to have a better understanding of the present invention, the specific examples are listed below, and the components of the present invention and the desired components are carefully described. The effect. Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams showing the structure of a high voltage MOS transistor according to a first preferred embodiment of the present invention, wherein FIG. 1 is a south voltage MOS battery. Schematic diagram of the cross section of the crystal, Fig. 2 is a top view of the high voltage m〇S transistor, and the position of AA in Fig. 1 is opposite to that of AA in Fig. 2. The high voltage MOS transistor 100 is fabricated on a substrate 40, such as a p-type germanium, 1336947: the substrate 'is separated from adjacent electronic components by at least one insulator>, such as field oxide layer 42 or at least one; | Ditch isolation (STI, not shown). The high voltage M〇s transistor 100 includes a source doped region 44, a gate 46, and a gateless doped region 48, wherein the source doped region 44 is a high concentration N-type doped region adjacent to a high concentration P-type doping region 50, and the source doping region 44 and the high concentration p-type first impurity-doping region 50 are sighed by the p-type first ion well 52, immediately below the field oxide layer 42. At the 52nd type ion well, β has a p-type ion well (high v〇丨 mail ep coffee to weu) • %. In addition, the 'no-polarization zone 48 is a high-concentration N-type doped zone, the non-polar doped zone 48 is set to the -N type; the sub-well is 5〇, and the N-type second ion well is In the 1 N type third ion well 56, thus, a triple gradient well structure is constructed. As shown in FIG. 1, the high voltage MOS transistor 1 is provided with an insulator which is located on a portion of the deep N-type second ion well 56 and is adjacent to the N-type second ion well%, and the insulator can be Shouting - field oxide layer 58 is at least - shallow trench is not shown); at least below the field oxide layer 58 is provided a p-type second doped region 6 〇 located in the p-type first Φ ion well 52 and N-type Between the two ion wells 54, for the sake of simplicity, the first figure is only a representative of the P-type second miscellaneous region 6G. However, the implementation of the present invention is not limited thereto, and the p-type ion-ion well 52 may also be used. A plurality of P-type second doped regions 60 are disposed between the N-type second ion wells 54. In addition, a source dielectric layer is provided from the surface of the substrate 4 between the field oxide layer 58 and a gate dielectric layer, for example, a deposition or thermal oxidation process, and a high voltage transistor. The gate % of 丨 (8) is disposed on the closed dielectric layer 62 and extends above the field oxide layer %; meanwhile, the high voltage is such that the transistor 1 〇 0 has a first dielectric layer 64 covering the interpole 46 The doped regions, the ionized well and the field oxide layer 58. "1336947 • As shown in Fig. 1, the P-type second doping region 60 provided on the substrate 40 of the high voltage MOS transistor 100 is electrically connected to each other at a boundary adjacent to the deep N 掣 third ion well 56. The difference is that a PN interface is formed on the right side, the left side, and the bottom of the P-type second change region, respectively. It is observed that the high-voltage M〇s transistor 1〇〇 is in the P-type second doped region 6 when it is in operation. There is a phenomenon that the electric field is excessively concentrated near the pn interface on the left and right sides, especially in the vicinity of the pN interface located on the right side of the P-type second doped region 6〇, and the collapse effect of the transistor is easily generated here. In order to avoid the occurrence of a collapse effect, the high voltage MOS transistor 1 of the present invention further includes a plurality of first field electrode rings 70a, 70b, 70c, 70d, 70e and a first across the first field electrode ring 7〇a_e ' The conductive layer 68 is disposed on the first dielectric layer 64. Here, please refer to the figure j and the second figure, wherein the second figure is a schematic diagram of the high voltage M〇s transistor. Simplified description, in the preferred embodiment, the first field electrode rings 70a, 7〇b, 7〇c, 7〇d, 7〇e are arranged in five concentric circles of the same line width and are represented by The line width, spacing and number of field electrode rings 70a-e can be changed according to product requirements, and there is no other limitation. As shown in FIG. 2, the first conductive layer 68 has at least three end points electrically connected to the circuit in the MOS transistor 1 or its peripheral circuit, for example, the first end of one of the connection poles 48. 76. Connect a first field electrode ring, a second end 78 of the period, and a third end 82 of the connection-connecting port 8〇, wherein the second end 78 of the first field electrode ring 70d is connected to the N-type third ion. The well % and the p-type second doped region 60 are close to the interface at the source 44, except for the field electrode ring period electrically connected to the first conductive layer 68, and the other first field electrode ring is n. Can be considered as a floating component. Π336947 Please refer to FIG. 1 and FIG. 2 at the same time, the first conductive layer 68 is guided at the first end 76 by the -terminal end plug 84, and then electrically connected to the first field electrode ring. The second end 78 of 70d applies the active voltage to the first field electrode ring 7()d by utilizing the coupling between the conductors, and the PN of the left side of the p-type second dummy region (6) close to the source 44. The interface and the PN interface located on the right side of the p-type second doping region 6 汲 close to the 汲 仙 仙 can exert their effects, effectively alleviating the phenomenon that the two electric fields are too concentrated to avoid the occurrence of a breakdown effect.
▲ 2前述之第—較佳實施例外，第3圖係依據本發明之一第二 較佳實施例崎示之高壓廳電晶體勘的結構示意圖，為則 說明與第一較佳實施例相同之元件將以相同的元件符號表示。 如第3圖所不，除具備第一較佳實施例之元件外在第一場電極 場氧化層58間，高壓⑽電晶體2㈣包含複數個 $ ==環86a、86b、86c、_，較佳之第二場電極環_ 糸=夕晶石夕或與多晶石夕電性相似之材料，且第二場電極環心( 係以父錯㈣的方式設置於第—場電極環7‘e下方。第二較 高壓_電晶體朋除可藉由第—較佳實施例所述以 f/予=物卜，财㈣，峨_二場電極環▲ 2, in addition to the foregoing-preferred embodiment, FIG. 3 is a schematic structural view of a high-voltage hall plasma survey according to a second preferred embodiment of the present invention, and is the same as the first preferred embodiment. Elements will be denoted by the same symbol. As shown in Fig. 3, in addition to the elements of the first preferred embodiment, between the first field electrode oxide layer 58, the high voltage (10) transistor 2 (four) comprises a plurality of $== rings 86a, 86b, 86c, _, Preferably, the second field electrode ring _ 糸 夕 夕 夕 或 or a material similar to the polycrystalline stone, and the second field ring center (in the form of a parent error (four) is set in the first field electrode ring 7'e The second higher pressure_electrode can be removed by the first preferred embodiment by f/pre=object, fortune (four), 峨_ two field electrode ring
i t 緩和位^除摻縣⑼左右兩側之PN 界面過度集中的電場。 此外，第4圖為依據本發明之―坌_ 疋第二較佳貧施例所繪示之高 M： MOS電晶體300的示意圖，除 弟一幸义佳實施例可見之第二場電 :極私·-"1外，在第一場電極環7〇a_e上另設有-第二介電層88 =及稷數個第三場電極環9Ga、懸、她、、術較佳之第三 暴電極%< 9Ga·6係包含金屬或其他具有導電特性的材料，且第三場 電極環90a-e與第一場電極環1也是呈現彼此交錯設置的排列 村。當高壓M〇S電晶體運作時，可對第三場電極環9〇a_e 7予-主動賴(圖未示），同樣藉由麵合的方式，經由第一場電極 % 70a-e或第二場電極環86a d，緩和高墨m〇s電晶體在p •型第一摻雜區60左側接近源極44的PN界面以及位於P型第二摻 雜區60右側接近汲極48的pN界面兩處電場過於集中的現象。 依據本發明之精神’本發明另揭露一第四較佳實施例，請參 閱第5圖及第6圖’其搶示第四較佳實施例之高壓M〇s電晶體的 俯視圖，為簡化說明，第5圖僅繪示一高壓應電晶體所包含之 複數個第一場電極環96a、96b、96c、96d、96e及第一導電層94， 瞻其他與前述實施例相同之元件則不再重覆說明。第一導電層94具 有與錄(目未tf)t雜之—帛—端％以及與連齡％電連接之 第三端102，且至少有一浮置的第一場電極環，如第一場電極環 96d ’電連接一第-電壓源' 1〇4，第—電壓源1〇4對第一場電極環 %d施予-主動電壓，其電壓值可等於或小於沒極的電壓大小，以 緩和下方N型第三離子井(圖未示)與p型第二換雜區(圖未示)之 PN介面在該高壓M0S電晶體運作喊生之電場集中的現象。另 外，第四較佳實施例中浮置的第一場電極環96a_e可分別電連接不 同的外接電壓源’如第6圖所示’第一場電極環96a係電連接至 12 1336947 一第二電壓源106，第一場電極環96b係電連接至一第三電壓源 1〇8,第一場電極環96c谗電連接至一第四電壓源ιι〇，第一場電 極環96d係電連接至一第一電壓源1〇4，第一場電極環咖係電連 接至一第五電壓源112,而各外接電壓源所提供之主動電壓值可依 實際運作需求作調整，在此並不多作限制。 田本發明之局壓MOS電晶體在運作時，其電場_電位的變化 ❿ 如第7圖所示。依據前述之實施例可得知，該等高壓M〇s電晶體 融第一導電層的設置，將—主動電壓施加於至少—第一場電極 壤上’透過導電__合叫免高壓電場過度 集中，而轉恆定㈣獻小，而高壓廳§電晶體⑽電壓值變 化則如第7圖所示，自沒極到祕呈現線性遞減的變化；因此， 當本發明之高壓M〇S電晶體應用在機件的電力系統時，將可有效 =把來自外部的降至機件_可運作的賴大小，以符合其 需求。 /' 綜觀本㈣之實_，其目的在於 接 極環之第-導電層，在連接處產 ㈣第场電 雷曰十應之電场’以維持高壓M〇S 電曰曰體運作_内部電場的恆定，而第 的接點位置和錄秘樹轉 I、 曰 個ϋν… 寻竿乂佳貫鈿例所示，可調整為連接二 個或一個以上、相鄰或不相鄰的第 和第-導電層不限;^ 電極辰，且第一場電極環 …η又在问一水平面上 環設於不同水平面時，場電 帛#電I、域極 讀第—導電層可透過其他元件， 1336947 如一第二端點滅，電連紐^於本發明之各實關中，係以 設於第-介電層上方之第—場電極為例施予—主動電壓，而不偈 於此限’在應用上’對第二場電極環或第三場電極環施予主動電 [亦可達成與第-場電極環相同之功效。此外，本發明所繪示 之场電極環係關形之同心_外型呈現，其外型可更動為惰圓 形矩形、多邊形或其他合適的形狀，亦具有相同之功能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，冑應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖及第2圖係依據本發明之一第―較佳實施例所繪示之一高 壓MOS電晶體的結構示意圖。 第3圖係依據本發明之一第二較佳實施例所繪示之另一高壓m〇s 電晶體的結構示意圖。 第4圖為依據本發明之一第三較佳實施例所繪示之又一高壓^^〇8 電晶體的結構示意圖。 第5圖與第6圖係依據本發明之一第四較佳實施例之再一高壓 MOS電晶體之示意圖。 第7圖係繪示本發明之高壓m〇S電晶體運作時電場及電壓的關係 圖。 14 1336947i t mitigation bit ^ In addition to the excessive concentration of the PN interface on the left and right sides of the county (9). In addition, FIG. 4 is a schematic diagram of a high M: MOS transistor 300 according to the second preferred embodiment of the present invention, except for the second field of electricity: In addition to the private---1, the first electrode ring 7〇a_e is additionally provided with a second dielectric layer 88 = and a plurality of third field electrode rings 9Ga, hanging, her, and a better third. The violent electrode % < 9Ga·6 series contains a metal or other material having electrically conductive characteristics, and the third field electrode ring 90a-e and the first field electrode ring 1 are also arranged in a staggered arrangement. When the high voltage M〇S transistor operates, the third field electrode ring 9〇a_e 7 can be actively activated (not shown), also by the face-to-face method, via the first field electrode % 70a-e or the first The two field electrode ring 86a d mitigates the PN interface of the high ink m〇s transistor near the source 44 on the left side of the p − type first doping region 60 and the pN of the drain pad 48 on the right side of the P type second doping region 60 The two electric fields on the interface are too concentrated. In accordance with the spirit of the present invention, the present invention further discloses a fourth preferred embodiment. Please refer to FIG. 5 and FIG. 6 for a top view of the high voltage M〇s transistor of the fourth preferred embodiment. 5 is only a plurality of first field electrode rings 96a, 96b, 96c, 96d, 96e and a first conductive layer 94 included in a high voltage transistor, and other components similar to the foregoing embodiments are no longer used. Repeat the instructions. The first conductive layer 94 has a third end 102 electrically connected to the recording terminal and the third terminal 102 electrically connected to the continuous age, and has at least one floating first field electrode ring, such as the first field. The electrode ring 96d' is electrically connected to a first-voltage source '1〇4, and the first-voltage source 1〇4 applies an active voltage to the first field electrode ring %d, and the voltage value thereof may be equal to or less than the voltage of the electrodeless electrode. To alleviate the phenomenon that the PN interface of the N-type third ion well (not shown) and the p-type second impurity-changing region (not shown) is concentrated in the electric field of the high-voltage MOS transistor. In addition, the floating first field electrode rings 96a-e in the fourth preferred embodiment can be electrically connected to different external voltage sources respectively. As shown in FIG. 6, the first field electrode ring 96a is electrically connected to 12 1336947 and the second. The voltage source 106, the first field electrode ring 96b is electrically connected to a third voltage source 1〇8, the first field electrode ring 96c is electrically connected to a fourth voltage source ιι, and the first field electrode ring 96d is electrically connected. Up to a first voltage source 1〇4, the first field electrode ring is electrically connected to a fifth voltage source 112, and the active voltage value provided by each external voltage source can be adjusted according to actual operational requirements, and is not More restrictions. The field-voltage MOS transistor of the invention has a change in electric field_potential as shown in Fig. 7. According to the foregoing embodiments, the high-voltage M〇s transistors are fused to the first conductive layer, and the active voltage is applied to at least the first field electrode, and the high-voltage electric field is excessively transmitted through the conductive __ Concentration, and constant (4) contribution small, while the voltage value of the high voltage hall § transistor (10) changes as shown in Fig. 7, since the end of the curve shows a linearly decreasing change; therefore, when the high voltage M〇S transistor of the present invention When applied to the power system of the machine, it will be effective to reduce the size of the machine from the outside to the size of the machine to meet its needs. /' Take a look at this (4) _, the purpose is to connect the pole-conducting layer of the pole ring, at the junction (4) the electric field of the first field electric thunders to maintain the high voltage M〇S electric 运作 body operation _ internal The electric field is constant, and the position of the first contact and the record tree turn I, 曰 ϋ ν... See the example of the best example, which can be adjusted to connect two or more, adjacent or non-adjacent The first conductive layer is not limited; ^ the electrode is, and the first field electrode ring ... η is placed on a different horizontal plane when asked to be on a horizontal plane, the field electric 、 # electric I, the domain pole reading the first conductive layer can pass through other components, 1336947, as a second terminal is extinguished, in the various aspects of the present invention, the first field electrode disposed above the first dielectric layer is exemplified as an active voltage, and is not limited thereto. In application, 'active current is applied to the second field ring or the third field electrode ring [the same effect as the first field electrode ring can also be achieved. In addition, the field electrode ring of the present invention is shown in the concentric shape of the closed shape, and its appearance can be changed to an odd circular rectangle, a polygon or other suitable shape, and has the same function. The above are only the preferred embodiments of the present invention, and the equivalent variations and modifications made by the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 and Fig. 2 are schematic views showing the structure of a high voltage MOS transistor according to a first preferred embodiment of the present invention. Figure 3 is a schematic view showing the structure of another high voltage m〇s transistor according to a second preferred embodiment of the present invention. FIG. 4 is a schematic structural view of still another high voltage transistor according to a third preferred embodiment of the present invention. Fig. 5 and Fig. 6 are views showing still another high voltage MOS transistor according to a fourth preferred embodiment of the present invention. Figure 7 is a graph showing the relationship between electric field and voltage during operation of the high voltage m〇S transistor of the present invention. 14 1336947
【主要元件符號說明】 100 、 200 、 高壓MOS電晶體 40 基底 300 、 400 42 場氧化層 44 源極摻雜區 46 閘極 48 >及極推雜區 P型第一離子 50 P型第一摻雜區 52 井 N型第二離子 53 高壓P型離子井 54 井 56 深N型第三離子井 58 場氧化層 60 P型第二摻雜區 62 閘極介電層 64 第一介電層 68 第一導電層 70a、70b、 第一場電極環 76 第一端 70c、70d、70e 78 第二端 80 連接墊 82 第三端 84 第一端點插塞 86a、86b、 第二場電極環 88 第二介電層 86c 、 86d 90a、90b、 第三場電極環 94 第一導電層 90c、90d、90e 96a、96b、 95 第一端 第一場電極環 96c、96d、96e 15 『1336947 98 連接墊 102 第三端 104 第一電壓源 106 第二電壓源 108 第三電壓源 110 第四電壓源 112 第五電壓源[Main component symbol description] 100, 200, high voltage MOS transistor 40 substrate 300, 400 42 field oxide layer 44 source doping region 46 gate 48 > and pole push region P type first ion 50 P type first Doped region 52 Well N-type second ion 53 High-pressure P-type ion well 54 Well 56 Deep N-type third ion well 58 Field oxide layer 60 P-type second doped region 62 Gate dielectric layer 64 First dielectric layer 68 first conductive layer 70a, 70b, first field electrode ring 76 first end 70c, 70d, 70e 78 second end 80 connection pad 82 third end 84 first end plugs 86a, 86b, second field electrode ring 88 second dielectric layer 86c, 86d 90a, 90b, third field electrode ring 94 first conductive layer 90c, 90d, 90e 96a, 96b, 95 first end first field electrode ring 96c, 96d, 96e 15 "1336947 98 Connection pad 102 third end 104 first voltage source 106 second voltage source 108 third voltage source 110 fourth voltage source 112 fifth voltage source
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