TWI643271B - 熱增強型全模製扇出模組 - Google Patents
熱增強型全模製扇出模組 Download PDFInfo
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- TWI643271B TWI643271B TW105130761A TW105130761A TWI643271B TW I643271 B TWI643271 B TW I643271B TW 105130761 A TW105130761 A TW 105130761A TW 105130761 A TW105130761 A TW 105130761A TW I643271 B TWI643271 B TW I643271B
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- semiconductor die
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- molded core
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Classifications
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract
一種製造一半導體裝置之方法,其可包括提供具有黏著劑之一暫時載體。可將一第一半導體晶粒一及第二半導體晶粒面向上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內。可藉由在單一步驟中囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及導電互連件之側表面而形成一嵌入式晶粒面板。藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下可互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件。可將該至少一個模製核心單元安裝至一有機多層基材。
Description
本揭露係關於包含熱增強型扇出模組之半導體封裝及其製造方法。
半導體裝置常見於現代電子產品中。半導體裝置具有不同之電組件數量及電組件密度。離散半導體裝置一般含有一種類型電組件,例如,發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、及功率金屬氧化物半導體場效電晶體(MOSFET)。整合式半導體裝置一般而言含有數百至數百萬個電組件。整合式半導體裝置之實例包括微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、及數位微鏡裝置(DMD)。
半導體裝置執行各式各樣功能,諸如信號處理、高速計算、傳輸及接收電磁信號、控制電子裝置、將日光轉變成電力、及建立用於電視顯示器之視覺投影。在娛樂、通訊、功率轉換、網路、電腦、及消費性產品領域中可見到半導體裝置。軍事應用、航空、汽車、工業控制器、及辦公室設備中亦可見到半導體裝置。
半導體裝置利用半導體材料之電性質。半導體材料之原子結構允許藉由施加一電場或基極電流或透過摻雜程序來操縱其導電性。摻雜引入雜質至半導體材料中以操縱及控制半導體裝置之導電性。
一半導體裝置含有主動及被動電結構。主動結構(包括雙極性及場效電晶體)控制電流之流動。藉由改變摻雜的位準及一電場或基極電流施加的位準,電晶體促進或限制電流之流動。被動結構(包括電阻器、電容器、及電感器)建立執行各式各樣電功能所必須的電壓與電流之間之關係。被動結構及主動結構經電連接以形成電路,其致能半導體裝置執行高速計算及其他實用的功能。
一般使用兩個複雜的製造程序來製造半導體裝置,即,前段製造及後段製造,各者可能涉及數百個步驟。前段製造涉及形成複數個半導體晶粒於一半導體晶圓之表面上。每一半導體晶粒典型地相同且含有藉由電連接主動及被動組件而形成之電路。後段製造涉及從晶圓成品中單切個別半導體晶粒,及封裝晶粒以提供結構支撐及環境隔離。如本文中所使用,用語「半導體晶粒(semiconductor die)」係指彼字詞之單數形及複數形兩者,並且據此可係指一單一半導體裝置及多個半導體裝置兩者。
半導體製造之一個目標是生產愈小半導體裝置。愈小裝置典型地消耗愈少功率、具有愈高效能,且能夠愈有效地生產。另外,愈小半導體裝置具有愈小佔用面積,此對於愈小的最終產品係所欲的。藉由前段製程之改良而實現愈小的半導體晶粒大小能,從而產生具有尺寸愈小、密度愈高的主動及被動組件的半導體晶粒。後段製程可藉由電互連與封裝材料的改良而產生佔用面積更小的半導體裝置封裝。
一種用於對多個半導體晶粒或晶片10進行高路由密度及高熱耗散的整合的方法是將具有微凸塊、凸塊或球體12之半導體晶粒10覆晶附著於矽(Si)中介層20,且進一步將Si中介層20覆晶附著於封裝或多層有機球狀柵格陣列(BGA)基材30,以形成具有Si中介層20之半導體封裝40。晶片10可係個別半導體晶粒或晶粒條(strip)或晶粒片(die slice),包括28奈米場可程式化閘極陣列(FPGA)晶粒片。Si中介層20提供多個晶片10之間的高密度路由。Si穿孔(TSV) 22形成於Si中介層20中,以使電信號穿過路由層或重分佈層(RDL) 24及TSV 22而被路由至中介層底部上的覆晶凸塊或C4凸塊26之陣列。路由層24是高帶寬(bandwidth)、低時(low-latency)之連接。進出封裝基材30的信號可被路由穿過覆晶凸塊26及球狀柵格陣列凸塊或焊球32。在封裝40組裝至母板之後,散熱器可附著於封裝40,諸如附著於晶片10之背表面14。
現在存在改良半導體製造之一機會。因此,在一態樣中,一種製造全模製扇出模組(FMFOM)之方法可包含:提供包含黏著劑之一暫時載體,該黏著劑設置於該暫時載體之一頂表面上方;提供包含導電互連件之一第一半導體晶粒,該等導電互連件耦接至該第一半導體晶粒之一作用表面;及提供包含導電互連件之一第二半導體晶粒,該等導電互連件耦接至該第二半導體晶粒之一作用表面。在囊封該第一半導體晶粒及該第二半導體晶粒之前,可將該第一半導體晶粒及該第二半導體晶粒面向上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內。藉由在單一步驟中利用囊封物囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及該等導電互連件之側表面而形成一嵌入式晶粒面板。藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下可互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元。可移除該暫時載體。可將該至少一個模製核心單元安裝至一有機多層基材。利用一熱界面材料(TIM)可將一散熱器耦接至該模製核心單元,該熱界面材料設置於一散熱器與該模製核心單元之間。
製造FMFOM之方法可進一步包含:在囊裝該第一半導體晶粒及該第二半導體晶粒之後,從該黏著劑移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面。該第一半導體晶粒及該第二半導體晶粒之該等背表面自該囊封物偏移一距離,該距離大於10 µm(微米)。可提供該TIM在該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方,及利用設置在該散熱器與該模製核心單元之間之該TIM可將該散熱器耦接至該模製核心單元。該等導電互連件可形成為銅椿(stud),且該等導電互連件可進一步包含10微米至100微米之高度,且不含焊料。該精細節距堆積互連結構可直接接觸該等導電互連件。該精細節距堆積互連結構可包含小於3微米之線及空間距離(line and space distance)。在將該至少一個模製核心單元安裝至該有機多層基材之前可測試該至少一個模製核心單元之導電性。
在另一態樣中,一種製造FMFOM之方法可包含提供含有黏著劑之一暫時載體,該黏著劑設置在該暫時載體之一頂表面上方。在囊封該第一半導體晶粒及該第二半導體晶粒之前,可將一第一半導體晶粒及一第二半導體晶粒面朝上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內。藉由在單一步驟中囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及導電互連件之側表面而形成一嵌入式晶粒面板,該等導電互連件耦接至該第一導體晶粒及該第二半導體晶粒。藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下可互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元。可移除該暫時載體,及可將該至少一個模製核心單元安裝至一多層基材。
該製造FMFOM之方法可進一步包含:在囊封該第一半導體晶粒及該第二半導體晶粒之前將該第一半導體晶粒及該第二半導體晶粒面朝上安裝至該載體,及在囊封該第一半導體晶粒及該第二半導體晶粒之後從該載體移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面。該第一半導體晶粒及該第二半導體晶粒之該等背表面可自該囊封物偏移一距離,該距離大於10微米。可提供一TIM在該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方,及利用該TIM可將一散熱器耦接至該模製核心單元,該TIM設置在該散熱器與該模製核心單元之間。該精細節距堆積互連結構可直接接該等觸導電互連件。該精細節距堆積互連結構可包含小於3微米之線及空間距離。可將該多層基材形成為高密度堆積(HDBU)基材,其中該核心單元之熱膨脹係數(CTE)係於與該HDBU基材之CTE相差40%內。可平坦化該嵌入式晶粒面板以提供小於或等於10微米之共面性,該等精細節距堆積互連結構形成於該嵌入式晶粒面板上。
在另一態樣中,一種製造FMFOM之方法可包含提供具有導電互連件之一第一半導體晶粒及一第二半導體晶粒。可藉由在單一步驟中囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及該等導電互連件之側表面而形成一嵌入式晶粒面板。藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下可互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元。可將該至少一個模製核心單元安裝至一多層基材。
該製造FMFOM之方法可進一步包含:提供含有黏著劑之一暫時載體,該黏著劑設置在該暫時載體之一頂表面上方;在囊封該第一半導體晶粒及該第二半導體晶粒之前,將該第一半導體晶粒及該第二半導體晶粒面朝上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內;及在囊封該第一半導體晶粒及該第二半導體晶粒之後從該載體移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面。該第一半導體晶粒及該第二半導體晶粒之該等背表面可自該囊封物偏移一距離,該距離大於10微米。可提供一TIM在該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方,及利用該TIM可將一散熱器耦接至該模製核心單元,該TIM設置在該散熱器與該模製核心單元之間。在將該至少一個模製核心單元安裝至該多層基材之前可測試該至少一個模製核心單元之導電性。可將該多層基材形成為HDBU基材,且可將該模製核心單元安裝至具有覆晶凸塊的該HDBU基材,該等覆晶凸塊包含小於或等於15微米之凸塊共面性。在形成該精細節距堆積互連結構之後,可單切該嵌入式晶粒面板,以形成複數個模製核心單元,該複數個模製核心單元包括至少一個模製核心單元。
所屬技術領域中具有通常知識者將可自實施方式與附圖及申請專利範圍清楚瞭解前述及其他態樣、特徵及優點。
本揭露在下文描述中包括一或更多個參考圖式之態樣或實施例,該等圖式中,相似數字表示相同或類似元件。所屬技術領域中具有通常知識者將理解,此描述意欲涵蓋如本揭露之精神及範疇內可包括之替代內容、潤飾、及同等內容,如由所附專利申請範圍及其同等內容所定義,且如由以下揭示內容及圖式支持。在描述中,闡述數個特定細節,如特定組態、組成、及製程等等,以便提供對本揭露之徹底瞭解。在其他情況下,未以特定細節來描述眾所熟知之製程及製造技術,以便不無謂地使本揭露含義模糊。此外,圖式中展示的多項實施例是說明性表示,且並非一定按比例描繪。
本揭露、其態樣及實施方式並不限定於特定設備、材料類型、或其他系統組件實例、或本文中揭示之方法。設想與製造及封裝一致的所屬技術領域中已熟知之許多額外組件、製造及組裝程序,用於搭配來自本揭露之特定實施方案使用。據此,例如,雖然揭示具體實施方案,但是此類實施方案及實施之組件可包含如所屬技術領域中已熟知之用於此類系統及實施之組件的任何組件、型號、類型、材料、版本、量、及/或類似者,該等系統及實施之組件與意圖的操作一致。
本文使用字詞「例示性(exemplary)」、「實例(example)」或其各種形式意指用作為為一實例、案例、或圖解闡釋。本文描述「例示性」或為「實例」之任何態樣或設計非必然視為較佳或優點優於其他態樣或設計。另外,實例僅為了清楚及理解之目的而提供並且非意欲以任何方式限制或限定所揭示之標的物或本揭露之相關部分。應理解,可能已呈現各種不同範疇的許多額外或替代之實例,但是為了簡短目的而省略。
在以下實例、實施例、及實施方式參照實例的情況下,所屬技術領域中具有通常知識者應瞭解,其他製造裝置及實例可與所提供之裝置及實例互混或取代所提供之裝置及實例。在上文描述參考特定實施例之處,應顯而易見,可進行數個修改而不會脫離其精神,並且顯而易見,這些實施例及實施方案亦可應用於其他技術。據此,所揭示之標的物意圖含括所有此類變更、修改及變化,彼等皆落入本揭露之精神及範疇以及所屬技術領域中具有通常知識者之知識內。
大致上而言,使用兩個複雜的製造程序製造半導體裝置:前段製造及後段製造。前段製造涉及形成複數個晶粒於一半導體晶圓之表面上。該晶圓上之各晶粒含有經電連接以形成功能電路之主動電組件及被動電組件。主動電組件(諸如電晶體及二極體)具有控制電流之流動的能力。被動電組件(諸如電容器、電感器、電阻器及變壓器)建立執行電路功能所必須的電壓與電流之間之關係。
藉由一系列程序步驟形成被動組件及主動組件於半導體晶圓之表面上方,包括摻雜、沉積、光學微影、蝕刻、及平坦化。摻雜藉由諸如離子佈植(ion implantation)或熱擴散之技術而引入雜質至半導體材料中。摻雜程序修改主動裝置中的半導體材料之導電性,將半導體材料轉變成絕緣體、導體,或回應於一電場或基極電流而動態變更半導體材料導電性。電晶體含有經配置成所必要的不同類型及摻雜程度之區域,以在施加電場或基極電流時致能電晶體促進或限制電流之流動。
主動組件及被動組件係由具有不同電性質之材料之層所形成。可藉由各式各樣沉積技術來形成層,部分依沉積之材料之類型而決定沉積技術。例如,薄膜沉積可涉及化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解電鍍、及無電解電鍍程序。大致上而言,各層被圖案化以形成主動組件部分、被動組件部分、或介於組件之間之電連接部分。
可使用光學微影將層圖案化,微影涉及沉積光敏材料(例如,光阻)於待圖案化之層上方。使用光將一圖案自一光罩轉移至光阻。在一實施例中,使用溶劑移除光阻圖案之經受光之部分,而暴露待圖案化之下方層之部分。在另一實施例中,使用溶劑移除光阻圖案之未經受光之部分(負光阻),而暴露待圖案化之下方層之部分。移除光阻之其餘部分,留下一經圖案化之層。替代地,一些類型材料係藉由使用諸如無電解及電解電鍍之技術直接沉積該材料於藉由一先前沉積/蝕刻程序所形成之區或空隙中而圖案化。
圖案化係移除半導體晶圓表面上之頂部層之部分的基本操作。可使用光學微影、光罩、遮罩、氧化物或金屬移除、攝影及模板印刷、以及顯微蝕刻(microlithography)來移除半導體晶圓之部分。光學微影包括:形成一圖案於比例光罩(reticle)或一光罩中;及轉移該圖案至半導體晶圓之表面層。光學微影以一兩步驟式程序形成主動及被動組件之水平尺寸於半導體晶圓之表面上。第一步驟係,將比例光罩或光罩之圖案轉移至光阻層上。光阻係在受曝光時經歷結構及性質變更之一光敏材料。變更光阻之結構及性質之程序作為負型作用光阻或正型作用光阻發生。第二步驟係,將光阻層轉移至晶圓表面中。轉移發生在蝕刻移除半導體晶圓之頂部層之未被光阻覆蓋的部分時。光阻之化學使得該光阻實質上維持完好,並且在移除半導體晶圓之頂部層之未被光阻覆蓋之部分的同時,抵抗被化學蝕刻溶液移除。可根據使用的特定光阻及所欲結果,修改形成、曝光及移除光阻之程序,以及修改移除半導體晶圓之一部分的程序。
在負型作用光阻中,光阻被曝光,並且在名為聚合之程序自可溶狀況變更至不可溶狀況。在聚合中,使未聚合材料曝光或暴露於能量源,且聚合物形成交聯材料,該交聯材料係抗蝕劑。在大多數負光阻中,聚合物係聚異戊二烯。用化學溶劑或顯影劑移除可溶部分(即,未被曝光之部分),而在光阻層中留下對應於比例光罩上之不透明圖案的孔洞。圖案存在於不透明區域中的光罩稱為清場光罩(clear-field mask)。
在正型作用光阻中,光阻被曝光且在名為光溶解化(photosolubilization)之程序中自相對非可溶狀況變更至更可溶狀況。在光溶解化中,相對不可溶光阻被曝光於適當的光能量並且轉換成一較可溶狀態。在顯影程序中,可藉由溶劑移除光阻之經光溶解化部分。基本正光阻聚合物係酚-甲醛(phenol-formaldehyde)聚合物,亦稱為酚-甲醛酚醛樹脂。用化學溶劑或顯影劑移除可溶部分(即,被曝光之部分),而在光阻層中留下對應於比例光罩上之透明圖案的孔洞。圖案存在於透明區域中的光罩稱為暗場光罩(dark-field mask)。
在移除半導體晶圓之未被光阻覆蓋之頂部部分之後,移除光阻之其餘部分,而留下一經圖案化之層。替代地,一些類型材料係藉由使用諸如無電解及電解電鍍之技術直接沉積該材料於藉由一先前沉積/蝕刻程序所形成之區或空隙中而圖案化。
沉積材料之一薄膜於一現有圖案上方會增大下方圖案且建立一非均勻平表面。均勻平表面可係有利的或所需的以生產較小及更緻密充填之主動及被動組件。可使用平坦化以自晶圓之表面移除材料且生產均勻平表面。平坦化涉及用拋光墊拋光晶圓之表面。在拋光期間將研磨材料及腐蝕性化學品添加至晶圓之表面。或者,不使用腐蝕性化學品的機械磨蝕用於進行平坦化。在一些實施例中,藉由使用帶研磨機器、標準晶圓磨背機、或其他類似機器而實現純機械磨蝕。組合之研磨機械作用及化學腐蝕作用移除任何不規則形貌,導致均勻平表面。
後段製造係指將晶圓成品切割或單切為個別半導體晶粒,然後封裝半導體晶粒以用於結構支撐及環境隔離。為單切半導體晶粒,可沿晶圓之非功能區域(稱為鋸道(saw street)或劃線)切割晶圓。使用雷射切割工具或鋸刃單切晶圓。在單切之後,將個別半導體晶粒安裝至封裝基材,該基材包括用於與其他系統組件互連之插針或接觸墊。接著,形成於半導體晶粒上方的接觸墊連接至在封裝內之接觸墊。可利用焊料凸塊、椿凸塊、導電膏、重分佈層、或線接合進行電連接。囊封物或其他模製材料沉積於封裝上方,以提供實體支撐及電絕緣。接著,將封裝成品插入於電系統中,並且使半導體裝置之功能可供其他系統組件取用。
電系統可能是使用半導體裝置以執行一或更多個電功能的獨立系統。或者,電系統可以是較大系統之子組件。例如,電系統可以是蜂巢式手機、個人數位助理(PDA)、數位視訊攝影機(DVC)、或其他電子通信裝置中之部分。或者,電系統可以是圖形卡、網路介面卡、或可插入電腦中之其他信號處理卡。半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散裝置、或其他半導體晶粒或電氣組件。微型化及重量減輕對於待被市場接受的產品而言可能是有益的或必要的。半導體裝置之間的距離必須縮短以實現更高密度。
藉由在單一基材上方組合一或更多個半導體封裝,製造商可將預製造組件納入電子裝置及系統。因為半導體封裝包括完善功能性,因此可藉由使用更低成本組件及改進的製造過程製造電子裝置。所產生之裝置極少故障,且製造價格更低,從而使得消費者成本更低。
圖2A至圖2D展示已根據如上文所概述的前段製造方式及程序而形成的複數個半導體晶粒。更特定而言,圖2A展示半導體晶圓、裝置晶圓、或原生晶圓110之頂視圖或平面圖,該晶圓110具有基底基材材料112以用於結構支撐,該材料諸如(但不限定於)矽、鍺、砷化鎵、磷化銦、或碳化矽。複數個半導體晶粒或組件114形成於晶圓110上方,該等晶粒或組件藉由非作用、晶粒間晶圓區域或鋸道116而分隔,如上所述。鋸道116提供切割區域以將半導體晶圓110單切成個別半導體晶粒114。
圖2B展示半導體晶圓110之一部分的橫剖面圖,該圖垂直於圖2A展示之視圖。各半導體晶粒114具有背側或背表面118及與背側相對立的作用表面120。作用表面120含有類比或數位電路,該等電路經實作為形成於晶粒內的主動裝置、被動裝置、導電層、及介電層,且根據晶粒的電氣設計及功能而電互連。例如,電路可包括一或多個電晶體、二極體、及形成於作用表面120內的其他電路元件,以實作類比電路或數位電路,諸如DSP、ASIC、記憶體、或其他信號處理電路。半導體晶粒114亦可含有用於進行射頻信號處理之IPD,諸如電感器、電容器、及電阻器。
藉由使用PVD、CVD、電解電鍍、無電電鍍製程、或其他適合的金屬沉積製程而形成導電層或接觸墊122於作用表面120上方。導電層122可為一更多層鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他適合的導電材料。導電層122作為電耦接或連接至作用表面120上之電路的接觸墊或接合墊而操作。導電層122可形成為與半導體晶粒114之邊緣相距第一距離而並排設置的接觸墊,如圖2B中所示。或者,導電層122可形成為以多列偏移之接觸墊,使得第一列接觸墊設置於與晶粒邊緣相距第一距離處,及與第一列交替之第二列接觸墊設置於與晶粒邊緣相距第二距離處。
圖2C展示等形地施用於作用表面120上方及導電層122上方之可選絕緣或鈍化層126。絕緣層126可包括藉由使用PVD、CVD、絲網印刷、旋塗、噴塗、燒結、熱氧化、或其他適合製程而施用的一或更多個層。絕緣層126可含有但不限於一或多層二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、聚合物、聚醯亞胺、苯并環丁烯(BCB)、聚苯并唑(PBO)、或具有類似絕緣及結構特性的其他材料。或者,半導體晶粒114係在不使用任何PBO層下封裝,且絕緣層126可由不同材料形成,或整個省略。在另一實施例中,絕緣層126包括形成於作用表面120上方(而非設置於導電層122上方)之鈍化層。當存在絕緣層126且絕緣層126形成於導電層122上方時,形成完全穿過絕緣層126之開口以暴露導電層122之至少一部分,以用於後續機械及電互連。或者,當省略絕緣層126時,導電層122經暴露以用於後續電互連,無需形成開口。
圖2C亦展示電互連結構128可形成為椿、圓柱、導柱(pillar)、或柱桿(post),上述各者設置於導電層122上方且耦接或連接至導電層122。可藉由使用圖案化及金屬沉積製程而直接形成互連結構128於導電層122上,該等製程諸如印刷、PVD、CVD、濺射、電解電鍍、無電電鍍、金屬蒸發、金屬濺射、或其他適合的金屬沉積製程。互連結構128可能是一或多層Al、Cu、Sn、Ni、Au、Ag、鈀(Pd)、或其他適合的導電材料,且可包括一或更多個UBM層。在一實施例中,一光阻層沉積於半導體晶粒114及導電層122上方。藉由蝕刻顯影製程暴露及移除光阻層之一部分。藉由使用選擇性電鍍製程,在光阻劑之移除部分中及導電層122上方將電互連結構128形成為導柱或銅導柱。光阻層被移除,留下互連結構128,該等互連結構以提供關於作用表面120及絕緣層126的後續機械及電互連以及支座(standoff)(若存在)。在一些情況下,互連結構128包括範圍自10微米至100微米之高度H1,且可能不含焊料。在其他實例中,互連結構128包括範圍自20微米至50微米之高度。在其他實例中,互連結構128包括約35微米之高度。
圖2C進一步展示晶圓110可經受利用研磨機130之可選研磨操作,以使背表面118平坦化及減小晶圓厚度。亦可使用化學蝕刻以移除及平坦化晶圓110之一部分。
圖2D展示在形成互連結構128及可選地研磨晶圓110之後,藉由使用鋸片或雷射切割工具132穿過鋸道116將晶圓110單切成為個別半導體晶粒114。
圖3A展示含有用於結構支撐的暫時或犧牲性基礎材料之暫時載體或基材136,諸如矽、聚合物、不銹鋼、或其他適合的低成本剛性材料。可選黏著劑、介面層、或雙面膠帶138形成於載體136上方以作為暫時黏合接合膜或蝕刻終止層。在一實施例中,如圖3B中展示,載體136是在膠帶138外圍支撐膠帶的環狀膜框,該框包含中央開口部分。
圖3A進一步展示圖2D中之半導體晶粒114,半導體晶粒114面朝上安裝至載體136及介面層138,該晶粒之背側118經定向朝向基材,且作用表面120經定向背對載體。半導體晶粒114可包含第一半導體晶粒114a及第二半導體晶粒114b,分別而言,第一半導體晶粒114a可專用於或針對特定用途,如邏輯或記憶體;且第二半導體晶粒114b可專用於或針對不同於第一半導體晶粒114a之特定用途,如記憶體或邏輯。半導體晶粒114可藉由使用取放操作或其他適合的操作而置於載體136上方。可選地,黏著劑141設置於半導體晶粒114之背側118與載體136之間。黏著劑141可能是熱環氧化物、環氧樹脂、B-階段環氧薄膜、具有可選丙烯酸聚合物之紫外線B-階段薄膜、或其他適合的材料。在一實施例中,可在將半導體晶粒114安裝在載體136上方之前將黏著劑141設置於背側118上方。或者,可在將半導體晶粒安裝至載體之前將黏著劑141設置於載體136上。在其他實施例中,黏著劑141被省略,且在無需使用黏著劑141下將半導體晶粒114直接安裝至黏著劑138,以使得背側118直接接觸介面層138。當省略黏著劑141時,在囊封第一半導體晶粒114a及第二半導體晶粒114b之前,包括第一半導體晶粒114a及第二半導體晶粒114b之半導體晶粒144之背表面118可陷入載體膠帶138內。
將半導體晶粒114安裝至載體136,使得在將半導體晶粒安裝至載體136上方時藉由空間或間隙140而分隔,空間或間隙140提供用於隨後形成的精細節距堆積互連結構之區域,且可額外包括用於設置在間隙140內的被動組件之空間。間隙140之大小包括充足面積以用於可選地將半導體裝置或組件安裝在隨後形成之嵌入式晶粒面板或模製核心單元內。
圖3C展示藉由使用糊膏印刷、壓縮模製、轉移模製、液態囊封物模製、分層、真空層壓、旋塗、或其他適合的塗施器而沉積囊封物142。具體而言,圖3C展示具有複數個側壁146之模具144,該等側壁與頂部部分或頂板145、載體136、及介面層138組裝在一起,以將半導體晶粒114圍封在模具144內,以用於隨後之囊封。模具144亦可包括底部部分,載體136置於該底部部分上,及側壁146可接觸該底部部分。在一實施例中,載體136及黏著劑138充當底部模具部分,以用於後續囊封製程。或者,半導體晶粒114、載體136、及介面層138可設置在包括多個部分(諸如頂部部分及底部部分)之模具內。藉由圍繞半導體晶粒114移動模具144,或者藉由將半導體晶粒移入模具中而將模具144組裝在一起。
圖3C進一步展示模具144將半導體晶粒114圍封在腔室或開放空間150內。腔室150延伸在模具144至半導體晶粒114與介面層138之間。囊封物142體積設置在半導體晶粒114及載體136上方。入口148可能是排氣埠,該排氣埠具有用於在腔室150中提供真空之可選真空輔助154;然而,入口148不提供用於囊封物142的逸散路徑。囊封物或模製化合物142可能是聚合物複合材料,如含填料之環氧樹脂、含填料之環氧丙烯酸酯、或含適用填料之聚合物。根據腔室150之空間需求減去半導體晶粒114及任何額外可能存在的半導體裝置所佔據的面積而量測囊封物142體積。囊封物142設置於半導體晶粒114上方及側壁146之間。模具144之頂部部分145可沿側壁146移動朝向囊封物142及半導體晶粒114,直至頂部部分接觸囊封物,以使囊封物142在圍繞半導體晶粒114之腔室150內均勻分散及均勻分佈。囊封物142之黏度及高溫可經選擇以用於均勻覆蓋,例如,愈低黏度及高溫可增大用於模製、糊膏印刷、及旋塗之囊封物之流率。亦可在腔室150內控制囊封物142之溫度,以促進囊封物之固化。半導體晶粒一起嵌入囊封物142中以形成面板、塑膠面板、嵌入式晶粒面板、重新建構之面板、重新建構之晶圓、模製面板、或模製晶圓158,囊封物是非導電的且以環保方式保護半導體晶粒114不受外部元件及污染物之影響。因而,可藉由在同一製程中或同時,在單一步驟中利用囊封物142囊封第一半導體晶粒114a之至少四個側表面124及作用表面120、第二半導體晶粒114b、及導電互連件128之側表面127而形成嵌入式晶粒面板158。
圖3D展示類似於針對圖3C中所述製程的囊封製程。圖3D在與圖3C之差異於半導體晶粒114相對於載體136及黏著劑138之取向。圖3D展示一實施例,其中將半導體晶粒114面朝下安裝且作用表面120經定向朝向載體136,而非如圖3C中展示將半導體晶粒114面朝上安裝且作用表面120經定向至背對載體136。因此,可從半導體晶粒114之背表面118上方省略黏著劑141。此外,儘管圖3E至圖3K中後續展示之處理係針對圖3C中繪示的半導體晶粒114之封裝,但後續處理同樣適用於第3D圖中展示的封裝。
在圖3E中,從模具144中移除半導體晶粒114作為面板158之部分,及模製晶圓158能夠可選地經受固化製程,以固化囊封物142。載體136及黏著劑138可立即移除,或在從模具144移除之後不久且在後續處理之前進行移除。或者,載體136、介面層138或兩者可在後續處理之後移除,如在堆積互連結構170形成之後移除。在任何情況下,可藉由化學蝕刻、機械剝離、CMP、機械研磨、熱烘焙、紫外光、雷射掃描、或濕式剝除來移除載體136及介面層138以暴露囊封物142。
囊封物142之前表面或第一表面164可實質上與導電互連件128之端部129共面,如下文更詳細地論述。囊封物142中與第一表面164相對立的背表面或第二表面166可實質上與黏著劑141或半導體晶粒114之背表面118共面。或者,囊封物142之背表面166可相對於半導體晶粒114之背側118實質上不共面或偏移達一距離或偏移量O,此係因為半導體晶粒114陷入或凹陷在黏著劑138內。偏移量O可係大於10微米之距離,且亦可處於10微米至20微米範圍中。可藉由移除載體136及介面層138而暴露囊封物142及半導體晶粒114之背側118兩者。嵌入式晶粒面板158可包括任何形狀及大小的佔用面積或外觀尺寸,該佔用面積或外觀尺寸允許且有利於形成FMFOM所需的後續處理,如下文更詳細地描述。在一實施例中,面板158之一外觀尺寸類似於300毫米(mm)半導體晶圓之外觀尺寸,且面板158包括具有300毫米直徑的圓形佔用面積。然而,亦可使用其他直徑,包括200毫米、400毫米、及任何其他適合大小之直徑。面板158之外觀尺寸或佔用面積亦可是正方形、矩形、或具有任何其他適合之形狀。
圖3E亦展示面板158經受利用研磨機160進行的可選研磨操作,以平坦化表面及縮減面板158之厚度。亦可使用化學蝕刻以移除並平坦化面板158中囊封物142之一部分。因此,互連結構128之表面或端部129相對於囊封物142而暴露,以在半導體晶粒114與後續形成之精細節距堆積互連結構之間提供電連接,該互連結構128之相對附著件附著於接觸墊122。導電互連件128之側面或側壁可沿導電互連件128之高度H1延伸在接觸墊122與端部129之間,側面127被囊封物覆蓋或接觸囊封物。
憑藉從囊封物142中暴露互連件128之端部129,可利用掃描器或成像器168掃描、成像、或以其他方式量測面板159,以判定每一半導體晶粒114及導電互連件128之位置、定向或兩者,如美國專利申請案第14/930,514號及第15/219,025號中所闡述,該申請案之全部揭示內容以引用之方式併入本文。
圖3F展示在模製面板158上方形成堆積互連結構、精細節距堆積互連結構、或高密度多層RDL路由圖案170,以經由導電互連件128而電連接半導體晶粒114,及在諸如半導體晶粒114a及半導體晶粒114b之半導體晶粒114之間提供路由。可在無矽中介層下,藉由在嵌入式晶粒面板158上方形成精細節距堆積互連結構170以形成至少一個核心單元或模製核心單元200而實現第一半導體晶粒114a及第二半導體晶粒114b之導電互連件128的互連。精細節距堆積互連結構170可經形成以直接接觸導電互連件129,如導電互連件128之端部129。如本文中所使用,精細節距堆積互連結構170之間隔或密度可包含少於5微米、少於3微米、及亦少於1微米之線及空間寬度、或節距。
儘管圖3F展示堆積互連結構170經展示包含三個導電層及三個絕緣層,但所屬技術領域中具有通常知識者將理解,可使用更少層或更多層,此取決於FMFOM之組態及設計。可選地,堆積互連結構170包含經形成或設置於重新建構之面板158上的第一絕緣或鈍化層172。第一絕緣層172可包含一或多層SiO2
、Si3
N4
、SiON、Ta2
O5
、Al2
O3
、或具有類似絕緣及結構特性的其他材料。可藉由使用PVD、CVD、印刷、旋塗、噴塗、燒結、或熱氧化而形成絕緣層172。開口或第一層級導電通孔可穿過絕緣層172而形成於導電互連件128上方,以促使與半導體晶粒114連接。
第一導電層174可形成於重新建構之面板158上方及第一絕緣層172上方以作為第一RDL層,以延伸貫穿第一絕緣層172中之開口,以電連接第一層級導電通孔,且電連接導電互連件128。導電層174可能是一或多層Al、Cu、Sn、Ni、Au、Ag、或藉由使用圖案化及金屬沉積製程而形成的其他適合導電材料,該製程諸如濺射、電解電鍍、及無電電鍍、或其他適合的製程。
可類似於或相同於第一絕緣層172之第二絕緣或鈍化層176可設置或形成於重新建構之面板158、第一導電層174、及第一絕緣層172上方。開口或第二層級導電通孔可經形成穿過第二絕緣層176以與第一導電層174連接。
可類似於或相同於第一導電層174之第二導電層178可作為第二RDL層形成於重新建構之面板158上方、第一絕緣層172上方、第一導電層174上方、第二層級導電通孔上方、或第二絕緣層172之開口內,以與第一導電層174、第一層級及第二層級導電通孔、及半導體晶粒114電連接。
可類似於或相同於第一絕緣層172之第三絕緣或鈍化層180可設置或形成於第二導電層178及第二絕緣層176上方。開口或第三層級導電通孔亦可形成於第三絕緣層180中或經形成穿過第三絕緣層180以連接第二導電層178。
第三導電層或UBM 182可形成於第三絕緣層180及第三層級導電通孔上方,以與堆積互連結構170內的其他導電層及導電通孔電連接,且電連接至半導體晶粒114、導電互連件128、及導電互連件52。與由如本文所展示之電鍍製程形成的所有層、電鍍層、或導電層類似的UBM 182可能是多金屬堆疊,該多金屬堆疊包含黏附層、阻障層、種晶層、或潤濕層中之一或多者。黏附層可包含鈦(Ti)、或氮化鈦(TiN)、鎢鈦(TiW)、Al、或鉻(Cr)。阻障層可形成於黏附層上方,且可由Ni、NiV、鉑(Pt)、鈀(Pd)、TiW、或鉻銅(CrCu)製成。在一些實例中,阻障層可能是TiW或Ti濺射層,且可充當黏附層及阻障層。在任一情況下,阻障層可抑制如Cu之材料之不良擴散。種晶層可能是Cu、Ni、NiV、Au、Al、或其他適合的材料。例如,種晶層可能是Cu濺射層,包含約2000埃之厚度(例如2000±600埃)。
如圖3G所示,種晶層可形成於阻障層上方,且可充當後續形成之互連結構、柱桿、導柱、或圓柱184、及凸塊或球狀體186下方的中間導電層。在一些情況下,可在無需互連結構184下形成凸塊186,且潤濕層可包含厚度範圍自約5微米至11微米或7微米至9微米之Cu層。凸塊186(如當由SnAg焊料形成時)可能在回焊期間消耗一些Cu UBM 182,且在焊料凸塊184與潤濕層之Cu之間的界面處形成金屬間化合物。然而,潤濕層之Cu可經製作以具有足夠厚度,該厚度足以防止Cu襯墊在高溫老化期間被焊料消耗殆盡。在一些實例中,UBM 182可包含Ni、Pd、及Au。UBM 182可提供至堆積互連結構170之低電阻互連件,及提供對焊料擴散及種晶層之阻障,以實現焊料可潤濕性。
在形成導電互連件184及凸塊186之後,可在將至少一個模製核心單元200安裝至多層基材、有機基材、有機多層基材、或圖3I中展示的高密度堆積(HDBU)基材210之前,測試至少一個模製核心單元200之導電性。
完成的精細節距互連結構170可包含範圍為5微米至12微米、12微米至25微米、或25微米至70微米的總厚度T1。精細節距互連結構170之平坦度可小於或等於10微米,該平坦度可等於面板158之平坦度。
圖3G亦展示,在形成精細節距互連結構170及互連結構184及凸塊186之後,可藉由使用鋸片或雷射切割工具190穿過鋸道202而單切面板158,以形成一或多個或複數個模製核心單元200。模製核心單元200可包含範圍為0.15毫米至1.1毫米之厚度或高度T2,最大厚度為約1.1毫米及最小厚度為約0.15毫米,其中大約相等之差異百分比可小於或等於20%、10%、或5%。
圖3H展示在從面板158單切核心單元200之前包含複數個核心單元200之面板158的平面圖,如圖3G之剖面視圖中所示。
圖3I展示類似於圖3G中視圖的剖面圖,其中核心單元200安裝至多層基材210。多層基材210可包含數個導電層212及絕緣層214,以用於電信號與模製核心單元200之路由,及由此用於FMFOM 230之組態及設計。導電層212可包含一或多層Al、Cu、Sn、Ni、Au、Ag、或其他類似材料。絕緣層214可包含用於結構支撐之一或多層SiO2
、Si3
N4
、SiON、Ta2
O5
、Al2
O3
、矽、鍺、砷化鎵、磷化銦、碳化矽、聚合物、氧化鈹、或其他適合的剛性材料。或者,絕緣層214可能是預浸漬(預浸)聚四氟乙烯、FR-4、FR-1、CEM-1、或CEM-3的一或多個片壓層,上述各者含有酚醛棉紙、環氧化物、樹脂、玻璃織物、磨砂玻璃、聚酯、及其他強化纖維或織品、或具有類似絕緣及結構特性之其他材料的組合。多層基材210亦可包含一或多個屏蔽墊216,該等屏蔽墊可形成於多層基材210之頂部或第一表面處,且可由一或更多層導電材料形成,該材料包括Al、Cu、Sn、Ni、Au、Ag、或其他類似材料。墊216可提供用於電磁干擾(EMI)屏蔽罩226的位置、安裝位點、或附著點,如圖3K所示。
多層基材210亦可包含藉由使用蒸鍍、電解電鍍、無電電鍍、落球、或絲網印刷製程而形成於基材210上方或附著於基材210的複數個凸塊或球狀體218。凸塊材料可能是具有可選助焊劑溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及上述各者之組合。例如、凸塊材料可係共熔Sn/Pb、高鉛焊料、或無鉛焊料。凸塊材料可藉由使用適合的附著或接合製程而接合至多層基材210,包括導電層212之一部分。在一實施例中,可藉由將凸塊材料加熱至高於其熔點來使凸塊材料回焊,以形成圓形球體或凸塊218。在一些應用中,凸塊218第二次經回焊以改良與多層基材210之電接觸。在一實施例中,凸塊218形成於具有潤濕層、阻障層、及黏著劑層的UBM上方。凸塊218亦可壓縮接合至多層基材210。凸塊218表示一種可形成於多層基材210上方的互連結構。互連結構亦可使用接合線、導電膏、椿凸塊、微凸塊、或其他電互連件。
圖3I亦展示核心單元200可具有暫時載體136,在互連結構170、互連結構184、及凸塊186形成之後,諸如就在安裝核心單元200至多層基材210之前移除暫時載體136。在其他實例中,可在形成面板158之後及形成互連結構170之前移除暫時載體136。隨著暫時載體136被移除,且核心單元200經測試以確保正確操作及無缺陷之後,核心單元200可安裝至多層基材210。在任何情況下,在將至少一個模製核心單元200安裝至多層基材210之前,可測試至少一個模製核心單元200之導電性以確保正確操作及偵測缺陷。當偵測到缺陷時,有缺陷的模製核心單元200可被丟棄或改變用途,而非安裝至多層基材210,從而避免在有缺陷的封裝或組件的生產上耗費額外時間及費用。在一些情況下,將在用鋸件190進行單切之前測試複數個模製核心單元200,以允許並行或同時測試複數個模製核心單元200(諸如在面板158之層級)。
從前,當使用矽中介層時,如用於具有Si中介層之半導體封裝40時,此種測試不可用於封裝40,此係因為在測試期間Si中介層20有可能受損。因而,除非封裝完成及安裝至具有凸塊26的BGA基材30,否則不測試具有Si中介層之習用半導體封裝40。
測試之後,互連結構184及凸塊186可用於將核心單元200覆晶安裝至多層基材210,多層210與互連結構184及凸塊186之間的界面具有小於或等於15微米之凸塊共面性。核心單元200之熱膨脹係數(CTE)可在與多層基材210之CTE相差40%之內。換言之,核心單元200與多層基材210之CTE差異百分比小於或等於40%。
圖3J展示可選的底部充填材料或模製底部充填料(MUF) 220可沉積在核心單元200下方、多層基材上方、或沉積在核心單元200下方及多層基材上方。底部充填材料220可包括環氧化物、環氧樹脂黏著劑材料、聚合材料、薄膜、或其他非導電材料。底部充填料220可能是非導電的及以環保方式保護核心單元200與多層210之間的界面或電互連(諸如保護互連結構184及凸塊186免於外部元件及污染物之影響),及提供結構支撐。在一些實例中,底部充填料220可從貯器泵送至施配針,以使得在壓力下從核心單元200與多層210之間的施配針注入底部充填料220。因為核心單元200之組態及設計及Si中介層(如Si中介層20)之省略,底部充填料220無需設置在半導體晶粒114與TSV基材或Si中介層(如Si中介層20)之間。在一些情況下,真空輔助可吸入MUF 220以協助均勻分佈。底部充填料220可能是聚合物複合材料,如含填料之環氧樹脂、含填料之環氧丙烯酸酯、或含適用填料之聚合物。
圖3K展示於核心單元200上方(包括在第一半導體晶粒114a與第二半導體晶粒114b之偏移背表面118上方)提供或設置熱界面材料(TIM) 224,及利用TIM 224將電磁干擾(EMI)屏蔽罩或散熱器226耦接至模製核心單元200,TIM 224設置在散熱器226與模製核心單元200之間。TIM 224可包含熱環氧化物、熱環氧樹脂、熱導電膏、氧化鋁、氧化鋅、氮化硼、磨碎銀、熱油脂、或其他適合材料。EMI屏蔽罩226可由Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔、導電樹脂、及能夠阻擋或吸收電磁干擾(EMI)、射頻干擾(RFI)、諧波失真、及其他裝置間干擾的其他金屬與複合物而形成。屏蔽罩226亦可是非金屬材料,諸如碳黑或鋁薄片,以降低EMI與RFI效應。藉由利用TIM 224將EMI屏蔽罩226耦接至模製核心單元200,TIM 224設置在EMI屏蔽罩226與模製核心單元200之間,可減少電磁干擾,且可改良FMFOM 230之熱效能。為了提升效能,屏蔽罩226可穿過屏蔽墊216而電連接至外部低阻抗接地點。
圖4展示類似於圖3K中所示的FMFOM 230之FMFOM 240。FMFOM 240不同於FMFOM 230之處在於包括散熱器或熱散片242,而非EMI屏蔽罩226。散熱器242(如同電磁干擾屏蔽罩226)利用TIM 224耦接至模製核心單元200,此TIM 224設置在散熱器242與模製核心單元200之間。散熱器242可能是Cu、Al、或具有高熱導率之其他材料。藉由利用TIM 224將散熱器242耦接至模製核心單元200,TIM 224設置在散熱器242與模製核心單元200之間,可改良FMFOM 240之熱效能。可藉由形成熱導性路徑來改良熱效能,該路徑協助半導體晶粒114所產生之熱的分佈及逸散。
FMFOM 240可在運輸時使半導體晶粒114之背表面118暴露,以便在運輸之後直接附著外部散熱器(諸如散熱器242)。被動組件可整合於多層基材210上或以內,以及整合至模製核心單元200以內。為了獲得增強的機械可靠性、增大的路由密度、及提高的熱穩定性,典型地用於精細節距堆積互連結構170內的晶圓層級重分佈製程的光聚合物(例如PBO或PI)可替換為無機介電質。半導體晶粒114在附著於或置於暫時載體136上之前,可利用晶粒附著材料將半導體晶粒114安裝至熱散片或散熱器(諸如散熱器242)。FMFOM 240亦可藉由使用用於凸塊218之覆晶、LGA、或BGA互連件而直接安裝至系統母板。
如藉由FMFOM 230及240所說明,可在無需諸如Si中介層20之Si中介層下形成FMFOM,同時仍提供穿過精細節距堆積互連結構170的高密度多晶片路由,類似於利用Si中介層達成的裝置間極高配線密度。FMFOM 230、240可包含具有精細節距(40微米)之多層精細節距路由(例如包含2微米線及空間的路由),以及用於高密度晶粒間路由之無焊料Cu椿互連件128。FMFOM 230、240可包含大面積Cu椿128,該等椿可形成於半導體晶片114上及形成於通常連接的晶粒接合墊122上,以獲得改良的熱及功率分佈。單元特殊圖案化(諸如Adaptive PatterningTM)可確保用於FMFOM 230、240之模製中介層170內的半導體晶粒114之間的高互連良率。FMFOM 230、240可包含Cu導柱、用於至多層基材210之覆晶互連件的無Pb焊料凸塊、或兩者。FMFOM 230、240可包含半導體晶粒114之具有偏移量O的暴露背側118,背側118略突出至模製化合物142之背表面166上方,以用於進行優質TIM 224接合線厚度控制。在有利情況下,且不同於利用Si中介層之習用半導體封裝40,FMFOM 230、240之核心單元200可在組裝至高密度多層基材210之前經充分測試。
由於堆積互連結構170之單元特殊圖案化,FMFOM 230、240促進整合不同類型晶片或半導體晶粒(包括不同類型或不同數目的節點),而無需使用Si中介層20,此允許在頂部上的多個不同結構,包括不同晶片類型(記憶體、邏輯、類比),以及在單一核心單元200內不同製程節點(例如130奈米、90奈米、或20奈米)上形成之晶片。堆積互連結構170之高密度路由實現不同記憶體與邏輯半導體晶粒114之間的高速介面。大半導體晶粒114亦可分割為效能損失最小的較小半導體晶粒,以透過更高的晶粒良率而節省晶圓製造成本。核心單元200可將其他主動裝置及被動裝置整合至核心單元200內,從而允許更簡化的PCB設計。因為傳統邏輯晶片包含顯著數量之可重用智慧產權(IP),因此核心單元200內的單獨半導體晶粒114可允許在已證實半導體晶片IP與新IP半導體晶片之間進行拆分或劃分,該新IP包括新增功能性,該功能性可在核心單元200內並排連接。利用FMFOM 230、240設計的晶片設計亦可節省由建置輸入/輸出(I/O)緩衝器及晶片上記憶體所佔用之大量設計及製造成本。
FMFOM 230、240具有優於利用Si中介層40之習用半導體封裝的數個優勢。第一,以習用方式,Si中介層20需要在晶片10與中介層20之間的極精細節距焊料互連件12,與精細間距覆晶10相關聯的Si中介層20組裝良率損失可能是一問題,及微凸塊12的極小焊料接點之可靠性亦可能是一問題。然而,憑藉FMFOM 230、240,便可排除極精細節距焊料接點,且將該等接點替換為精細節距堆積互連結構170內的高密度RDL路由線,諸如直接連接或接觸導電互連件128之導電層174,該等導電互連件可形成為半導體晶粒114上之Cu椿凸塊,而無需使用焊料、微凸塊或兩者。
第二,製造Si中介層20之成本通常可能極高,此係因為必須在先進晶圓製造廠(先進的晶圓加工車間)中執行典型製程。典型地,TSV 22必須形成於中介層20內,覆晶凸塊26必須形成於中介層20底部之上,且TSV製程需要典型厚度約為100微米之極薄Si晶圓20,此可能導致製造時之翹曲及處置問題。憑藉FMFOM 230、240,便可藉由在面板158上使用精細節距堆積互連結構170而完全排除TSV製程,且亦不形成原本通常形成於Si中介層20底部上的焊料凸塊,而是使互連結構184、凸塊186、或兩者同時直接形成於最終路由層上方,諸如形成於面板158上之導電層178,此可實質上降低處理成本及難度。相關而言,在形成FMFOM 230、240時,不執行用於封裝40之半導體晶粒10及微凸塊12的覆晶組裝步驟,且相較之下此步驟已被排除,從而與封裝40相比較,更進一步簡化FMFOM 230、240的封裝組裝製程。
第三,由於Si中介層之翹曲,將半導體晶粒10附著於薄Si中介層20,及進一步將Si中介層20附著於具有習用Si中介層封裝40的BGA基材30之製程可能較為困難。另一方面,利用FMFOM 230、240,精細節距堆積互連結構170內的高密度多層RDL路由圖案174、178可施用於模製面板158內的半導體晶粒114,此為比Si中介層20更穩定的結構,且受翹曲影響更小。
第四,FMFOM 230、240提供額外優勢在於,在半導體晶粒10附著於Si中介層20之後及Si中介層20組裝至昂貴的基材30之前,由於Si中介層20極薄及難以處理,因此一般難以測試包含習用Si中介層20之半導體封裝40是否正常功能。相反,FMFOM 230、240包含嵌入在塑膠面板158內的半導體晶粒114,塑膠面板158有助於在已施用高密度RDL路由170及覆晶凸塊184、186之後及核心單元200組裝至多層基材210之前進行測試。在沒有薄Si中介層20存在之困難的情況下,核心單元200之測試提供降低組裝良率損失的優勢。
第五,在具有Si中介層之半導體封裝40中,具有微凸塊12之覆晶互連件之可靠性具有挑戰性,此係因為Si中介層20之CTE遠低於基材30之CTE,此在溫度循環下產生高應力及應變,導致增加封裝故障。另一方面,FMFOM 230、240包括模製化合物或囊封物142以作為面板158之部分,該部分具有比Si中介層20更高的CTE,導致減少與多層基材210之CTE失配。
相對於FMFOM 230、240,存在優於習用嵌入晶圓層級球狀柵格陣列(eWLB)封裝之數個優勢。eWLB封裝涉及將半導體晶粒面朝下置於膠帶上;在半導體晶粒單元之背表面上方模製或封裝以形成面板或模製面板;然後移除膠帶及於半導體晶粒之作用表面上方形成互連結構,且該互連結構直接接觸該作用表面,以與半導體晶粒之作用表面進行電連接。
第一,eWLB結構典型地包含略壓縮入膠帶內的半導體晶粒,從而在晶粒與扇出封裝之間的界面處產生不均勻表面,該不均勻表面可能導致一構形,該構形需要比在均勻表面之平面上場深度更大之微影製程。所得場深度會限制可應用於面板之RDL的特徵大小。另一方面,在FMFOM製程中,半導體晶粒114可面向上附著於載體膠帶138上,半導體晶粒114之背部有利地壓縮入膠帶138內,不會在作用表面產生偏移量,如上文針對eWLB結構所述。此外,可在模製或囊封半導體晶粒114之後,對包含經囊封半導體晶粒114之塑膠面板158之作用側面進行平坦化,此舉消除偏移及場深度問題,因此可能藉由使用光微影術實現極細線及空間RDL特徵,而不同於面朝下的eWLB方法。如本文所使用,藉由使用更進階微影工具,極細線及空間可包括5微米以下之線及空間、或2微米以下之線及空間,且將可能實現在RDL跡線之間使用無機薄介電層以用於FMFOM 230、240,而此舉在eWLB封裝中是不可能的。
第二,如上所述,典型製備之eWLB模製半導體晶粒的作用表面處之不平坦構形額外為覆晶凸塊提供不平坦表面,此舉可導致覆晶凸塊高度之不均勻性。此可進一步導致在覆晶組裝至基材30期間歸因於開放焊料接點的良率損失。FMFOM 230、240之塑膠面板中的半導體晶粒之平面表面可實現使用覆晶互連件,以將模製核心單元200附著於多層基材210,其中形成於作用側上之覆晶凸塊可具有小於或等於15微米之凸塊共面性,從而產生高良率總成。
第三,在形成eWLB封裝的晶粒面朝下組態中,必須囊封半導體晶粒之整個背部。稍後,可藉由研磨掉模製化合物而暴露eWLB模組中之半導體晶粒,但此方法往往導致模製化合物及半導體晶粒背部共面。共面的模製化合物與半導體晶粒背部使得難以利用可壓縮TIM將散熱器附著於半導體晶粒背部,同時精密控制半導體晶粒背表面上方的TIM厚度。然而,上述問題憑藉FMFOM設計及半導體晶粒114之背表面118與囊封物142之背表面166之間的偏移量O而得到改善。
第四,可藉由FMFOM製程與設計而克服在eWLB模組中與半導體晶粒之背表面相互作用的TIM的問題。對於FMFOM 230、240,在模製面板158與釋放載體136之後,半導體晶粒114之背表面118已暴露以便準備將散熱器226、242安裝至半導體晶粒114之背側118。此外,利用FMFOM 230、240,半導體晶粒114之背側118被壓縮至暫時膠帶138內,以使得半導體晶粒114之背表面118凸起至模製化合物之背表面166上方達一偏移量O,該偏移量O大於或等於10微米、或大於或等於40微米。半導體晶粒114之背表面118與塑膠面板158的囊封物142之對應背表面118之間的偏移量O可允許可壓縮TIM 224在半導體晶粒114與散熱器226、242之間形成一層,該層厚度小於囊封物142之背表面166與散熱器226、242之間的TIM 224之厚度。
第五,FMFOM 230、240包括施用於半導體晶粒114之作用表面120及側面124上方的囊封物142,該囊封物142可包括高於eWLB模組中之對應結構之CTE的CTE。因此,FMFOM 230、240中之更高的CTE將減少翹曲及將在模製核心單元200與多層基材210之間的互連件184、186上產生更少應力及應變,該應力及應變少於在具有Si中介層40的習用模組中之Si中介層20與基材30之間的凸塊26上之應力及應變。
第六,FMFOM 230、240之進一步優勢可包括將導電互連件128與184之大小及密度特製為椿,以縮減大小及在半導體晶粒114與導電互連件128及184之間產生更低熱阻,此舉可在一些特定實例中藉由產生更大面積的導電互連件128及184而實現,該等導電互連件通常連接至電力及接地網。
圖5展示一繪示形成熱增強型FMFOM 230之一方法的非限制性實例之流程圖300,如圖1A至圖4中所繪示及描述,且在要素302至要素326中進一步展示,且在下文於流程圖300中所述的以下操作、步驟、或製程中進行描述。圖5中所列之此等要素、操作、或步驟可以展示之次序或順序執行,但非必須。在不脫離本揭露之精神及範疇的前提下,可修正流程圖300中所含之更少要素、及多個要素的次序或順序。
要素302表示在半導體裝置晶圓110上電鍍導電互連件128,如圖2C所示。要素304表示將晶圓110薄化至成品矽厚度,如圖2C所示。要素306表示單切半導體晶粒114,如圖2D所示。要素308表示利用順應性黏著劑138將半導體晶粒114面朝上置於暫時載體136上,及將半導體晶粒114壓入黏著劑材料138,如圖3A所示。要素310表示利用囊封物或模製材料142模製半導體晶粒114以形成嵌入式晶粒面板或塑膠面板158,如至圖3E圖3C圖3E所示。要素312表示移除載體136以暴露模製半導體晶粒114之背部118,如圖3E至圖3I所示。要素314表示研磨面板158之前側164以暴露導電互連件128,如圖3E所示。要素316表示掃描面板156以量測各晶粒114之位置及取向,如圖3E所示。要素318表示使用單元特殊圖案化或Adaptive PatterningTM來施加高密度多層RDL路由圖案170(如圖3E所示),以使RDL圖案170對準各半導體晶粒114(如半導體晶粒114a及半導體晶粒114b)。要素320表示在路由170上方電鍍覆晶凸塊,如圖3G所示。要素322表示將面板158單切為核心單元200,如圖3G所示。要素324表示測試個別全模製核心單元200。要素326表示藉由使用覆晶互連件而將全模製核心單元200組裝至多層基材210上,如圖3I所示。
在前述說明中,已描述本揭露之多個實施例。然而,將顯而易見,可在不脫離本發明之更廣泛精神及範疇的情況下對該等實施例進行多個潤飾及變更,如所附專利申請範圍中所闡述。因此,本說明書及圖式將被視作具有說明性含義,而非限制性含義。
10‧‧‧半導體晶粒/晶片/覆晶
12‧‧‧微凸塊/凸塊/球體/互連件
14‧‧‧背表面
20‧‧‧Si中介層/Si晶圓/中介層
22‧‧‧Si穿孔/TSV
24‧‧‧路由層/重分佈層
26‧‧‧覆晶凸塊/C4凸塊/凸塊
30‧‧‧基材/封裝基材/封裝/多層有機球狀柵格陣列(BGA)基材/BGA基材
32‧‧‧球狀柵格陣列凸塊/焊球
40‧‧‧半導體封裝/封裝
110‧‧‧晶圓/半導體晶圓/裝置晶圓/原生晶圓
112‧‧‧基底基材材料
114‧‧‧半導體晶粒/組件/晶粒
114a‧‧‧第一半導體晶粒
114b‧‧‧第二半導體晶粒
116‧‧‧鋸道
118‧‧‧背表面/背側
120‧‧‧作用表面
122‧‧‧導電層/接觸墊/晶粒接合墊
124‧‧‧側表面/側面
126‧‧‧絕緣層/鈍化層
127‧‧‧側表面/側面
128‧‧‧導電互連件/互連件/Cu椿互連件/Cu椿/互連結構/電互連結構
129‧‧‧表面/端部/導電互連件
130‧‧‧研磨機
132‧‧‧鋸片/雷射切割工具
136‧‧‧暫時載體/基材/載體
138‧‧‧黏著劑/介面層/雙面膠帶/膠帶/載體膠帶/黏著劑材料
140‧‧‧空間/間隙
141‧‧‧黏著劑
142‧‧‧囊封物/模製化合物
144‧‧‧模具
145‧‧‧頂部部分/頂板
146‧‧‧側壁
148‧‧‧入口
150‧‧‧腔室/開放空間
154‧‧‧真空輔助
158‧‧‧面板/塑膠面板/嵌入式晶粒面板/重新建構之面板/重新建構之晶圓/模製面板/模製晶圓/嵌入式晶粒面板
160‧‧‧研磨機
164‧‧‧前表面/第一表面/前側
166‧‧‧背表面/第二表面
168‧‧‧成像器
170‧‧‧高密度多層RDL路由圖案/堆積互連結構/互連結構/模製中介層/RDL圖案/路由/高密度RDL路由
172‧‧‧絕緣層/鈍化層
174‧‧‧導電層
176‧‧‧絕緣層/鈍化層
178‧‧‧導電層/高密度多層RDL路由圖案
180‧‧‧絕緣層/鈍化層
182‧‧‧導電層/UBM
184‧‧‧互連結構/柱桿/導柱/圓柱/互連件/導電互連件/焊料凸塊/覆晶凸塊
186‧‧‧凸塊/球狀體/覆晶凸塊/互連件
190‧‧‧鋸片/雷射切割工具
200‧‧‧模製核心單元/核心單元
202‧‧‧鋸道
210‧‧‧多層基材/有機基材/有機多層基材/高密度堆積(HDBU)基材/多層
212‧‧‧導電層
214‧‧‧絕緣層
216‧‧‧屏蔽墊/墊
218‧‧‧凸塊/球狀體
220‧‧‧底部充填材料/模製底部充填料/底部充填料/MUF
224‧‧‧熱界面材料/TIM
226‧‧‧電磁干擾(EMI)屏蔽罩/散熱器/屏蔽罩
230‧‧‧FMFOM
240‧‧‧FMFOM
242‧‧‧散熱器/熱散片
300‧‧‧流程圖
302‧‧‧步驟
304‧‧‧步驟
306‧‧‧步驟
308‧‧‧步驟
310‧‧‧步驟
312‧‧‧步驟
314‧‧‧步驟
316‧‧‧步驟
318‧‧‧步驟
320‧‧‧步驟
322‧‧‧步驟
324‧‧‧步驟
326‧‧‧步驟
H1‧‧‧高度
O‧‧‧偏移量
T1‧‧‧總厚度
T2‧‧‧厚度
圖1A及圖1B展示具有矽中介層之半導體封裝,如先前技術中已知。
圖2A至圖2D展示從原生晶圓處理半導體晶粒之一態樣。
圖3A至圖3K展示FMFOM形成之一態樣。
圖4展示熱增強型FMOM之一態樣。
圖5展示形成FMOM時所包括的要素之流程圖。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
(請換頁單獨記載) 無
Claims (20)
- 一種製造一全模製扇出模組(FMFOM)之方法,其包含:提供一暫時載體,該暫時載體包含設置於該暫時載體之一頂表面上方的黏著劑;提供一第一半導體晶粒,該第一半導體晶粒包含耦接至該第一半導體晶粒之一作用表面的導電互連件;提供一第二半導體晶粒,該第二半導體晶粒包含耦接至該第二半導體晶粒之一作用表面的導電互連件;在囊封該第一半導體晶粒及該第二半導體晶粒之前,將該第一半導體晶粒及該第二半導體晶粒面向上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內;在單一步驟中形成一嵌入式晶粒面板,這是藉由下述方式達成:利用囊封物囊封該第一半導體晶粒之至少四個側表面及該作用表面、該第二半導體晶粒,且進一步囊封該第一半導體晶粒與該第二半導體晶粒的該等導電互連件之各者的至少兩個側表面;藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元;移除該暫時載體;將該至少一個模製核心單元安裝至一有機多層基材;及利用一熱界面材料(TIM)將一散熱器耦接至該模製核心單元,該熱界面材料設置於該散熱器與該模製核心單元之間。
- 如請求項1之方法,其進一步包含在囊封該第一半導體晶粒及該第二半導體晶粒之後從該黏著劑移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面,其中該第一半導體晶粒及該第二半導體晶粒之該等背表面自該囊封物偏移一距離,該距離大於10μm(微米)。
- 如請求項2之方法,其進一步包含:提供該TIM於該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方;及利用設置在該散熱器與該模製核心單元之間之該TIM將該散熱器耦接至該模製核心單元。
- 如請求項1之方法,其中該等導電互連件形成為銅椿,及該等導電互連件進一步包含10微米至100微米之高度,且不含焊料。
- 如請求項1之方法,其中該精細節距堆積互連結構直接接觸該等導電互連件。
- 如請求項1之方法,其中該精細節距堆積互連結構包含小於3微米之線及空間距離。
- 如請求項1之方法,其進一步包含在將該至少一個模製核心單元安裝至該有機多層基材之前測試該至少一個模製核心單元之導電性。
- 一種製造一全模製扇出模組(FMFOM)之方法,其包含:提供一暫時載體,該暫時載體包含設置於該暫時載體之一頂表面上方的黏著劑;在囊封該第一半導體晶粒及該第二半導體晶粒之前,將一第一半導體晶粒及一第二半導體晶粒面向上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內;藉由在單一步驟中囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及耦接至該第一半導體晶粒及該第二半導體晶粒之複數個導電互連件之各者的一側表面而形成一嵌入式晶粒面板;藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元;移除該暫時載體;及將該至少一個模製核心單元安裝至一多層基材。
- 如請求項8之方法,其進一步包含:在囊封該第一半導體晶粒及該第二半導體晶粒之前,將該第一半導體晶粒及該第二半導體晶粒面向上安裝至該載體;及在囊封該第一半導體晶粒及該第二半導體晶粒之後從該載體移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面,其中該第一半導體晶粒及該第二半導體晶粒之該等背表面自該囊封物偏移一距離,該距離大於10微米。
- 如請求項9之方法,其進一步包含:提供一熱界面材料(TIM)於該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方;及利用該TIM將一散熱器耦接至該模製核心單元,該TIM設置在該散熱器與該模製核心單元之間。
- 如請求項8之方法,其中該精細節距堆積互連結構直接接觸該等導電互連件。
- 如請求項8之方法,其中該精細節距堆積互連結構包含小於3微米之線及空間距離。
- 如請求項8之方法,其進一步包含將該多層基材形成為一高密度堆積(HDBU)基材,其中該模製核心單元之熱膨脹係數(CTE)係於與該HDBU基材之CTE相差40%以內。
- 如請求項8之方法,其進一步包含平坦化該嵌入式晶粒面板,以提供小於或等於10微米之共面性,該精細節距堆積互連結構形成於該嵌入式晶粒面板上。
- 一種製造一全模製扇出模組(FMFOM)之方法,其包含:提供具有導電互連件之一第一半導體晶粒及一第二半導體晶粒;藉由在單一步驟中囊封該第一半導體晶粒之至少四個側表面及一作用表面、該第二半導體晶粒、及該等導電互連件之各者的至少兩個側表面而形成一嵌入式晶粒面板;藉由形成一精細節距堆積互連結構在該嵌入式晶粒面板上方,以在無一矽中介層下互連該第一半導體晶粒及該第二半導體晶粒之該等導電互連件,而形成至少一個模製核心單元;及將該至少一個模製核心單元安裝至一多層基材。
- 如請求項15之方法,其進一步包含:提供一暫時載體,該暫時載體包含設置於該暫時載體之一頂表面上方的黏著劑;在囊封該第一半導體晶粒及該第二半導體晶粒之前,將該第一半導體晶粒及該第二半導體晶粒面向上安裝至該暫時載體,使得該第一半導體晶粒及該第二半導體晶粒之背表面陷入該黏著劑內;及在囊封該第一半導體晶粒及該第二半導體晶粒之後從該載體移除該第一半導體晶粒及該第二半導體晶粒,以暴露該第一半導體晶粒及該第二半導體晶粒之該等背表面,其中該第一半導體晶粒及該第二半導體晶粒之該等背表面自該囊封物偏移一距離,該距離大於10微米。
- 如請求項16之方法,其進一步包含:提供一熱界面材料(TIM)於該第一半導體晶粒及該第二半導體晶粒之該等偏移背表面上方;及利用該TIM將一散熱器耦接至該模製核心單元,該TIM設置在該散熱器與該模製核心單元之間。
- 如請求項15之方法,其進一步包含在將該至少一個模製核心單元安裝至該多層基材之前測試該至少一個模製核心單元之導電性。
- 如請求項15之方法,其進一步包含:將該多層基材形成為一高密度堆積(HDBU)基材;及將該模製核心單元安裝至具有覆晶凸塊的該HDBU基材,該等覆晶凸塊包含小於或等於15微米之凸塊共面性。
- 如請求項15之方法,其進一步包含:在形成該精細節距堆積互連結構之後單切該嵌入式晶粒面板,以形成複數個模製核心單元,該複數個模製核心單元包括該至少一個模製核心單元。
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US20180261586A1 (en) | 2018-09-13 |
TW201812938A (zh) | 2018-04-01 |
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CN108028225B (zh) | 2022-06-07 |
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WO2017049269A1 (en) | 2017-03-23 |
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KR20180051611A (ko) | 2018-05-16 |
TW201921530A (zh) | 2019-06-01 |
TWI716732B (zh) | 2021-01-21 |
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