TWI614893B - 串聯式電晶體結構及其製造方法 - Google Patents
串聯式電晶體結構及其製造方法 Download PDFInfo
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- TWI614893B TWI614893B TW104106267A TW104106267A TWI614893B TW I614893 B TWI614893 B TW I614893B TW 104106267 A TW104106267 A TW 104106267A TW 104106267 A TW104106267 A TW 104106267A TW I614893 B TWI614893 B TW I614893B
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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Abstract
一種串聯式電晶體結構包含第一源極、第一通道-汲極結構、第二通道-汲極結構、閘介電層、閘極、第一汲極墊及第二汲極墊。第一源極位於基材上。第一通道-汲極結構位於第一源極上,且包含第一通道及位於其上的第一汲極。第二通道-汲極結構位於第一源極上,並大致上與第一通道-汲極結構平行,且包含第二通道及位於其上的第二汲極。閘介電層圍繞第一通道及第二通道。閘極圍繞閘介電層。第一汲極墊位於第一汲極上,並接觸第一汲極。第二汲極墊位於第二汲極上,並接觸第二汲極,其中第一汲極墊與第二汲極墊彼此分離。
Description
本發明係有關於一種串聯式電晶體結構及其製造方法。
半導體元件根據其功能可分為I/O元件及核心元件,其中I/O元件及核心元件一般包含水平式電晶體。由於施加在I/O元件的電壓比施加在核心元件的電壓更高,因此I/O元件的水平式電晶體的閘極長度和閘介電層厚度需比核心元件的閘極長度和閘介電層厚度更大,導致其佔據區域大且集成密度差。
為了改善集成密度,在I/O元件與核心元件中,可使用具有相同閘極長度的垂直式電晶體。然而垂直式電晶體的閘極長度與通道長度比水平式電晶體的閘極長度與通道長度更短,因此當施加高電壓在I/O元件的垂直式電晶體時,可能會發生汲極感應勢壘降低(drain induced barrier lowering,DIBL)及熱載子注入(hot carrier injection,HCI)現象,使得漏電流增加,可靠度明顯下降。因此,持
續尋求改善I/O元件的垂直式電晶體的方法。
本發明提供一種串聯式電晶體結構,包含第一源極、第一通道-汲極結構、第二通道-汲極結構、閘介電層、閘極、第一汲極墊及第二汲極墊。第一源極位於基材上。第一通道-汲極結構位於第一源極上,第一通道-汲極結構包含第一通道及第一汲極位於第一通道上。第二通道-汲極結構位於第一源極上,並大致上與第一通道-汲極結構平行。第二通道-汲極結構包含第二通道及第二汲極位於第二通道上。閘介電層圍繞第一通道及第二通道。閘極圍繞閘介電層。第一汲極墊位於第一汲極上,並接觸第一汲極。第二汲極墊位於第二汲極上,並接觸第二汲極,其中第一汲極墊與第二汲極墊彼此分離。
本發明另提供一種串聯式電晶體結構,包含第一源極、第二源極、隔離部分、第二通道-汲極結構、第三通道-汲極結構、閘介電層、閘極及第二汲極墊。第一源極位於基材上。第二源極位於基材上,且側向鄰接第一源極。隔離部分位於第一源極與第二源極之間,以電性隔離第一源極與第二源極。第二通道-汲極結構位於第一源極上,第二通道-汲極結構包含第二通道及第二汲極位於第二通道上。第三通道-汲極結構位於第二源極上,並大致上與第二通道-汲極結構平行。第三通道-汲極結構包含第三通道及第三汲極位於第三通道上。閘介電層圍繞第二通道及第三通道。閘
極圍繞閘介電層。第二汲極墊位於第二汲極及第三汲極上,並接觸第二汲極及第三汲極。
本發明又提供一種製造串聯式電晶體結構的方
法,包含:形成串聯式源極-通道-汲極結構突出基材,串聯式源極-通道-汲極結構包含第一源極位於基材上、第一通道-汲極結構位於第一源極上及第二通道-汲極結構位於第一源極上,第一通道-汲極結構大致上與第二通道-汲極結構相互平行,或者串聯式源極-通道-汲極結構包含第一源極、第二源極位於基材上且側向鄰接第一源極、隔離部分位於第一源極與第二源極之間、第二通道-汲極結構位於第一源極上及第三通道-汲極結構位於第二源極上,第二通道-汲極結構大致上與第三通道-汲極結構相互平行;形成源極介電層於第一源極上,或者於第一源極與第二源極上;形成閘介電層圍繞第一通道-汲極結構之通道與第二通道-汲極結構之通道,或者圍繞第二通道-汲極結構之通道與第三通道-汲極結構之通道;形成閘極於源極介電層上,並圍繞閘介電層;以及分別形成第一汲極墊與第二汲極墊於第一通道-汲極結構之汲極與第二通道-汲極結構之汲極上,並接觸第一通道-汲極結構之汲極與第二通道-汲極結構之汲極,或者形成第二汲極墊於第二通道-汲極結構之汲極與第三通道-汲極結構之汲極上,並接觸第二通道-汲極結構之汲極與第三通道-汲極結構之汲極。
110‧‧‧基材
120‧‧‧隔離部分
110a‧‧‧I/O區
130‧‧‧閘介電層
140‧‧‧源極介電層
150‧‧‧高介電常數介電層
160‧‧‧層間介電層
210‧‧‧層間介電層
C1‧‧‧第一通道
C2‧‧‧第二通道
C3‧‧‧第三通道
C4‧‧‧第四通道
CDS1‧‧‧第一通道-汲極結構
CDS2‧‧‧第二通道-汲極結構
CDS3‧‧‧第三通道-汲極結構
CDS4‧‧‧第四通道-汲極結構
CL‧‧‧通道層
D1‧‧‧第一汲極
D2‧‧‧第二汲極
D3‧‧‧第三汲極
D4‧‧‧第四汲極
DL‧‧‧汲極層
DP1‧‧‧第一汲極墊
DP2‧‧‧第二汲極墊
DPL1‧‧‧第一汲極墊層
DPL2‧‧‧第二汲極墊層
G‧‧‧閘極
HM‧‧‧硬遮罩層
P‧‧‧導電插塞
P1‧‧‧第一導電插塞
P2‧‧‧第二導電插塞
P3‧‧‧第三導電插塞
S1‧‧‧第一源極
S2‧‧‧第二源極
SL‧‧‧源極層
SSR‧‧‧源極矽化物區
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。
第2圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。
第3圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。
第4圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。
第5圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。
第6A-6F圖繪示根據本發明多個實施例之一種製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。
第7A-7G圖繪示根據本發明多個實施例之一種製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。
第8A-8G圖繪示根據本發明多個實施例之一種製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。
以下提供本發明之多種不同的實施例或實例,以實現所提供之標的的不同技術特徵。下述具體實例的元件和設計用以簡化本發明。當然,這些僅為示例,而非用以限定本發明。舉例而言,說明書中揭示形成第一特徵結構於第二特徵結構之上方,其包括第一特徵結構與第二特徵結構形
成而直接接觸的實施例,亦包括於第一特徵結構與第二特徵結構之間另有其他特徵結構的實施例,亦即,第一特徵結構與第二特徵結構並非直接接觸。此外,本發明於各個實例中可能用到重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述結構之間的關係。
另外,空間相對用語,如「下」、「上」等,
是用以方便描述一元件或特徵與其他元件或特徵在圖式中的相對關係。這些空間相對用語旨在包含除了圖式中所示之方位以外,裝置在使用或操作時的不同方位。裝置可被另外定位(例如旋轉90度或其他方位),而本文所使用的空間相對敘述亦可相對應地進行解釋。
如上所述,當施加高電壓在垂直式電晶體時,
可能會發生汲極感應勢壘降低及熱載子注入現象,使得漏電流增加,可靠度明顯下降。為了解決此問題,提供一種用以分配電壓(例如汲極-源極電壓(Vds))的串聯式電晶體結構,其可有效降低或避免汲極感應勢壘降低及熱載子注入現象,從而降低漏電流及改善可靠度。以下詳細敘述串聯式電晶體結構及其製造方法的實施例。
第1圖繪示根據本發明多個實施例之一種串聯式電晶體結構的剖面示意圖。串聯式電晶體包含第一源極S1、第一通道-汲極結構CDS1、第二通道-汲極結構CDS2、閘介電層130、閘極G、第一汲極墊DP1及第二汲極墊DP2。在數個實施例中,串聯式電晶體結構位於I/O元件內。在數
個實施例中,串聯式電晶體結構位於核心元件內。
第一源極S1位於基材110上。在數個實施例
中,基材110包含元素半導體,其包括矽或鍺的結晶、多晶或無定形結構;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和銻化銦;合金半導體,包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦;任何其他合適的材料;或其組合。在數個實施例中,基材110包含一導電型的井區(未繪示)自基材110表面延伸至基材110內,此井區的導電型與第一源極S1的導電型不同。在數個實施例中,第一源極S1位於井區上,並接觸井區。在數個實施例中,基材110具有I/O區110a與核心區(未繪示),且第一源極S1位於基材110的I/O區110a上。
在數個實施例中,第一源極S1是一導電型的重
摻雜層。在數個實施例中,第一源極S1是n型重摻雜層。在數個實施例中,第一源極S1是n型重摻雜層,井區是p型井區。在數個實施例中,第一源極S1包含n型摻質,例如磷、砷、銻、鉍、硒、碲、其他合適的n型摻質或其組合。在數個實施例中,串聯式電晶體結構更包含源極矽化物區SSR位於第一源極S1內,以降低第一源極S1的電阻。換言之,源極矽化物區SSR可被視為第一源極S1的一部分。在數個實施例中,第一源極S1包含多個源極矽化物區SSR彼此間隔。
第一通道-汲極結構CDS1位於第一源極S1
上。第一通道-汲極結構CDS1包含第一通道C1及位於第一
通道C1上的第一汲極D1。在數個實施例中,第一通道C1為一導電型的摻雜層,此導電型與第一源極S1的導電型相同。在數個實施例中,第一汲極D1為一導電型的重摻雜層,此導電型與第一源極S1的導電型相同。
第二通道-汲極結構CDS2也位於第一源極S1
上,並且大致上與第一通道-汲極結構CDS1平行。第二通道-汲極結構CDS2包含第二通道C2及位於第二通道C2上的第二汲極D2。在數個實施例中,第二通道C2為一導電型的摻雜層,此導電型與第一源極S1的導電型相同。在數個實施例中,第二汲極D2為一導電型的重摻雜層,此導電型與第一源極S1的導電型相同。在數個實施例中,第一通道-汲極結構CDS1與第二通道-汲極結構CDS2為垂直奈米線結構。
閘介電層130圍繞第一通道C1及第二通道
C2。在數個實施例中,閘介電層130包含一介電材料,如二氧化矽、氮化矽、氮氧化矽或其他合適的介電材料。閘極G圍繞閘介電層130。換言之,串聯式電晶體結構屬於垂直式閘極全圍繞(vertical gate-all-around)電晶體。在數個實施例中,閘極G包含一導電材料,如多晶矽(poly)、金屬或金屬合金。
第一汲極墊DP1位於第一汲極D1上,並接觸第一汲極D1,第二汲極墊DP2位於第二汲極D2上,並接觸第二汲極D2。第一汲極墊DP1與第二汲極墊DP2彼此分離。在數個實施例中,第一汲極墊DP1與第二汲極墊DP2包含金
屬、矽化物或其他導電材料。當施加高電壓在第一汲極墊DP1或第二汲極墊DP2時,電壓會透過第一源極S1而被分配到第一通道-汲極結構CDS1與第二通道-汲極結構CDS2,如第1圖的虛線所示。在數個實施例中,串聯式電晶體結構包含多個第一通道-汲極結構CDS1與多個第二通道-汲極結構CDS2,第一汲極墊DP1位於多個第一汲極D1上,並接觸這些第一汲極D1,第二汲極墊DP2位於多個第二汲極D2上,並接觸這些第二汲極D2。當施加高電壓在第一汲極墊DP1或第二汲極墊DP2時,電壓會透過第一源極S1而被分配到這些第一通道-汲極結構CDS1與這些第二通道-汲極結構CDS2。在數個實施例中,這些第一通道-汲極結構CDS1與這些第二通道-汲極結構CDS2為垂直奈米線結構。
在數個實施例中,垂直式電晶體結構更包含一
源極介電層140位於第一源極S1與閘極G之間,以使第一源極S1與閘極G之間電性隔離。在數個實施例中,源極介電層140包含介電材料,例如二氧化矽、氮化矽、氮氧化矽或其他合適的介電材料。
在數個實施例中,串聯式電晶體結構更包含高
介電常數(highk)介電層150位於閘介電層130與閘極G之間,以及源極介電層140與閘極G之間。在數個實施例中,高介電常數介電層150包含HfO2、ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、SrTiO或其組合。
在數個實施例中,串聯式電晶體結構更包含層
間介電層(ILD)160覆蓋閘極G且暴露出第一汲極D1的上表面與第二汲極D2的上表面。第一汲極墊DP1與第二汲極墊DP2位於層間介電層160上,且分別接觸第一汲極D1與第二汲極D2。在數個實施例中,串聯式電晶體結構更包含另一層間介電層210位於第一汲極墊DP1與第二汲極墊DP2上。在數個實施例中,層間介電層160,210係由氧化矽、氮氧化矽及/或其他合適的絕緣材料製成。在數個實施例中,串聯式電晶體結構更包含二個導電插塞P穿透層間介電層210,此二個導電插塞P分別連接第一汲極墊DP1與第二汲極墊DP2。在數個實施例中,導電插塞P包含金屬、金屬化合物或其組合,例如鈦、鉭、鎢、鋁、銅、鉬、鉑、氮化鈦、氮化鉭、碳化鉭、氮化鉭矽、氮化鎢、氮化鉬、氮氧化鉬、氧化钌、鈦鋁、氮化鈦鋁、碳氮化鉭、其組合或其他合適的材料。
第2圖繪示根據本發明多個實施例之一種串聯
式電晶體結構的剖面示意圖。串聯式電晶體結構包含第一源極S1、第二源極S2、隔離部分120、第二通道-汲極結構CDS2、第三通道-汲極結構CDS3、閘介電層130、閘極G及第二汲極墊DP2。在數個實施例中,串聯式電晶體結構位於I/O元件內。在數個實施例中,串聯式電晶體結構位於核心元件內。
第一源極S1位於基材110上。第二源極S2亦位
於基材110上,且側向鄰接第一源極S1。在數個實施例中,
基材110具有I/O區110a與核心區(未繪示),且第一源極S1與第二源極S2皆位於基材110的I/O區110a上。在數個實施例中,第一源極S1與第二源極S2是相同導電型的重摻雜層。在數個實施例中,第一源極S1與第二源極S2是n型重摻雜層。在數個實施例中,第一源極S1是n型重摻雜層。在數個實施例中,第一源極S1與第二源極S2是由同一層製造而得。在數個實施例中,串聯式電晶體結構更包含多個源極矽化物區SSR位於第一源極S1與第二源極S2內。
隔離部分120位於第一源極S1與第二源極S2
之間,以使第一源極S1與第二源極S2之間電性隔離。在數個實施例中,隔離部分120為淺溝渠隔離(STI)。在數個實施例中,隔離部分120包含氧化矽、氮化矽、氮氧化矽、低介電常數之介電材料和/或其組合。
第二通道-汲極結構CDS2位於第一源極S1
上。第二通道-汲極結構CDS2包含第二通道C2及位於第二通道C2上的第二汲極D2。在數個實施例中,第二通道C2為一導電型的摻雜層,此導電型與第一源極S1的導電型相同。在數個實施例中,第二汲極D2為一導電型的重摻雜層,此導電型與第一源極S1的導電型相同。
第三通道-汲極結構CDS3位於第二源極S2
上,並且大致上與第二通道-汲極結構CDS2平行。第三通道-汲極結構CDS3包含第三通道C3及位於第三通道C3上的第三汲極D3。在數個實施例中,第三通道C3為一導電型的摻雜層,此導電型與第二源極S2的導電型相同。在數個
實施例中,第三汲極D3為一導電型的重摻雜層,此導電型與第二源極S2的導電型相同。在數個實施例中,第二通道-汲極結構CDS2與第三通道-汲極結構CDS3為垂直奈米線結構。
閘介電層130圍繞第二通道C2及第三通道
C3。在數個實施例中,閘介電層130包含一介電材料,如二氧化矽、氮化矽、氮氧化矽或其他合適的介電材料。閘極G圍繞閘介電層130。在數個實施例中,閘極G包含一導電材料,如多晶矽(poly)、金屬或金屬合金。
第二汲極墊DP2位於第二汲極D2與第三汲極
D3上,並接觸第二汲極D2與第三汲極D3。在數個實施例中,第二汲極墊DP2包含金屬、矽化物或其他導電材料。矽化物可為矽化鈷、矽化鈦、矽化鎢、矽化鎳或其組合。當施加高電壓在第一源極S1或第二源極S2時,電壓會透過第二汲極墊DP2而被分配到第二通道-汲極結構CDS2與第三通道-汲極結構CDS3,如第2圖的虛線所示。在數個實施例中,串聯式電晶體結構包含多個第二通道-汲極結構CDS2位於第一源極S1上及多個第三通道-汲極結構CDS3位於第二源極S2上,第二汲極墊DP2位於多個第二汲極D2與多個第三汲極D3上,並接觸這些第二汲極D2與這些第三汲極D3。當施加高電壓在第一源極S1或第二源極S2時,電壓會透過第二汲極墊DP2而被分配到這些第二通道-汲極結構CDS2與這些第三通道-汲極結構CDS3。在數個實施例中,這些第二通道-汲極結構CDS2與這些第三通道-汲極結構
CDS3為垂直奈米線結構。
在數個實施例中,串聯式電晶體結構更包含源
極介電層140位於第一源極S1與閘極G之間,以及第二源極S2與閘極G之間。在數個實施例中,源極介電層140包含介電材料,例如二氧化矽、氮化矽、氮氧化矽或其他合適的介電材料。
在數個實施例中,串聯式電晶體結構更包含高
介電常數介電層150位於閘介電層130與閘極G之間,及源極介電層140與閘極G之間。在數個實施例中,高介電常數介電層150包含HfO2、ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、SrTiO或其組合。
在數個實施例中,串聯式電晶體結構更包含層
間介電層160覆蓋閘極G且暴露出第二汲極D2的上表面及第三汲極D3的上表面。第二汲極墊DP2位於層間介電層160上,並接觸第二汲極D2與第三汲極D3。在數個實施例中,串聯式電晶體結構更包含另一層間介電層210位於第二汲極墊DP2上。在數個實施例中,層間介電層160,210係由氧化矽、氮氧化矽及/或其他合適的絕緣材料製得。在數個實施例中,串聯式電晶體結構更包含二個導電插塞P穿透層間介電層210,160,此二個導電插塞P分別連接第一源極S1與第二源極S2。在數個實施例中,導電插塞P包含金屬、金屬化合物或其組合。
第3圖繪示根據本發明多個實施例之一種串聯
式電晶體結構的剖面示意圖。第2圖與第3圖的串聯式電晶體結構的差異在於,第3圖的第二汲極墊DP2包含第一汲極墊層DPL1與第二汲極墊層DPL2。第一汲極墊層DPL1位於第二汲極D2與第三汲極D3上,並接觸第二汲極D2與第三汲極D3,且包含矽化物。第二汲極墊層DPL2位於第一汲極墊層DPL1上,且包含金屬、金屬化合物或其組合,以進一步降低第二汲極墊DP2的電阻。金屬或金屬化合物可為鈦、鉭、鎢、鋁、銅、鉬、鉑、氮化鈦、氮化鉭、碳化鉭、氮化鉭矽、氮化鎢、氮化鉬、氮氧化鉬、氧化钌、鈦鋁、氮化鈦鋁、碳氮化鉭、其組合或其他合適的材料。在數個實施例中,導電插塞P與第二汲極墊層DPL2係由同一材料製得。
第4圖繪示根據本發明多個實施例之一種串聯
式電晶體結構的剖面示意圖。第4圖與第2圖的串聯式電晶體結構的差異在於,第4圖的串聯式電晶體結構更包含第一通道-汲極結構CDS1與第一汲極墊DP1,而二個導電插塞P分別連接第一汲極墊DP1與第二源極S2。
第一通道-汲極結構CDS1位於第一源極S1
上,並大致上與第二通道-汲極結構CDS2平行。第一通道-汲極結構CDS1包含第一通道C1及位於第一通道C1上的第一汲極D1。閘介電層130更圍繞第一通道C1。第一汲極墊DP1位於第一汲極D1上,並接觸第一汲極D1。第一汲極墊DP1與第二汲極墊DP2彼此分離。當高電壓透過導電插塞P的其中一者而施加在第一汲極墊DP1或第二源極S2時,電壓會透過第一源極S1與第二汲極墊DP2而被分配到第一通
道-汲極結構CDS1、第二通道-汲極結構CDS2與第三通道-汲極結構CDS3,如第4圖的虛線所示。在其他實施例中,串聯式電晶體結構更包含第四通道-汲極結構(未繪示)位於第二源極S2上,以替代連接第二源極S2的導電插塞P。
第5圖繪示根據本發明多個實施例之一種串聯
式電晶體結構的剖面示意圖。串聯式電晶體結構包含第一源極S1、第二源極S2、隔離部分120、多個第一通道-汲極結構CDS1、多個第二通道-汲極結構CDS2、多個第三通道-汲極結構CDS3、多個第四通道-汲極結構CDS4、閘介電層130、閘極G、第一汲極墊DP1、第二汲極墊DP2及第三汲極墊DP3。在數個實施例中,串聯式電晶體結構更包含第一導電插塞P1、第二導電插塞P2與第三導電插塞P3。第一導電插塞P1連接閘極G。第二導電插塞P2連接第一汲極墊DP1。第三導電插塞P3連接第三汲極墊DP3。在數個實施例中,閘極電壓(Vg)透過第一導電插塞P1施加在閘極G上,工作電壓(Vdd)透過第二導電插塞P2施加在第一汲極墊DP1上,第三導電插塞P3電性連接接地電位。此串聯式電晶體結構可用以提供高增益(gain)。
值得注意的是,相較於串聯式鰭式場效電晶體
(FinFET)結構,本發明的串聯式電晶體結構可具有較小的佔據面積,這是因為本發明的串聯式電晶體結構可被視為是垂直式的折疊結構,但串聯式鰭式場效電晶體結構並非折疊結構。以另一個角度而言,在佔據相同面積的情況下,相較於典型的串聯式鰭式場效電晶體結構,本發明的串聯式電晶
體結構具有較高的增益。
此外,可以發現,相較於並聯式電晶體結構,
串聯式電晶體結構的閥值電壓(threshold voltage,Vth)具有較低的局部變化。串聯式電晶體結構與並聯式電晶體結構的差異在於,並聯式電晶體結構只有一個汲極墊,其連接多個通道-汲極結構的多個汲極,並且只有一個源極,其連接這些通道-汲極結構的多個通道。
由上述可知,本發明的串聯式電晶體結構可藉
由二或多個通道-汲極結構、一或多個源極與一或多個汲極墊分配汲極-源極電壓(Vds),以有效降低或避免汲極感應勢壘降低與熱載子注入現象。此外,相較於水平式電晶體或透過金屬線和導電插塞連接的串聯式電晶體結構,本發明之串聯式電晶體結構佔據較小的面積,從而具有較高的集成密度。
第6A-6F圖繪示根據本發明多個實施例之一種
製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。如第6A圖所示,提供一基材110。在數個實施例中,基材110包含元素半導體、化合物半導體、合金半導體或其組合。在數個實施例中,進行井摻雜製程,以形成由基材110上表面延伸至基材110內的一導電型的井區(未繪示)。
然後,依序形成一源極層SL、一通道層CL及
一汲極層DL於基材110上,如第6A圖所示。在數個實施例中,藉由磊晶(epi)成長與不同摻質濃度的摻雜製程,依序形成源極層SL、通道層CL與汲極層DL。在數個實施例中,
藉由離子摻雜與退火製程形成源極層SL、通道層CL與汲極層DL。通道層CL的摻質濃度低於源極層SL的摻質濃度或汲極層DL的摻質濃度。
隨後,形成一硬遮罩層HM於汲極層DL上,以圖案化汲極層DL、通道層CL與源極層SL,如第6A圖所示。在數個實施例中,硬遮罩材料是藉由化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、旋轉塗佈或其他合適的形成製程形成,然後利用光學微影製程或其他合適的材料移除製程圖案化硬遮罩材料,以形成硬遮罩層HM。
如第6A-6B圖所示,根據硬遮罩層HM圖案化汲極層DL、通道層CL與源極層SL,以形成突出於基材110的串聯式源極-通道-汲極結構,其包含第一源極S1、第一通道-汲極結構CDS1與第二通道-汲極結構CDS2。第一通道-汲極結構CDS1與第二通道-汲極結構CDS2位於第一源極S1上,且大致上相互平行。第一通道-汲極結構CDS1包含第一通道C1及位於第一通道C1上的第一汲極D1,第二通道-汲極結構CDS2包含第二通道C2及位於第二通道C2上的第二汲極D2。在數個實施例中,如第6A圖所示,藉由乾蝕刻,移除自硬遮罩層HM暴露出的汲極層DL及其下方的通道層CL與源極層SL。在數個實施例中,蝕刻劑包含碳氟化物(CxFy)、六氟化硫、氧氣、氦氣、碳醯氯(CxCly)、氬氣或其他合適的蝕刻劑材料。
如第6C圖所示,多個源極矽化物區SSR形成於第一源極S1內。源極矽化物區SSR可用以降低第一源極S1
的電阻。在數個實施例中,源極矽化物區SSR係藉由矽化物沉積製程形成。在數個實施例中,源極矽化物區SSR係利用金屬沉積及退火製程形成。在數個實施例中,沒有源極矽化物區形成於第一源極S1內。
如第6D圖所示,形成源極介電層140覆蓋第一
源極S1與源極矽化物區SSR。在數個實施例中,源極介電層140係利用化學氣相沉積製程、物理氣相沉積製程、旋轉塗佈製程或其他合適的形成製程形成。
然後形成閘介電層130圍繞第一通道C1與第二
通道C2,如第6D圖所示。在數個實施例中,透過物理氣相沉積製程、化學氣相沉積製程、熱濕氧化、熱乾氧化、熱電漿氧化或其他合適的形成製程形成閘介電層130。在數個實施例中,閘介電層130係利用熱氧化製程形成。在數個實施例中,先形成介電層(未繪示)全面覆蓋第一汲極D1與第二汲極D2,以避免在利用熱氧化製程形成閘介電層130時,第一汲極D1與第二汲極D2氧化。
如第6E圖所示,形成高介電常數介電層150與
閘極G於源極介電層140上,並圍繞閘介電層130。源極介電層140用以讓第一源極S1與閘極G之間電性絕緣。在數個實施例中,依序毯覆式沉積高介電常數介電材料與閘極材料,然後進行圖案化,以形成高介電常數介電層150與閘極G。在數個實施例中,利用化學氣相沉積製程、原子層沉積(ALD)製程或其他合適的形成製程毯覆式沉積高介電常數介電材料。在數個實施例中,利用物理氣相沉積製程、化學
氣相沉積製程、原子層沉積製程、電鍍製程、旋轉塗佈製程或其他合適的形成製程毯覆式沉積閘極材料。在數個實施例中,利用光學微影/蝕刻製程或其他合適的材料移除製程圖案化閘極材料與高介電常數介電材料。
如第6F圖所示,形成層間介電層160覆蓋第一
通道-汲極結構CDS1、第二通道-汲極結構CDS2與閘極G,然後進行平坦化製程,以暴露出第一汲極D1的上表面與第二汲極D2的上表面。在數個實施例中,層間介電層160係利用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程形成。在數個實施例中,平坦化製程包含化學機械拋光(CMP)製程、研磨製程、蝕刻製程或其他合適的材料移除製程。在數個實施例中,在平坦化製程之後,第一汲極D1的上表面、第二汲極D2的上表面與層間介電層160的上表面共平面。
隨後,第一汲極墊DP1與第二汲極墊DP2分別
形成在第一汲極D1與第二汲極D2上,且分別接觸第一汲極D1與第二汲極D2,如第6F圖所示。在數個實施例中,先使用任何合適的形成製程形成汲極墊材料,然後利用光學微影/蝕刻製程或其他合適的材料移除製程進行圖案化,以形成第一汲極墊DP1與第二汲極墊DP2。在數個實施例中,第一汲極墊DP1與第二汲極墊DP2包含金屬、矽化物或其組合。
在形成第一汲極墊DP1與第二汲極墊DP2之
後,形成另一層間介電層210於第一汲極墊DP1、第二汲極墊DP2與層間介電層160上,如第1圖所示。在數個實施例
中,層間介電層210係利用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程形成。
之後,圖案化層間介電層210,以形成多個開
口,然後填充導電材料於這些開口中,以形成多個導電插塞P分別連接第一汲極墊DP1與第二汲極墊DP2。在數個實施例中,利用光學微影/蝕刻製程、雷射鑽孔製程或其他合適的材料移除製程圖案化層間介電層210。在數個實施例中,導電材料係利用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程形成。
第7A-7G圖繪示根據本發明多個實施例之一種
製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。如第7A圖所示,提供一基材100,此基材110具有一隔離部分120位於基材110上。隔離部分120係由基材110內延伸至基材110外。在數個實施例中,提供一厚基材(未繪示),然後形成隔離部分120於基材110內。隨後,薄化此厚基材,以形成具有隔離部分120的基材110。在數個實施例中,在薄化厚基材之前,進行井摻雜製程,以形成由厚基材上表面延伸至厚基材內的一導電型的井區(未繪示)。
如第7B圖所示,依序形成一源極層SL、一通道層CL與一汲極層DL於基材110上,且鄰接隔離部分120。在數個實施例中,藉由磊晶成長與不同摻質濃度的摻雜製程,依序形成源極層SL、通道層CL與汲極層DL。在數個實施例中,藉由離子摻雜與退火製程形成源極層SL、通道
層CL與汲極層DL。
隨後,形成一硬遮罩層HM於汲極層DL上,以圖案化汲極層DL、通道層CL與源極層SL,如第7B圖所示。在數個實施例中,硬遮罩材料是藉由化學氣相沉積製程、物理氣相沉積製程、旋轉塗佈或其他合適的形成製程形成,然後利用光學微影製程或其他合適的材料移除製程圖案化硬遮罩材料,以形成硬遮罩層HM。
如第7B-7C圖所示,根據硬遮罩層HM圖案化汲極層DL、通道層CL與源極層SL,以形成突出於基材110的串聯式源極-通道-汲極結構,其包含第一源極S1、第二源極S2、位於第一源極S1上的第二通道-汲極結構CDS2及位於第二源極S2上的第三通道-汲極結構CDS3。隔離部分120位於第一源極S1與第二源極S2之間。第二通道-汲極結構CDS2與第三通道-汲極結構CDS3大致上相互平行。第二通道-汲極結構CDS2包含第二通道C2及位於第二通道C2上的第二汲極D2,第三通道-汲極結構CDS3包含第三通道C3及位於第三通道C3上的第三汲極D3。在數個實施例中,如第7B圖所示,藉由乾蝕刻,移除自硬遮罩層HM暴露出的汲極層DL及其下方的通道層CL與源極層SL。
如第7D圖所示,多個源極矽化物區SSR形成於第一源極S1與第二源極S2內。源極矽化物區SSR可用以降低第一源極S1的電阻及第二源極S2的電阻。在數個實施例中,源極矽化物區SSR係藉由矽化物沉積製程形成。在數個實施例中,源極矽化物區SSR係利用金屬沉積及退火製程形
成。在數個實施例中,沒有源極矽化物區形成於第一源極S1與第二源極S2內。
如第7E圖所示,形成源極介電層140覆蓋第一源極S1、第二源極S2、源極矽化物區SSR與隔離部分120。在數個實施例中,源極介電層140係利用化學氣相沉積製程、物理氣相沉積製程、旋轉塗佈製程或其他合適的形成製程形成。
然後形成閘介電層130圍繞第二通道C2與第三通道C3,如第7E圖所示。在數個實施例中,透過物理氣相沉積製程、化學氣相沉積製程、熱濕氧化、熱乾氧化、熱電漿氧化或其他合適的形成製程形成閘介電層130。在數個實施例中,閘介電層130係利用熱氧化製程形成。在數個實施例中,先形成介電層(未繪示)全面覆蓋第二汲極D2與第三汲極D3,以避免在利用熱氧化製程形成閘介電層130時,第二汲極D2與第三汲極D3氧化。
如第7F圖所示,形成高介電常數介電層150與閘極G於源極介電層140上,並圍繞閘介電層130。在數個實施例中,依序毯覆式沉積高介電常數介電材料與閘極材料,然後藉由光學微影蝕刻製程進行圖案化,以形成高介電常數介電層150與閘極G。
如第7G圖所示,形成層間介電層160覆蓋第二通道-汲極結構CDS2、第三通道-汲極結構CDS3與閘極G,然後進行平坦化製程,以暴露出第二汲極D2的上表面與第三汲極D3的上表面。在數個實施例中,層間介電層160係利
用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程形成。在數個實施例中,平坦化製程包含化學機械拋光製程、研磨製程、蝕刻製程或其他合適的材料移除製程。在數個實施例中,在平坦化製程之後,第二汲極D2的上表面、第三汲極D3的上表面與層間介電層160的上表面共平面。
隨後,形成第二汲極墊DP2於第二汲極D2與第
三汲極D3上,並接觸第二汲極D2與第三汲極D3,如第7G圖所示。在數個實施例中,先使用任何合適的形成製程形成汲極墊材料,然後利用光學微影/蝕刻製程或其他合適的材料移除製程進行圖案化,以形成第二汲極墊DP2。在數個實施例中,第二汲極墊DP2包含金屬、矽化物或其組合。
在形成第二汲極墊D P2之後,形成另一層間介
電層210於第二汲極墊DP2與層間介電層160上,如第2圖所示。在數個實施例中,層間介電層210係利用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程形成。
之後,圖案化層間介電層210,160,以形成多
個開口,然後填充導電材料於這些開口中,以形成多個導電插塞P分別連接第一源極S1與第二源極S2。在數個實施例中,利用光學微影/蝕刻製程、雷射鑽孔製程或其他合適的材料移除製程圖案化層間介電層210,160。在數個實施例中,導電材料係利用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋轉塗佈製程或其他合適的形成製程
形成。
第8A-8G圖繪示根據本發明多個實施例之一種
製造串聯式電晶體結構的方法在各個製程階段的剖面示意圖。如第8A圖所示,提供一基材100,此基材110具有一隔離部分120位於基材110上。隔離部分120係由基材110內延伸至基材110外。如第8B圖所示,依序形成一源極層SL、一通道層CL與一汲極層DL於基材110上,且鄰接隔離部分120。隨後,形成一硬遮罩層HM於汲極層DL上,以圖案化汲極層DL、通道層CL與源極層SL。
如第8B-8C圖所示,根據硬遮罩層HM圖案化
汲極層DL、通道層CL與源極層SL,以形成突出於基材110的串聯式源極-通道-汲極結構,其包含第一源極S1、第二源極S2、位於第一源極S1上的第一通道-汲極結構CDS1與第二通道-汲極結構CDS2,及位於第二源極S2上的第三通道-汲極結構CDS3。亦即,相較於第7B-7C圖的實施例,第8B-8C圖的實施例更包含形成第一通道-汲極結構CDS1於第一源極S1上,第一通道-汲極結構CDS1與第二通道-汲極結構CDS2大致上相互平行。第一通道-汲極結構CDS1包含第一通道C1及位於第一通道C1上的第一汲極D1。
如第8D圖所示,多個源極矽化物區SSR形成於
第一源極S1與第二源極S2內。如第8E圖所示,形成源極介電層140覆蓋第一源極S1、第二源極S2、源極矽化物區SSR與隔離部分120。然後形成閘介電層130圍繞第一通道C1、第二通道C2與第三通道C3。如第8F圖所示,形成高介電常
數介電層150與閘極G於源極介電層140上,並圍繞閘介電層130。
如第8G圖所示,形成層間介電層160覆蓋第一
通道-汲極結構CDS1、第二通道-汲極結構CDS2、第三通道-汲極結構CDS3與閘極G,然後進行平坦化製程,以暴露出第一汲極D1的上表面、第二汲極D2的上表面與第三汲極D3的上表面。隨後,形成第一汲極墊DP1與第二汲極墊DP2。第一汲極墊DP1形成於第一汲極D1上,並接觸第一汲極D1,第二汲極墊DP2形成於第二汲極D2與第三汲極D3上,並接觸第二汲極D2與第三汲極D3。
在形成第一汲極墊DP1與第二汲極墊DP2之
後,形成另一層間介電層210於第一汲極墊DP1、第二汲極墊DP2與層間介電層160上,如第4圖所示。然後圖案化層間介電層210,160,以形成多個開口,再填充導電材料於這些開口中,以形成多個導電插塞P分別連接第一汲極墊DP1與第二源極S2。
本發明之方法可用以製造串聯式電晶體結構以
分配汲極到源極的電壓。此外,相較於透過金屬線和導電插塞連接的串聯式電晶體結構,本發明之方法所製得的串聯式電晶體結構可佔據較小的面積,這是因為形成金屬線和導電插塞有製程上的極限。
雖然本發明已以實施例揭露如上,然其並非用
以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範
圍當視後附之申請專利範圍所界定者為準。
110‧‧‧基材
110a‧‧‧I/O區
130‧‧‧閘介電層
140‧‧‧源極介電層
150‧‧‧高介電常數介電層
160‧‧‧層間介電層
210‧‧‧層間介電層
C1‧‧‧第一通道
C2‧‧‧第二通道
CDS1‧‧‧第一通道-汲極結構
CDS2‧‧‧第二通道-汲極結構
D1‧‧‧第一汲極
D2‧‧‧第二汲極
DP1‧‧‧第一汲極墊
DP2‧‧‧第二汲極墊
G‧‧‧閘極
P‧‧‧導電插塞
S1‧‧‧第一源極
SSR‧‧‧源極矽化物區
Claims (10)
- 一種串聯式電晶體結構,包含:一第一源極,位於一基材上;一第一通道-汲極結構位於該第一源極上,該第一通道-汲極結構包含一第一通道及一第一汲極位於該第一通道上;一第二通道-汲極結構,位於該第一源極上,並大致上與該第一通道-汲極結構平行,該第二通道-汲極結構包含一第二通道及一第二汲極位於該第二通道上;一閘介電層,圍繞該第一通道及該第二通道;一閘極,圍繞該閘介電層並填充於該第一通道與該第二通道之間;一第一汲極墊,位於該第一汲極上,並接觸該第一汲極;一第二汲極墊,位於該第二汲極上,並接觸該第二汲極,其中該第一汲極墊與該第二汲極墊彼此分離;以及一源極矽化物區,位於該第一通道與該第二通道之間的該閘極下方的該第一源極內。
- 如請求項第1項所述之串聯式電晶體結構,其中該串聯式電晶體結構位於一I/O元件內。
- 一種串聯式電晶體結構,包含:一第一源極,位於一基材上;一第二源極,位於該基材上,且側向鄰接該第一源極; 一隔離部分,位於該第一源極與該第二源極之間,以電性隔離該第一源極與該第二源極;一第二通道-汲極結構,位於該第一源極上,該第二通道-汲極結構包含一第二通道及一第二汲極位於該第二通道上;一第三通道-汲極結構,位於該第二源極上,並大致上與該第二通道-汲極結構平行,該第三通道-汲極結構包含一第三通道及一第三汲極位於該第三通道上;一閘介電層,圍繞該第二通道及該第三通道;一閘極,圍繞該閘介電層並填充於該第一通道與該第二通道之間;以及一第二汲極墊,位於該第二汲極及該第三汲極上,並接觸該第二汲極及該第三汲極,其中該隔離部分未位於該第一通道與該第二通道之間。
- 如請求項第3項所述之串聯式電晶體結構,更包含二個導電插塞分別連接該第一源極與該第二源極。
- 如請求項第3項所述之串聯式電晶體結構,其中該第二汲極墊包含矽化物。
- 如請求項第3項所述之串聯式電晶體結構,其中該第二汲極墊包含: 一第一汲極墊層位於該第二汲極及該第三汲極上,並接觸該第二汲極及該第三汲極,該第一汲極墊層包含矽化物;以及一第二汲極墊層位於該第一汲極墊層上,該第二汲極墊層包含金屬、金屬化合物或其組合。
- 如請求項第3項所述之串聯式電晶體結構,更包含一第一通道-汲極結構位於該第一源極上,並大致上與該第二通道-汲極結構平行,該第一通道-汲極結構包含一第一通道及一第一汲極位於該第一通道上。
- 如請求項第7項所述之串聯式電晶體結構,更包含一第一汲極墊位於該第一汲極上,並接觸該第一汲極,該第一汲極墊與該第二汲極墊彼此分離。
- 如請求項第7項所述之串聯式電晶體結構,更包含一導電插塞連接該第二源極。
- 一種製造串聯式電晶體結構的方法,包含:形成一串聯式源極-通道-汲極結構突出一基材,該串聯式源極-通道-汲極結構包含一第一源極位於該基材上、一第一通道-汲極結構位於該第一源極上及一第二通道-汲極結構位於該第一源極上,該第一通道-汲極結構大致上與該第二通道-汲極結構相互平行,或者該串聯式源極-通道- 汲極結構包含該第一源極、一第二源極位於該基材上且側向鄰接該第一源極、一隔離部分位於該第一源極與該第二源極之間、該第二通道-汲極結構位於該第一源極上及一第三通道-汲極結構位於該第二源極上,該第二通道-汲極結構大致上與該第三通道-汲極結構相互平行;形成一源極矽化物區於該第一通道與該第二通道之間的一空間下方的該第一源極內,或者於該第一源極內與該第二源極內;形成一源極介電層於該第一源極上,或者於該第一源極與該第二源極上;形成一閘介電層圍繞該第一通道-汲極結構之一通道與該第二通道-汲極結構之一通道,或者圍繞該第二通道-汲極結構之該通道與該第三通道-汲極結構之一通道;形成一閘極於該源極介電層上,並圍繞該閘介電層且填充於該第一通道與該第二通道之間;以及分別形成一第一汲極墊與一第二汲極墊於該第一通道-汲極結構之一汲極與該第二通道-汲極結構之一汲極上,並接觸該第一通道-汲極結構之該汲極與該第二通道-汲極結構之該汲極,或者形成該第二汲極墊於該第二通道-汲極結構之該汲極與該第三通道-汲極結構之一汲極上,並接觸該第二通道-汲極結構之該汲極與該第三通道-汲極結構之該汲極。
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US9373620B2 (en) * | 2014-09-12 | 2016-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Series connected transistor structure and method of manufacturing the same |
TWI662625B (zh) * | 2015-01-19 | 2019-06-11 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
US9899264B2 (en) * | 2016-06-30 | 2018-02-20 | International Business Machines Corporation | Integrated metal gate CMOS devices |
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US10840354B2 (en) * | 2017-02-06 | 2020-11-17 | International Business Machines Corporation | Approach to bottom dielectric isolation for vertical transport fin field effect transistors |
KR20180098446A (ko) | 2017-02-24 | 2018-09-04 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
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US11923837B2 (en) | 2020-11-25 | 2024-03-05 | Nuvolta Technologies (Hefei) Co., Ltd. | Load switch including back-to-back connected transistors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110012085A1 (en) * | 2007-09-24 | 2011-01-20 | International Business Machines Corporation | Methods of manufacture of vertical nanowire fet devices |
TW201434154A (zh) * | 2013-02-27 | 2014-09-01 | Sk Hynix Inc | 電晶體、包含相同電晶體之可變電阻記憶元件及其製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100486253B1 (ko) | 2002-08-12 | 2005-05-03 | 삼성전자주식회사 | 수직형 트랜지스터의 제조방법 |
US7192876B2 (en) * | 2003-05-22 | 2007-03-20 | Freescale Semiconductor, Inc. | Transistor with independent gate structures |
US7372091B2 (en) * | 2004-01-27 | 2008-05-13 | Micron Technology, Inc. | Selective epitaxy vertical integrated circuit components |
US7241655B2 (en) * | 2004-08-30 | 2007-07-10 | Micron Technology, Inc. | Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array |
KR100618875B1 (ko) | 2004-11-08 | 2006-09-04 | 삼성전자주식회사 | 수직 채널 mos 트랜지스터를 구비한 반도체 메모리소자 및 그 제조방법 |
US8058683B2 (en) | 2007-01-18 | 2011-11-15 | Samsung Electronics Co., Ltd. | Access device having vertical channel and related semiconductor device and a method of fabricating the access device |
JP5091491B2 (ja) * | 2007-01-23 | 2012-12-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US8183628B2 (en) * | 2007-10-29 | 2012-05-22 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor structure and method of fabricating the semiconductor structure |
JP5317343B2 (ja) | 2009-04-28 | 2013-10-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及びその製造方法 |
US8188537B2 (en) * | 2008-01-29 | 2012-05-29 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
WO2009095997A1 (ja) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | 半導体装置およびその製造方法 |
US7969776B2 (en) | 2008-04-03 | 2011-06-28 | Micron Technology, Inc. | Data cells with drivers and methods of making and operating the same |
TWI368315B (en) * | 2008-08-27 | 2012-07-11 | Nanya Technology Corp | Transistor structure, dynamic random access memory containing the transistor structure, and method of making the same |
JP4487221B1 (ja) | 2009-04-17 | 2010-06-23 | 日本ユニサンティスエレクトロニクス株式会社 | 半導体装置 |
GB2472227B (en) | 2009-07-29 | 2011-09-14 | Mobiletron Electronics Co Ltd | Impact drill |
KR101698193B1 (ko) * | 2009-09-15 | 2017-01-19 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
JP5066590B2 (ja) * | 2010-06-09 | 2012-11-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置とその製造方法 |
CN102543877B (zh) * | 2010-12-29 | 2014-03-12 | 中国科学院微电子研究所 | 制备三维半导体存储器件的方法 |
JP2013088862A (ja) | 2011-10-13 | 2013-05-13 | Elpida Memory Inc | レイアウトデータ作成装置及び半導体装置 |
US8772175B2 (en) * | 2011-12-19 | 2014-07-08 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US8890119B2 (en) | 2012-12-18 | 2014-11-18 | Intel Corporation | Vertical nanowire transistor with axially engineered semiconductor and gate metallization |
US9496256B2 (en) | 2014-07-18 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device including a vertical gate-all-around transistor and a planar transistor |
US9373620B2 (en) * | 2014-09-12 | 2016-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Series connected transistor structure and method of manufacturing the same |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110012085A1 (en) * | 2007-09-24 | 2011-01-20 | International Business Machines Corporation | Methods of manufacture of vertical nanowire fet devices |
TW201434154A (zh) * | 2013-02-27 | 2014-09-01 | Sk Hynix Inc | 電晶體、包含相同電晶體之可變電阻記憶元件及其製造方法 |
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