WO2022000257A1 - 半导体器件及其制作方法、电子设备 - Google Patents

半导体器件及其制作方法、电子设备 Download PDF

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Publication number
WO2022000257A1
WO2022000257A1 PCT/CN2020/099219 CN2020099219W WO2022000257A1 WO 2022000257 A1 WO2022000257 A1 WO 2022000257A1 CN 2020099219 W CN2020099219 W CN 2020099219W WO 2022000257 A1 WO2022000257 A1 WO 2022000257A1
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semiconductor
layer
isolation
channel
pattern layer
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PCT/CN2020/099219
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English (en)
French (fr)
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万光星
黄威森
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华为技术有限公司
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Priority to PCT/CN2020/099219 priority Critical patent/WO2022000257A1/zh
Priority to EP20943407.5A priority patent/EP4156300A4/en
Priority to CN202080101293.6A priority patent/CN115668509A/zh
Publication of WO2022000257A1 publication Critical patent/WO2022000257A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic device.
  • VGAA devices vertical gate all around transistors
  • the present application provides a semiconductor device, a method for manufacturing the same, and an electronic device, and a semiconductor device including vertical gate-around transistors with different gate lengths.
  • Embodiments of the present application provide a semiconductor device, including: a substrate, and a first semiconductor fin and a second semiconductor fin on the substrate; the first semiconductor fin includes a plurality of isolated semiconductor pattern layers and at least one channel semiconductor pattern layer arranged in layers , wherein each channel semiconductor pattern layer is sandwiched between two isolation semiconductor pattern layers; the second semiconductor fin includes a first isolation semiconductor pattern layer, a first channel semiconductor layer and a second isolation semiconductor pattern layer that are stacked in sequence ; The total thickness of all the channel semiconductor pattern layers in the first semiconductor fin is different from the thickness of the first channel semiconductor pattern layer.
  • the first vertical gate-all-around transistor and the second vertical gate-all-around transistor have different gate lengths, thereby increasing the application range of the semiconductor device, for example, it can meet the requirements of analog circuits for vertical gate-all-around transistors with different gate lengths .
  • the channel semiconductor pattern layer in the first semiconductor fin closest to the substrate is the same semiconductor material as the first channel semiconductor pattern layer.
  • the channel semiconductor pattern layer of the first semiconductor fin closest to the substrate and the first channel semiconductor pattern layer can be prepared through the same channel semiconductor layer, thereby simplifying the process and reducing the production cost the goal of.
  • the first semiconductor fin includes a third isolation semiconductor pattern layer, a second channel semiconductor pattern layer, and a fourth isolation semiconductor pattern layer sequentially disposed on the substrate; the thickness of the second channel semiconductor pattern layer The thickness of the semiconductor pattern layer is different from that of the first channel; thus, the first vertical gate-all-around transistor and the second vertical gate-all-around transistor having different channel lengths can be obtained.
  • the third isolation semiconductor pattern layer is close to the substrate relative to the fourth isolation semiconductor pattern layer; the first isolation semiconductor pattern layer is close to the substrate relative to the second isolation semiconductor pattern layer; the third isolation semiconductor pattern layer is close to the third isolation semiconductor pattern layer.
  • One isolation semiconductor pattern layer has the same thickness, and the third isolation semiconductor pattern layer is the same as the semiconductor material in the first isolation semiconductor pattern layer; the fourth isolation semiconductor pattern layer has the same thickness as the second isolation semiconductor pattern layer, and the fourth isolation semiconductor pattern layer has the same thickness
  • the semiconductor pattern layer is the same as the semiconductor material in the second isolation semiconductor pattern layer.
  • the third isolation semiconductor pattern layer and the first isolation semiconductor pattern layer can be prepared through the same isolation semiconductor layer
  • the fourth isolation semiconductor pattern layer and the second isolation semiconductor pattern layer can be prepared through the same isolation semiconductor layer. That is, the third isolation semiconductor pattern layer and the first isolation semiconductor pattern layer are in the same layer and the same material, and the fourth isolation semiconductor pattern layer and the second isolation semiconductor pattern layer are in the same layer and the same material, so as to simplify the process and reduce the production cost. the goal of.
  • the first semiconductor fin includes a fifth isolation semiconductor pattern layer, a third channel semiconductor pattern layer, a sixth isolation semiconductor pattern layer, a fourth channel semiconductor pattern layer, a Seven isolation semiconductor pattern layers; the thickness of the third channel semiconductor pattern layer is the same as that of the first channel semiconductor pattern layer; thus, the first vertical gate-all-around transistor and the second vertical gate-all-around transistor with different channel lengths can be obtained.
  • the semiconductor materials in the first channel semiconductor pattern layer and the second channel semiconductor pattern layer are the same; in this case, during actual production, the first channel semiconductor pattern layer and the second channel semiconductor pattern layer are the same
  • the channel semiconductor pattern layer can be prepared by using the same channel semiconductor layer and thinning by local etching; that is, the first channel semiconductor pattern layer and the second channel semiconductor pattern layer are of the same layer and the same material; thus simplifying process, the purpose of reducing production costs.
  • the fifth isolation semiconductor pattern layer is close to the substrate relative to the sixth isolation semiconductor pattern layer; the first isolation semiconductor pattern layer is close to the substrate relative to the second isolation semiconductor pattern layer; the fifth isolation semiconductor pattern layer is close to the substrate
  • the thickness of an isolation semiconductor pattern layer is the same, and the fifth isolation semiconductor pattern layer is the same as the semiconductor material in the first isolation semiconductor pattern layer; the thickness of the sixth isolation semiconductor pattern layer is the same as that of the second isolation semiconductor pattern layer, and the sixth isolation semiconductor pattern layer has the same thickness
  • the semiconductor pattern layer is the same as the semiconductor material in the second isolation semiconductor pattern layer.
  • the fifth isolation semiconductor pattern layer and the first isolation semiconductor pattern layer can be prepared through the same isolation semiconductor layer; the sixth isolation semiconductor pattern layer and the second isolation semiconductor pattern layer can be prepared through the same isolation semiconductor layer That is, the fifth isolation semiconductor pattern layer and the first isolation semiconductor pattern layer are in the same layer and the same material, and the sixth isolation semiconductor pattern layer and the second isolation semiconductor pattern layer are in the same layer and the same material, so as to simplify the process and reduce the production cost. the goal of.
  • the thicknesses of the first channel semiconductor pattern layer and the third channel semiconductor pattern layer are the same, and the semiconductor materials in the first channel semiconductor pattern layer and the third channel semiconductor pattern layer are the same; in In this case, in actual production, the first channel semiconductor pattern layer and the third channel semiconductor pattern layer can be prepared from the same semiconductor layer; that is, the first channel semiconductor pattern layer and the third channel semiconductor pattern layer are the same Layer the same material, so as to achieve the purpose of simplifying the process and reducing the production cost.
  • spacer shields are provided on the sides around the isolation semiconductor pattern layer located on both sides of each channel semiconductor pattern layer, and spacer shields are provided around the channel semiconductor pattern layer.
  • a gate insulating layer and a gate layer are arranged on the side and between the two sidewall shielding bodies in sequence; in the second semiconductor fin, the sides around the first isolation semiconductor pattern layer and the second isolation semiconductor pattern layer are provided with In the sidewall shielding body, a gate insulating layer and a gate electrode layer are sequentially arranged on the sides around the first channel semiconductor layer and between the two sidewall shielding bodies.
  • the substrate is a silicon substrate.
  • the material for forming the isolation semiconductor layer includes: SiGe; the material for forming the channel semiconductor layer includes: Si.
  • the material for forming the isolation semiconductor layer includes: Si; the material for forming the channel semiconductor layer includes: SiGe.
  • Embodiments of the present application further provide a method for fabricating a semiconductor device, including: forming an initial semiconductor stack structure on a substrate; wherein the initial semiconductor stack structure includes at least one isolation semiconductor layer and at least one channel semiconductor layer alternately formed on the substrate in sequence layer; the initial semiconductor stack structure is etched to form an intermediate semiconductor stack structure; wherein, the intermediate semiconductor stack structure includes an effective channel semiconductor layer, and the effective channel semiconductor layer is located between the two isolation semiconductor layers; the effective channel semiconductor layer
  • the first region has a first thickness and the second region has a second thickness; the first thickness is different from the second thickness, and the first region and the second region are different regions; the intermediate semiconductor stack structure is etched to A first semiconductor fin structure is formed in the first region, and a second semiconductor fin structure is formed in the second region.
  • an effective channel semiconductor pattern layer having regions with different thicknesses can be fabricated by etching, and the regions with different thicknesses of the effective channel semiconductor pattern layer can be subsequently used as a vertical gate-all-around transistor.
  • the channel shape (such as cylindrical, cubic, etc.) of the vertical gate-all-around transistor can be controlled according to actual needs by etching during the manufacturing process; that is, the manufacturing method of the present application can be used.
  • At least two types of vertical gate-all-around transistors with different channel lengths are simultaneously fabricated in one process, which increases the channel design freedom of the vertical gate-all-around transistor, and can simultaneously form long-channel gate-all-around transistors and short gate-all-around transistors.
  • the channel gate-all-around transistor thereby improving the application range of semiconductor devices.
  • the uppermost layer of the intermediate semiconductor stacked structure is provided with a top epitaxial isolation semiconductor layer; before the intermediate semiconductor stacked structure is etched, the manufacturing method of the semiconductor device further includes: the top epitaxial isolation semiconductor layer is The upper surface is planarized to ensure the flatness of the upper surface of the top epitaxial isolation semiconductor layer, so as to facilitate the subsequent fabrication of other film layers on the top epitaxial isolation semiconductor layer.
  • forming the initial semiconductor stacked structure on the substrate includes: sequentially forming a first isolation semiconductor layer and a first channel semiconductor layer on the substrate to obtain an initial semiconductor stacked structure; Etching to form the intermediate semiconductor stack structure includes: etching and thinning the first channel semiconductor layer located in the second region to form an effective channel semiconductor layer; sequentially forming a second isolation on the effective channel semiconductor layer The semiconductor layer and the top layer epitaxially isolate the semiconductor layer to obtain an intermediate semiconductor stack structure.
  • forming the initial semiconductor stack structure on the substrate includes: sequentially forming a first isolation semiconductor layer, a first channel semiconductor layer, a second isolation semiconductor layer, a second channel semiconductor layer, a The three isolation semiconductor layers and the first epitaxial isolation semiconductor layer are obtained to obtain an initial semiconductor stacked structure; the etching of the initial semiconductor stacked structure to form the intermediate semiconductor stacked structure includes: etching the initial semiconductor stacked structure to remove at least the first semiconductor stacked structure.
  • the film layer above the second channel semiconductor layer in the second region obtains an initial semiconductor stacked structure after etching; the etched initial semiconductor stacked structure includes an effective channel semiconductor layer, and the effective channel semiconductor layer in the second region includes A channel semiconductor layer includes two channel semiconductor layers in the first region; a top layer epitaxial isolation semiconductor layer is formed on the upper surface of the etched initial semiconductor stacked structure to obtain an intermediate semiconductor stacked structure.
  • removing at least the film layer over the second channel semiconductor layer in the second region includes: removing the film layer over the second channel semiconductor layer in the second region, and thinning the second trench the thickness of the semiconductor layer in the second region. Therefore, a manufacturing process with lower etching precision can be used in the manufacturing process, thereby reducing the manufacturing process requirements.
  • the method for fabricating the semiconductor device After etching the intermediate semiconductor stacked structure to form the first semiconductor fin structure in the first region and forming the second semiconductor fin structure in the second region, the method for fabricating the semiconductor device It also includes: partially etching the isolation semiconductor layers in the first semiconductor fin structure and the second semiconductor fin structure to form sidewall grooves, and filling the sidewall grooves with insulating dielectric materials to form sidewall shields; The channel semiconductor layer located between the two spacer shielding bodies is etched to form a channel groove, and a gate insulating layer and a gate layer arranged in sequence are formed in the channel groove.
  • forming the gate insulating layer and the gate layer arranged in sequence in the channel groove includes: using an HKMG process to form the high-k insulating layer and the metal layer in sequence in the channel groove gate layer.
  • the performance of the prepared vertical gate-all-around transistor can be improved, the gate leakage amount can be reduced, the gate capacitance and the critical dimension of the vertical gate-all-around transistor can be reduced.
  • the method for fabricating the semiconductor device before forming the initial semiconductor stack structure on the substrate, the method for fabricating the semiconductor device further includes: disposing the substrate, and forming the substrate at positions corresponding to the plurality of vertical gate-all-around transistors to be formed on the substrate respectively well area.
  • Embodiments of the present application further provide an electronic device, which is characterized in that it includes a semiconductor device in any of the foregoing possible implementation manners.
  • FIG. 1 is a schematic partial structure diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a semiconductor fin portion in a semiconductor device provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a semiconductor fin portion in a semiconductor device according to an embodiment of the present application.
  • FIG. 4 is a flowchart of a front-end process of a semiconductor device provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a front-end process of a semiconductor device provided in Embodiment 1 of the present application;
  • FIG. 6 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 7 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 8 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 9 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 10 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 11 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 12 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application in a manufacturing process
  • FIG. 13 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application after completing the previous process;
  • FIG. 14 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present application after completion of a subsequent process;
  • FIG. 16 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 17 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 18 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 19 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 20 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 21 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 22 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application in a manufacturing process
  • FIG. 23 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application after completing the previous process;
  • FIG. 24 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present application after completion of a subsequent process.
  • Embodiments of the present application provide an electronic device including a semiconductor device provided with a plurality of vertical gate-all-around transistors.
  • the electronic device may be an electronic product such as a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, and a smart bracelet.
  • the specific form of the electronic device is not particularly limited in the embodiments of the present application.
  • the present application does not specifically limit the specific form of the above-mentioned semiconductor device provided with a plurality of vertical gate-all-around transistors; for example, the semiconductor device may be a chip or a substrate integrated with a control circuit in an electronic device.
  • the semiconductor device includes a substrate 01 and a first vertical gate-all-around transistor 10 and a second vertical gate-all-around transistor 20 located on the substrate 01; wherein, the first vertical gate-all-around transistor 10 includes a first semiconductor fin Z1, The second vertical gate-all-around transistor 20 includes a second semiconductor fin Z2.
  • the partial schematic diagram of the semiconductor device shown in FIG. 1 in order to illustrate the entire channel region of the first vertical gate-all-around transistor 10 , the part where the gate is connected to the channel region is omitted.
  • each of the first semiconductor fin Z1 and the second semiconductor fin Z2 includes a plurality of isolation semiconductor pattern layers 1 and at least one channel semiconductor pattern layer 2 arranged in layers, and each channel semiconductor pattern body The layers 2 are each sandwiched between two isolated semiconductor pattern layers 1 .
  • FIG. 1 is only a schematic illustration by taking as an example that both the first semiconductor fin Z1 and the second semiconductor fin Z2 are provided with two isolation semiconductor pattern layers 1 and one channel semiconductor pattern layer 2 .
  • the sum of the thicknesses of the channel semiconductor pattern layers 2 in the first semiconductor fin Z1 (ie, the total thickness) is different from the sum of the thicknesses of the channel semiconductor pattern layers 2 in the second semiconductor fin Z2 (ie, the total thickness).
  • the thickness L1 of the channel semiconductor pattern layer 2 in the first semiconductor fin Z1 and the Thickness L2 of the channel semiconductor pattern layer 2 in the second semiconductor fin Z2 is different (L1 ⁇ L2).
  • the channel semiconductor pattern layer 2 is used as the channel layer of the transistor, and its thickness is the length of the channel; of course, around the channel semiconductor pattern layer 2
  • a gate insulating layer and a gate layer can be arranged on the side of the transistor in sequence (for details, please refer to the following).
  • their gate lengths ie, gate lengths
  • their gate lengths must also be different.
  • the first vertical gate-all-around transistor and the second vertical gate-all-around transistor have different gate lengths, thereby improving the application range of the semiconductor device, for example, it can satisfy the requirements of analog circuits for different Demand for vertical gate-all-around transistors with gate lengths.
  • the type of vertical gate-all-around transistors (10, 20) is not limited in this application, and the vertical gate-all-around transistors can be nanowire gate-all-around transistors (namely, nanowire FETs) or nano-sheet gate-all-around transistors (namely, nanosheet FETs).
  • the semiconductor device includes at least one first vertical gate-all-around transistor 10 and at least one vertical gate-all-around transistor 20 in the semiconductor device.
  • One second vertical gate all around transistors 20 for example, there may be 1000 first vertical gate all around transistors 10 and 2000 second vertical gate all around transistors 20 .
  • the first vertical gate all around transistor 10 and the second vertical gate all around transistor 20 do not refer to two types of vertical gate all around transistors with specific gate lengths
  • the first vertical gate-all-around transistor 10 and the second vertical gate-all-around transistor 20 merely refer to two types of opposing vertical gate-all-around transistors that satisfy the aforementioned specific conditions;
  • any two vertical gate ring transistors with different channel lengths can be regarded as the aforementioned first vertical ring respectively.
  • isolation semiconductor pattern layer 1 and the channel semiconductor pattern layer 2 in the first semiconductor fin Z1 and the second semiconductor fin Z2 in the semiconductor device of the present application will be further described below.
  • the second semiconductor fin Z2 includes a first isolation semiconductor pattern layer a1 , a first channel semiconductor pattern layer b1 , and a second isolation semiconductor pattern layer a2 sequentially disposed on the substrate 01 ;
  • the first isolation semiconductor pattern layer a1 is closer to the substrate 01 than the second isolation semiconductor pattern layer a2.
  • the first semiconductor fin Z1 includes a third isolation semiconductor pattern layer a3, a second channel semiconductor pattern layer b2, and a fourth isolation semiconductor pattern layer a4 sequentially disposed on the substrate 01; the third isolation semiconductor pattern layer a3 is isolated from the fourth The semiconductor pattern layer a4 is close to the substrate 01 .
  • the thickness of the first channel semiconductor pattern layer b1 and the thickness of the second channel semiconductor pattern layer b2 are different, that is, the channel lengths of the first vertical gate-all-around transistor 10 and the second vertical gate-all-around transistor 20 are different.
  • the third isolation semiconductor pattern layer a3 and the first isolation semiconductor pattern layer a1 have the same thickness, and the third isolation semiconductor pattern layer a3 and the first isolation semiconductor pattern layer a1 have the same thickness.
  • the third isolation semiconductor pattern layer a3 and the first isolation semiconductor pattern layer a1 can be prepared by the same isolation semiconductor layer, that is, the third isolation semiconductor pattern layer a3
  • the isolation semiconductor pattern layer a3 and the first isolation semiconductor pattern layer a1 are of the same layer and material.
  • the thicknesses of the fourth isolation semiconductor pattern layer a4 and the second isolation semiconductor pattern layer a2 are the same, and the semiconductor materials in the fourth isolation semiconductor pattern layer a4 and the second isolation semiconductor pattern layer a2 are the same; also That is to say, in order to simplify the process and reduce the manufacturing cost, in actual production, the fourth isolation semiconductor pattern layer a4 and the second isolation semiconductor pattern layer a2 can be prepared by the same isolation semiconductor layer, that is, the fourth isolation semiconductor pattern layer a4 and The second isolation semiconductor pattern layer a2 is the same layer and the same material.
  • the semiconductor materials in the first channel semiconductor pattern layer b1 and the second channel semiconductor pattern layer b2 are the same; that is to say, in order to simplify the process and reduce the production cost, in actual production, the first The channel semiconductor pattern layer b1 and the second channel semiconductor pattern layer b2 can be prepared by using the same channel semiconductor layer and using a method of local etching and thinning; that is, the first channel semiconductor pattern layer b1 and the second channel semiconductor pattern layer b1
  • the semiconductor pattern layer b2 is the same layer and the same material.
  • the second semiconductor fin Z2 includes a first isolation semiconductor pattern layer a1 , a first channel semiconductor pattern layer b1 , and a second isolation semiconductor pattern layer a2 that are sequentially arranged on the substrate 01 ;
  • the first isolation semiconductor pattern layer a1 is closer to the substrate 01 than the second isolation semiconductor pattern layer a2.
  • the first semiconductor fin Z1 includes a fifth isolation semiconductor pattern layer a5 , a third channel semiconductor pattern layer b3 , a sixth isolation semiconductor pattern layer a6 , a fourth channel semiconductor pattern layer b4 , and a seventh isolation semiconductor pattern layer b4 , which are sequentially arranged on the substrate 01 .
  • the semiconductor pattern layer a7; the fifth isolation semiconductor pattern layer a5 is closer to the substrate 01 than the seventh isolation semiconductor pattern layer a7.
  • the thickness of the third channel semiconductor pattern layer b3 is the same as the thickness of the first channel semiconductor pattern layer b1, then there must be the sum of the thicknesses of the third channel semiconductor pattern layer b3 and the fourth channel semiconductor pattern layer b4 Greater than the first channel semiconductor pattern layer b1 , that is, the channel lengths of the first vertical gate-all-around transistor 10 and the second vertical gate-all-around transistor 20 are different.
  • the thicknesses of the fifth isolation semiconductor pattern layer a5 and the first isolation semiconductor pattern layer a1 are the same, and the thicknesses of the fifth isolation semiconductor pattern layer a5 and the first isolation semiconductor pattern layer a1 are the same.
  • the fifth isolation semiconductor pattern layer a5 and the first isolation semiconductor pattern layer a1 can be prepared by the same isolation semiconductor layer; that is, the fifth isolation semiconductor pattern layer a5 and the first isolation semiconductor pattern layer a1
  • the isolation semiconductor pattern layer a5 is of the same layer and material as the first isolation semiconductor pattern layer a1.
  • the sixth isolation semiconductor pattern layer a6 and the second isolation semiconductor pattern layer a2 have the same thickness, and the sixth isolation semiconductor pattern layer a6 and the second isolation semiconductor pattern layer a2 have the same semiconductor material That is to say, in order to simplify the process and reduce the manufacturing cost, in actual production, the sixth isolation semiconductor pattern layer a6 and the second isolation semiconductor pattern layer a2 can be prepared by the same isolation semiconductor layer; that is, the sixth isolation semiconductor pattern layer a6 and the second isolation semiconductor pattern layer a2 have the same layer and the same material.
  • the first channel semiconductor pattern layer b1 and the third channel semiconductor pattern layer b3 use the same semiconductor material on the basis of the same thickness; that is, in order to simplify the process, reduce the In terms of production cost, in actual production, the first channel semiconductor pattern layer b1 and the third channel semiconductor pattern layer b3 can be prepared by the same semiconductor layer; that is, the first channel semiconductor pattern layer b1 and the third channel semiconductor pattern layer b3
  • the layer b3 is the same layer and the same material.
  • the "same layer and same material" involved in this application means that two (or more than two) pattern layers can be made of the same film, but the two pattern layers are not absolutely at the same height Location. It can be understood that for the same film layer, since there may be different pattern layers under it, the film itself is not completely at the same height position, so it is not necessary to use the same film for multiple pattern layers. Must be at the same height; for example, the fourth isolation semiconductor pattern layer a4 and the second isolation semiconductor pattern layer a2 in FIG. 2 can be prepared from the same isolation semiconductor layer, but they are not at the same height.
  • vertical gate-all-around transistors such as 10 and 20
  • the basis of including semiconductor fins such as Z1 and Z2
  • it also includes other components, such as source (source, S), drain (drain, D), gate (gate, G), well region (well, W), etc.
  • the sidewall shielding bodies 200 are provided on the sides of the 1 , and a gate insulating layer 401 and a gate electrode layer 402 are sequentially arranged on the sides around the channel semiconductor pattern layer 1 and between the two sidewall shielding bodies 200; for FIG. 2 13 and FIG. 23 , and the specific structures of the sidewall shielding body 200 , the gate insulating layer 401 , and the gate layer 402 in FIG. 3 are not illustrated here.
  • the fabrication process may generally include a front end of line (FEOL) and a back end process (FEOL) that performs interconnection after the front end process. back end of line, BEOL).
  • FEOL front end of line
  • BEOL back end process
  • an embodiment of the present application provides a fabrication of a front-end process for a semiconductor device, including:
  • Step 1 forming an initial semiconductor stacked structure P1 on the substrate 01; wherein the initial semiconductor stacked structure P1 includes at least one isolation semiconductor layer and at least one channel semiconductor layer alternately formed on the substrate in sequence.
  • the initial semiconductor stacked structure P1 may be shown with reference to FIG. 6 and FIG. 16 .
  • Step 2 The initial semiconductor stacked structure P1 is etched to form an intermediate semiconductor stacked structure P2 (; wherein, the intermediate semiconductor stacked structure P2 includes an effective channel semiconductor layer C, and the effective channel semiconductor layer C is located between the two isolation semiconductor layers.
  • the effective channel semiconductor layer has a first thickness in the first region s1 and a second thickness in the second region s2; the first thickness is different from the second thickness, and the first region s1 and the second region s2 are different regions.
  • the initial semiconductor stacking result P1 may be etched as shown in FIG. 7 and FIG. 17 , and the intermediate semiconductor stack structure formed may be as shown in FIGS. 8 and 18 .
  • the effective channel semiconductor layer C reference may be made to the subsequent Embodiment 1 and Embodiment 2.
  • Step 3 Etching the intermediate semiconductor stacked structure P2 to form a first semiconductor fin structure F1 in the first region s1 and a second semiconductor fin structure F2 in the second region s2.
  • the intermediate semiconductor stacked structure P2 is etched to form F1 and F2, as shown in FIG. 9 and FIG. 19 .
  • Step 4 Partially etch the isolation semiconductor layers in the first semiconductor fin structure F1 and the second semiconductor fin structure F2 to form spacer grooves 100 , and fill the spacer grooves 100 with insulating dielectric materials to form spacers Shielding body 200 .
  • the sidewall groove 100 may be shown in FIG. 10 and FIG. 20
  • the sidewall shielding body 200 may be shown in FIG. 11 and FIG. 21 .
  • Step 5 Etch the channel semiconductor layer between the two spacer shielding bodies 200 to form a channel groove 300, and form a gate insulating layer 401 and a gate layer in sequence in the channel groove 300 402.
  • the gate insulating layer 401 and the gate layer 402 arranged in sequence may be shown with reference to FIGS. 13 and 23 .
  • Step 1 Step 2, Step 3, Step 4, and Step 5 in the foregoing pre-process will be specifically described below through specific embodiments.
  • the present embodiment provides a front-end process for forming a plurality of vertical gate-all-around transistors in a semiconductor device.
  • the front-end process includes:
  • Step 101 (ie, Step 1 ): As shown in FIG. 6 , a first isolation semiconductor layer A1 and a first channel semiconductor layer B1 are sequentially formed on the substrate 01 to obtain an initial semiconductor stacked structure P1 .
  • the substrate 01 (which may also be referred to as a substrate substrate) may be a silicon (Si) substrate (which may also be referred to as a silicon substrate); 01) firstly form the SiGe layer (ie the first isolation semiconductor layer A1), and then form the Si layer (ie the first channel semiconductor layer B1) on the SiGe layer, thereby forming the initial semiconductor stack structure P1.
  • Si silicon
  • ion implantation may be used for positions corresponding to a plurality of vertical gate-all-around transistors (10, 20) to be formed on the Si substrate Independently provided well regions W are respectively formed.
  • ions can be used for implantation to form corresponding types of well regions.
  • B boron
  • P or As phosphorus or arsenic
  • Step 102 (ie, Step 2): Referring to FIG. 6 to FIG. 7 and FIG. 8 , the first channel semiconductor layer B1 located in the second region s2 is etched and thinned to form an effective channel semiconductor pattern layer C; A second isolation semiconductor layer A2 and a top epitaxial isolation semiconductor layer T are sequentially formed on the effective channel semiconductor pattern layer C to obtain an intermediate semiconductor stacked structure P2 (refer to FIG. 8 ).
  • the effective channel semiconductor pattern layer C is located between the first isolation semiconductor layer A1 and the second isolation semiconductor layer A2, and the effective channel semiconductor pattern layer C has a first thickness in the first region s1 and a thickness in the second region s2. of a second thickness, and the first thickness is different from the second thickness.
  • the effective channel semiconductor pattern layer C is obtained by thinning the second region s2 of the first channel semiconductor layer B1 by etching, that is, the effective channel semiconductor
  • the first thickness of the pattern layer C in the first region s1 is greater than the second thickness in the second region s2; so that the effective channel semiconductor pattern layer C is subsequently formed in the vertical gate around the first region s1 and the second region s2
  • the channel lengths of the transistors are different (for details, please refer to the subsequent related description).
  • the above-mentioned process of etching and thinning the first channel semiconductor layer B1 located in the second region s2 to form the effective channel semiconductor pattern layer C may include: first on the upper surface of the first channel semiconductor layer B1 Apply photoresist (PR), and then use exposure, development, etching and other processes to complete the patterning process in sequence, so as to thin the second region s2 of the first channel semiconductor layer B1 to form different thicknesses.
  • the effective channel semiconductor pattern layer C of the region (s1, s2) (refer to FIG. 7).
  • FIG. 7 is only a schematic illustration of an area where the effective channel semiconductor pattern layer C has two different thicknesses as an example.
  • photoresist can be applied multiple times, and exposure, development, and etching are performed in sequence. and other processes to complete the patterning process to form an effective channel semiconductor pattern layer C with three or more regions of different thicknesses; this application does not make specific restrictions on this, and can be selected according to actual needs.
  • the following embodiments are based on It is illustrated that the effective channel semiconductor pattern layer C has two regions with different thicknesses as an example.
  • the upper surface of the top epitaxial isolation semiconductor layer T can be planarized. The upper surface is polished to ensure the flatness of the upper surface of the top epitaxial isolation semiconductor layer T.
  • Step 103 (ie, Step 3 ): Referring to FIG. 8 to FIG. 9 , the intermediate semiconductor stacked structure P2 is etched to form the first semiconductor stacked fin structure F1 in the first region s1 and the first semiconductor stacked fin structure F1 in the second region s2 . Two semiconductor stacked fin structures F2.
  • the etching of the intermediate semiconductor stacked structure P2 may include: firstly coating the upper surface of the intermediate semiconductor stacked structure P2 with photoresist, and then sequentially using exposure, development, etching, stripping and other processes to complete the patterning process to form A plurality of independently disposed semiconductor stacked fin structures (F1, F2).
  • the parts located in the aforementioned effective channel semiconductor pattern layer C are respectively used as the vertical gate-all-around transistors to be formed.
  • the different channel lengths cl of a plurality of vertical gate-all-around transistors to be formed are determined by the thicknesses of different regions of the aforementioned effective channel semiconductor pattern layer C (that is, by the step 102 to control and adjust); for the widths cw of the channel portions of a plurality of vertical gate-all-around transistors to be formed, in the process of patterning the intermediate semiconductor stacked structure P2, the mask used in the exposure process can be set by setting The width cw and shape of the channel portion of each vertical gate-all-around transistor are respectively controlled (that is, controlled and adjusted by step 103 ).
  • the length cl and width cw of the channel portions of multiple vertical gate-all-around transistors can be controlled and adjusted respectively through one process; at the same time, according to actual needs,
  • the shape of the channel portion of a plurality of vertical gate-all-around transistors can be set, for example, can be cylindrical, cubic, etc.; thereby increasing the channel design freedom of the vertical gate-all-around transistor.
  • Step 104 (ie, Step 4): Referring to FIG. 9 to FIG. 10 , in the first semiconductor stacked fin structure F1 and the second semiconductor stacked fin structure F2, the isolation semiconductors located on both sides of the effective channel semiconductor pattern layer C are separated.
  • the layers (A1, A2) are partially etched to form sidewall grooves 100, and insulating dielectric materials are filled in the sidewall grooves 100 to form a sidewall shield 200 (refer to FIG. 10 to FIG. 11).
  • the insulating dielectric material used for the sidewall shielding body 200 formed in the sidewall recess 100 may be one or more of silicon nitride, silicon oxide, or silicon oxynitride.
  • the insulating dielectric material when filling the sidewall groove 100 between the effective channel semiconductor pattern layer C and the substrate 01 with an insulating dielectric material, the insulating dielectric material may be directly covered with the insulating dielectric material. All areas other than the semiconductor stacked fin structures ( F1 , F2 ) are arranged on the substrate 01 ; of course, it is not limited to this, and only the insulating dielectric material can be filled in the sidewall grooves 100 , and in the subsequent fabrication process , and if necessary, an insulating layer is separately fabricated on the substrate 01 in areas other than the semiconductor stacked fin structures (F1, F2).
  • Step 105 (ie, Step 5): Referring to FIG. 11 to FIG. 12 , etching the effective channel semiconductor pattern layer C between the two spacer shielding bodies 200 to form a channel groove 300 , and forming a channel groove 300 in the channel.
  • a gate insulating layer 401 and a gate layer 402 are formed in sequence in the groove 300 (refer to FIG. 12 to FIG. 13 ).
  • in the above step 105 in the trench recess Forming the gate insulating layer 401 and the gate layer 402 in sequence in the trench 300 may include:
  • HKMG process high-k metal gate, that is, high-k insulating layer + metal gate process
  • a high-k insulating layer (401) and a metal gate layer ( 402) thereby completing the front-end process of a plurality of vertical gate-all-around transistors.
  • an anisotropic etching process can be used to perform etching only in the longitudinal direction. , without performing lateral etching, so that the high dielectric constant insulating layer (401) and the metal gate layer (402) can be fabricated under the protection of the sidewall shielding bodies 200 on both sides.
  • tungsten can be used to first fabricate the gate connecting portion 403 connected to the gate layer 402 , and then deposit an interlayer dielectric layer. dielectric, ILD), and through the etching process, via holes are formed on the interlayer dielectric layer ILD corresponding to the source S, drain D, and gate G positions of each vertical gate ring transistor, and metal (such as tungsten) is filled to complete the source. Fabrication of S, drain D, and gate G.
  • this embodiment provides an FEOL for forming a plurality of vertical gate-all-around transistors in a semiconductor device.
  • the front-end process includes:
  • Step 201 (ie, Step 1): As shown in FIG. 16 , a first isolation semiconductor layer A1, a first channel semiconductor layer B1, a second isolation semiconductor layer A2, a second channel semiconductor layer B2, The third isolation semiconductor layer A3, the first epitaxial isolation semiconductor layer T', and the initial semiconductor stack structure P1.
  • the substrate 01 may be a silicon (Si) substrate; SiGe layers ( Namely A1), Si layer (ie B1), SiGe layer (ie A2), Si layer (ie B2), SiGe layer (ie A3), Si layer (ie T'), thereby forming the initial semiconductor stack structure P1.
  • independently set wells can be formed by ion implantation at positions corresponding to a plurality of vertical gate-all-around transistors to be formed on the Si substrate. District W.
  • Step 202 (ie, Step 2): Referring to FIG. 16 to FIG. 17 , the initial semiconductor stacked structure P1 is etched, and at least the film layer located above the second channel semiconductor layer B2 in the second region s2 is removed to obtain etching and forming a top epitaxial isolation semiconductor layer T on the upper surface of the etched initial semiconductor stacked structure P1 ′ to obtain an intermediate semiconductor stacked structure P2 (refer to FIG. 18 ).
  • the etched initial semiconductor stack structure P1 ′ includes an effective channel semiconductor layer C
  • the effective channel semiconductor layer C includes a first isolation semiconductor layer A1 and a second isolation semiconductor layer C sandwiched between the first isolation semiconductor layer A1 and the second area s2 in the second region s2 a first channel semiconductor layer B1 between the isolation semiconductor layers A2, including the first channel semiconductor layers B1 sandwiched between the first isolation semiconductor layer A1 and the second isolation semiconductor layer A2 in the first region s1, respectively, and The second channel semiconductor layer B2 between the second isolation semiconductor layer A2 and the third isolation semiconductor layer A3.
  • the thickness of the effective channel semiconductor layer C in the first region s1 is the sum of the thicknesses of the first channel semiconductor layer B1 and the second channel semiconductor layer B2, and the thickness in the second region s2 is the thickness of the first channel semiconductor layer Thickness of layer B1.
  • the above-mentioned etching of the initial semiconductor stacked structure P1 may include: firstly coating a photoresist (PR) on the upper surface of the first epitaxial isolation semiconductor layer T', and then sequentially exposing, developing, etching, etc. process, the patterning process of the initial semiconductor stacked structure P1 is completed, and the effective channel semiconductor pattern layer C (refer to FIG. 17 ) having different thicknesses is formed in the first region s1 and the second region s2 .
  • PR photoresist
  • the above-mentioned "at least removing the film layer located above the second channel semiconductor layer B2 in the set region” means that only the film layer located above the second channel semiconductor layer B2 in the second region s2 can be removed, The second channel semiconductor layer B2 is not etched; the second channel semiconductor layer B2 may also be located on the second region s2 while removing the film layer located above the second channel semiconductor layer B2 in the second region s2. Partially thinned.
  • the upper surface of the top epitaxial isolation semiconductor layer T can be planarized, for example, chemical mechanical polishing (chemical mechanical polishing, CMP) can be used to perform a planarization process on the top epitaxial isolation semiconductor layer T.
  • CMP chemical mechanical polishing
  • Step 203 (ie, Step 3): Referring to FIG. 18 to FIG. 19 , the intermediate semiconductor stacked structure P2 is etched to form the first semiconductor stacked fin structure F1 in the first region s1 and the first semiconductor stacked fin structure F1 in the second region s2. Two semiconductor stacked fin structures F2.
  • the etching of the intermediate semiconductor stacked structure P2 may include: firstly coating the upper surface of the intermediate semiconductor stacked structure P2 with photoresist, and then sequentially using exposure, development, etching, stripping and other processes to complete the patterning process to form A plurality of independently disposed semiconductor stacked fin structures (F1, F2).
  • the length and width of the channel portions of a plurality of vertical gate-all-around transistors can be controlled and adjusted respectively through one process.
  • the shape of the channel portion of a plurality of vertical gate-all-around transistors can also be set according to actual needs, for example, it can be cylindrical, cubic, or the like.
  • the different channel lengths cl of a plurality of vertical gate-all-around transistors to be formed are determined by the thickness of the aforementioned effective channel semiconductor pattern layer C (that is, controlled and adjusted by step 201 combined with step 202 ); the schematic , the length cl of the channel portion of the vertical gate-all-around transistor formed by the semiconductor stacked fin structure F2 is the thickness of the first channel semiconductor layer B1 formed in step 201, and the vertical gate-all-around transistor formed by the semiconductor stacked fin structure F1 The length cl of the channel portion is the total thickness of the first channel semiconductor layer B1 and the second channel semiconductor layer B2 formed in step 201 .
  • the mask pattern of the mask used in the exposure process can be set, so that each vertical The width and shape of the channel portion of the gate-all-around transistor are separately controlled; that is, the degree of freedom of channel design of the vertical gate-all-around transistor is increased.
  • Step 204 (ie, Step 4): Referring to FIG. 19 to FIG. 20 , in the first semiconductor stacked fin structure F1 and the second semiconductor stacked fin structure F2, the channel semiconductor layer located in the effective channel semiconductor pattern layer is Partial etching is performed on the isolation semiconductor layers on both sides of (B1, B2) to form spacer grooves 100, and insulating dielectric materials are filled in the spacer grooves 100 to form spacer shields 200 (refer to FIG. 21).
  • the insulating dielectric material used for the sidewall shielding body 200 formed in the sidewall groove 100 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the spacer 100 when the spacer 100 is filled with an insulating dielectric material to form the sidewall shielding body 200, the regions other than the semiconductor stacked fin structures (F1, F2) may be covered with the insulating dielectric material on the substrate 01.
  • the annular sidewall groove 100 can also be filled with insulating dielectric materials, and in the subsequent manufacturing process, the semiconductor stacked fin structures (F1, F2) are arranged on the substrate 01 as required. Insulation layer is made separately for other areas.
  • Step 205 (ie, Step 5): Referring to FIG. 21 to FIG. 22 , the channel semiconductor layers ( B1 , B2 ) located between the two annular spacer shields 200 are etched to form annular channel grooves 300 . A gate insulating layer 401 and a gate layer 402 are formed in sequence in the annular channel groove 300 (refer to FIGS. 22 to 23 ).
  • in the above step 205 in the ring-shaped channel Forming the gate insulating layer 401 and the gate layer 402 in sequence in the groove 300 may include:
  • HKMG process high-k metal gate, that is, high-k insulating layer + metal gate process
  • a high-k insulating layer (401) and a metal gate layer are formed in sequence in the annular channel groove 300 (402), thereby completing the fabrication of the front-end process of a plurality of vertical gate-all-around transistors.
  • BEOL needs to be performed, and the interconnection and wiring process is performed.
  • tungsten may be used to form the gate connection portion 403 connected to the gate layer 402 first, and then the interlayer dielectric layer ILD is deposited, and Through an etching process, via holes are formed on the interlayer dielectric layer ILD corresponding to the source S, drain D, and gate G of each vertical gate-all-around transistor and filled with metal (such as tungsten) to complete the source S, drain D, Fabrication of gate G.
  • first embodiment and the second embodiment are only two FEOLs for forming multiple vertical gate-all-around transistors as shown in the present application, but the present application is not limited to this.
  • the adjustment or change of Example 2 shall be covered within the protection scope of this application.
  • two channel lengths (one is the thickness of the first channel semiconductor layer, and the other is the thickness of the first channel semiconductor layer) can be finally obtained.
  • a vertical gate-all-around transistor whose thickness is the sum of the thicknesses of the first channel semiconductor layer and the second channel semiconductor layer
  • three channel semiconductor layers (upper, middle, and lower) can be fabricated. ), and then vertical gate-all-around transistors with three channel lengths can be produced, that is, the channel length of a vertical gate-all-around transistor is the thickness of the underlying channel semiconductor layer, and the channel length of a vertical gate-all-around transistor is the thickness of the underlying channel semiconductor layer.
  • the relevant fabrication process can refer to the relevant description of the second embodiment, here No longer.
  • two channel semiconductor layers may be fabricated, and only the upper channel semiconductor layer is etched using the method of step 102 in Embodiment 1, that is, the upper channel semiconductor layer is etched Etched into regions with different thicknesses; in this case, the sum of the thicknesses of the patterned upper channel semiconductor layer and the lower channel semiconductor layer in the regions with different thicknesses is used as the channel length of each vertical gate-all-around transistor;
  • Related production process can refer to
  • an effective channel semiconductor pattern layer with regions of different thicknesses can be fabricated by etching, and the regions of the effective channel semiconductor pattern layer with different thicknesses can be subsequently used as The channel length region of the vertical gate-all-around transistor; at the same time, the channel shape of the vertical gate-all-around transistor (such as cylindrical, cubic, etc.) can be controlled according to actual needs through etching during the manufacturing process;
  • the manufacturing method can simultaneously manufacture at least two vertical gate ring transistors with different channel lengths (gate lengths) in one process, that is, the channel design freedom of the vertical gate ring transistor is increased, and a long channel ring can be formed at the same time. gate transistors and short-channel gate-all-around transistors, thereby increasing the application range of semiconductor devices.
  • SiGe is used for the isolation semiconductor layers (such as A1, A2, A3), and the channel semiconductor layers (such as B1, B2) and the epitaxial semiconductor layers (such as T', T) are all used.
  • Si is used as an example to illustrate, but this application is not limited to this.
  • each semiconductor layer can be adjusted according to actual needs; as long as the semiconductor materials used in adjacent semiconductor layers are different; for example, in In some possible implementations, the isolation semiconductor layers (such as A1, A2, A3) can all use Si, and the channel semiconductor layers (such as B1, B2) and the epitaxial semiconductor layers (such as T', T) can all use SiGe (wherein , the composition of Si and Ge can be adjusted according to demand). Of course, the adjacent epitaxial semiconductor layers (such as T' and T) can use the same semiconductor material.

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Abstract

一种半导体器件及其制作方法、电子设备，涉及半导体技术领域，提供一种包括不同栅长垂直环栅晶体管的半导体器件。该半导体器件包括：基板（01）以及位于基板（01）上的第一半导体鳍（Z1）和第二半导体鳍（Z2）；第一半导体鳍（Z1）包括层叠设置的多个隔离半导体图案层和至少一个沟道半导体图案层，其中，每一个沟道半导体图案层夹在两个隔离半导体图案层之间；第二半导体鳍（Z2）包括依次层叠设置的第一隔离半导体图案层、第一沟道半导体层和第二隔离半导体图案层；第一半导体鳍（Z1）中的所有沟道半导体图案层的总厚度与第二半导体鳍（Z2）中的第一沟道半导体层的厚度不同。

Description

半导体器件及其制作方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法、电子设备。
背景技术
随着金属-氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)器件的持续缩进，垂直环栅(vertical gate all around，VGAA)晶体管(下文简称为VGAA器件)逐渐得到应用，也被认为是未来的发展方向。
对于VGAA器件而言，由于沟道方向的更改使得同时制作不同栅长的VGAA器件变得极其困难，因此目前的研究几乎都集中相同栅长的短沟道器件的实现上。
发明内容
本申请提供一种半导体器件及其制作方法、电子设备，提供一种包括不同栅长垂直环栅晶体管的半导体器件。
本申请实施例提供一种半导体器件，包括：基板以及位于基板上的第一半导体鳍和第二半导体鳍；第一半导体鳍包括层叠设置的多个隔离半导体图案层和至少一个沟道半导体图案层，其中，每一个沟道半导体图案层夹在两个隔离半导体图案层之间；第二半导体鳍包括依次层叠设置的第一隔离半导体图案层、第一沟道半导体层和第二隔离半导体图案层；第一半导体鳍中的所有沟道半导体图案层的总厚度与第一沟道半导体图案层的厚度不同。
在该半导体器件中，第一垂直环栅晶体管和第二垂直环栅晶体管具有不同的栅长，从而提高了半导体器件的应用范围，例如可以满足模拟电路对不同栅长的垂直环栅晶体管的需求。
在一些可能实现的方式中，第一半导体鳍中最靠近基板的沟道半导体图案层与第一沟道半导体图案层中的半导体材料相同。在此情况下，在实际制作时，第一半导体鳍中最靠近基板的沟道半导体图案层与第一沟道半导体图案层可以通过同一沟道半导体层制备得到，从而达到简化工艺，降低制作成本的目的。
在一些可能实现的方式中，第一半导体鳍包括依次设置于基板上的第三隔离半导体图案层、第二沟道半导体图案层、第四隔离半导体图案层；第二沟道半导体图案层的厚度与第一沟道半导体图案层的厚度不同；从而能够得到具有不同沟道长度的第一垂直环栅晶体管和第二垂直环栅晶体管。
在一些可能实现的方式中，第三隔离半导体图案层相对于第四隔离半导体图案层靠近基板；第一隔离半导体图案层相对于第二隔离半导体图案层靠近基板；第三隔离半导体图案层与第一隔离半导体图案层的厚度相同，且第三隔离半导体图案层与第一隔离半导体图案层中的半导体材料相同；第四隔离半导体图案层与第二隔离半导体图案层的厚度相同，且第四隔离半导体图案层与第二隔离半导体图案层中的半导体材料相同。
在此情况下，在实际制作时，第三隔离半导体图案层与第一隔离半导体图案层可以通过同一隔离半导体层制备得到，第四隔离半导体图案层与第二隔离半导体图案层可以通过同一隔离半导体层制备得到；也即第三隔离半导体图案层与第一隔离半导体图案层同层同材料，第四隔离半导体图案层与第二隔离半导体图案层同层同材料，从而达到简化工艺，降低制作成本的目的。
在一些可能实现的方式中，第一半导体鳍包括依次设置于基板上的第五隔离半导体图案层、第三沟道半导体图案层、第六隔离半导体图案层、第四沟道半导体图案层、第七隔离半导体图案层；第三沟道半导体图案层的厚度与第一沟道半导体图案层的厚度相同；从而能够得到具有不同沟道长度的第一垂直环栅晶体管和第二垂直环栅晶体管。
在一些可能实现的方式中，第一沟道半导体图案层与第二沟道半导体图案层中的半导体材料相同；在此情况下，在实际制作时，第一沟道半导体图案层与第二沟道半导体图案层可以通过同一沟道半导体层，并采用对局部刻蚀减薄的方式制备得到；也即第一沟道半导体图案层与第二沟道半导体图案层同层同材料；从而达到简化工艺，降低制作成本的目的。
在一些可能实现的方式中，第五隔离半导体图案层相对于第六隔离半导体图案层靠近基板；第一隔离半导体图案层相对于第二隔离半导体图案层靠近基板；第五隔离半导体图案层与第一隔离半导体图案层的厚度相同，且第五隔离半导体图案层与第一隔离半导体图案层中的半导体材料相同；第六隔离半导体图案层与第二隔离半导体图案层的厚度相同，且第六隔离半导体图案层与第二隔离半导体图案层中的半导体材料相同。
在此情况下，在实际制作时，第五隔离半导体图案层与第一隔离半导体图案层可以通过同一隔离半导体层制备得到；第六隔离半导体图案层与第二隔离半导体图案层可以通过同一隔离半导体层制备得到；也即第五隔离半导体图案层与第一隔离半导体图案层同层同材料，第六隔离半导体图案层与第二隔离半导体图案层同层同材料，从而达到简化工艺，降低制作成本的目的。
在一些可能实现的方式中，第一沟道半导体图案层与第三沟道半导体图案层的厚度相同，且第一沟道半导体图案层与第三沟道半导体图案层中的半导体材料相同；在此情况下，在实际制作时，第一沟道半导体图案层与第三沟道半导体图案层可以通过同一半导体层制备得到；也即第一沟道半导体图案层与第三沟道半导体图案层同层同材料，从而达到简化工艺，降低制作成本的目的。
在一些可能实现的方式中，在第一半导体鳍中，在位于每一沟道半导体图案层两侧的隔离半导体图案层四周的侧面均设置有侧墙遮蔽体，在沟道半导体图案层四周的侧面、且位于两个侧墙遮蔽体之间依次设置有栅极绝缘层和栅极层；在第二半导体鳍中，第一隔离半导体图案层和第二隔离半导体图案层四周的侧面均设置有侧墙遮蔽体，在第一沟道半导体层四周的侧面、且位于两个侧墙遮蔽体之间依次设置有栅极绝缘层和栅极层。
在一些可能实现的方式中，基板为硅衬底。
在一些可能实现的方式中，形成隔离半导体层的材料包括：SiGe；形成沟道半导体层的材料包括：Si。
在一些可能实现的方式中，形成隔离半导体层的材料包括：Si；形成沟道半导体层的材料包括：SiGe。
本申请实施例还提供一种半导体器件的制作方法，包括：在基板上形成初始半导体层叠结构；其中，初始半导体层叠结构包括依次交替形成在基板上的至少一个隔离半导体层和至少一个沟道半导体层；对初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构；其中，中间半导体层叠结构包括有效沟道半导体层，有效沟道半导体层位于两层隔离半导体层之间；有效沟道半导体层在第一区域具有第一厚度，在第二区域具有第二厚度；第一厚度与第二厚度不同，第一区域与第二区域为不同的区域；对中间半导体层叠结构进行刻蚀，以在第一区域形成第一半导体鳍状结构，在第二区域形成第二半导体鳍状结构。
采用本申请实施例提供的制作方法，能够通过刻蚀制作出具有不同厚度区域的有效沟道半导体图案层，并将该有效沟道半导体图案层的不同厚度的区域，在后续作为垂直环栅晶体管的沟道长度区域；同时在制作过程中通过刻蚀还能够根据实际的需求控制垂直环栅晶体管的沟道形状(例如圆柱形、立方体形等)；也就是说，采用本申请的制作方法能够通过一次制程同时制作成至少两种具有不同沟道长度(栅长)的垂直环栅晶体管，也即增加了垂直环栅晶体管的沟道设计自由度，可以同时形成长沟道环栅晶体管和短沟道环栅晶体管，进而提高半导体器件的应用范围。
在一些可能实现的方式中，中间半导体层叠结构的最上层设置有顶层外延隔离半导体层；在对中间半导体层叠结构进行刻蚀之前，该半导体器件的制作方法还包括：对顶层外延隔离半导体层的上表面进行平坦化处理；以保证顶层外延隔离半导体层上表面的平整性，以便于后续在顶层外延隔离半导体层上制作其他膜层。
在一些可能实现的方式中，在基板上形成初始半导体层叠结构包括：在基板上依次形成第一隔离半导体层和第一沟道半导体层，以得到初始半导体层叠结构；对所述初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构包括：对位于第二区域的第一沟道半导体层进行刻蚀减薄，以形成有效沟道半导体层；在有效沟道半导体层上依次形成第二隔离半导体层、顶层外延隔离半导体层，以得到中间半导体层叠结构。
在一些可能实现的方式中，在基板上形成初始半导体层叠结构包括：在基板上依次形成第一隔离半导体层、第一沟道半导体层、第二隔离半导体层、第二沟道半导体层、第三隔离半导体层和第一外延隔离半导体层，以得到初始半导体层叠结构；对所述初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构包括：对初始半导体层叠结构进行刻蚀，至少去除第二区域中位于第二沟道半导体层上方的膜层，得到刻蚀后的初始半导体层叠结构；刻蚀后的初始半导体层叠结构包括有效沟道半导体层，有效沟道半导体层在第二区域包括一个沟道半导体层，在第一区域包括两个沟道半导体层；在刻蚀后的初始半导体层叠结构的上表面形成顶层外延隔离半导体层，以得到中间半导体层叠结构。
在一些可能实现的方式中，至少去除第二区域中位于第二沟道半导体层上方的膜层包括：去除第二区域中位于第二沟道半导体层上方的膜层，并减薄第二沟道半导体层在第二区域的厚度。从而在制作过程中可以采用较低刻蚀精度的制作工艺进行，进而降低了制作工艺要求。
在一些可能实现的方式中，在对中间半导体层叠结构进行刻蚀，以在第一区域形成第一半导体鳍状结构，在第二区域形成第二半导体鳍状结构之后，该半导体器件的制作方法还包括：对第一半导体鳍状结构、第二半导体鳍状结构中的隔离半导体层进行部分刻蚀形成侧墙凹槽，并在侧墙凹槽中填充绝缘介质材料形成侧墙遮蔽体；对位于两个侧墙遮蔽体 之间的沟道半导体层进行刻蚀形成沟道凹槽，并在沟道凹槽内形成依次设置的栅极绝缘层和栅极层。
在一些可能实现的方式中，在沟道凹槽内形成依次设置的栅极绝缘层和栅极层包括：采用HKMG工艺，在沟道凹槽内形成依次设置的高介电系数绝缘层和金属栅极层。在此情况下，能够提高制备得到的垂直环栅晶体管的性能，减小栅极漏电量，降低栅极电容，以及垂直环栅晶体管的关键尺寸。
在一些可能实现的方式中，在在基板上形成初始半导体层叠结构之前，所述半导体器件的制作方法还包括：设置基板，并在基板上对应待形成的多个垂直环栅晶体管的位置分别形成阱区。
本申请实施例还提供一种电子设备，其特征在于，包括如前述任一种可能实现的方式中的半导体器件。
附图说明
图1为本申请实施例提供的一种半导体器件的局部结构示意图；
图2为本申请实施例提供的一种半导体器件中的半导体鳍部分的结构示意图；
图3为本申请实施例提供的一种半导体器件中的半导体鳍部分的结构示意图；
图4为本申请实施例提供的一种半导体器件的前道工艺的流程图；
图5为本申请实施例一提供的一种半导体器件的前道工艺的流程图；
图6为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图7为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图8为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图9为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图10为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图11为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图12为本申请实施例一提供的一种半导体器件在制作过程中的结构示意图；
图13为本申请实施例一提供的一种半导体器件在完成前道工艺后的结构示意图；
图14为本申请实施例一提供的一种半导体器件在完成后道工艺后的结构示意图；
图15为本申请实施例二提供的一种半导体器件的前道工艺的流程图；
图16为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图17为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图18为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图19为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图20为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图21为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图22为本申请实施例二提供的一种半导体器件在制作过程中的结构示意图；
图23为本申请实施例二提供的一种半导体器件在完成前道工艺后的结构示意图；
图24为本申请实施例二提供的一种半导体器件在完成后道工艺后的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备中包括设置有多个垂直环栅晶体管的半导体器件。该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品。本申请实施例对该电子设备的具体形式不做特殊限制。
另外，本申请对于上述设置有多个垂直环栅晶体管的半导体器件的具体形式也不做特殊限制；例如，该半导体器件可以为芯片、或者电子设备内部集成有控制电路的基板等。
参考图1所示，该半导体器件包括基板01以及位于基板01上的第一垂直环栅晶体管10和第二垂直环栅晶体管20；其中，第一垂直环栅晶体管10包括第一半导体鳍Z1，第二垂直环栅晶体管20包括第二半导体鳍Z2。其中，图1中示出的半导体器件的局部示意图为了对第一垂直环栅晶体管10的整个沟道区域进行示意，省去栅极连接沟道区域的部分。
如图1所示，在第一半导体鳍Z1和第二半导体鳍Z2中均包括层叠设置的多个隔离半导体图案层1以及至少一个沟道半导体图案层2，并且每一沟道半导图案体层2均夹在两个隔离半导体图案层1之间。其中，图1仅是示意的以第一半导体鳍Z1和第二半导体鳍Z2中均设置有两个隔离半导体图案层1和一个沟道半导体图案层2为例进行说明的。
在该半导体器件中，第一半导体鳍Z1中沟道半导体图案层2的厚度和(即总厚度)与第二半导体鳍Z2中沟道半导体图案层2的厚度之和(即总厚度)不同。对于图1中第一半导体鳍Z1和第二半导体鳍Z2均采用一个沟道半导体图案层2的垂直环栅晶体管而言，即为第一半导体鳍Z1中沟道半导体图案层2的厚度L1与第二半导体鳍Z2中沟道半导体图案层2的厚度L2不同(L1≠L2)。
本领域的技术人员可以理解的是，在垂直环栅晶体管中，沟道半导体图案层2作为该晶体管的沟道层，其厚度即为沟道的长度；当然，在沟道半导体图案层2四周的侧面可以依次设置有栅极绝缘层和栅极层(具体可以参考下文)，对于沟道长度不同的晶体管而言，其栅极长度(即栅长)也必然也不同。也就是说，在本申请实施例提供的半导体器件中，第一垂直环栅晶体管和第二垂直环栅晶体管具有不同的栅长，从而提高了半导体器件的应用范围，例如可以满足模拟电路对不同栅长的垂直环栅晶体管的需求。
本申请中对于垂直环栅晶体管(10、20)的类型不作限制，该垂直环栅晶体管可以为纳米线环栅晶体管(即nanowire FET)，也可以为纳米薄片环栅晶体管(即nanosheet FET)。
需要说明的是，对于上述位于半导体器件中第一垂直环栅晶体管10和第二垂直环栅晶体管20而言，可以理解的是，该半导体器件中包括至少一个第一垂直环栅晶体管10和至少一个第二垂直环栅晶体管20；例如，可以是1000个第一垂直环栅晶体管10，2000个第二垂直环栅晶体管20。对于第一垂直环栅晶体管10和第二垂直环栅晶体管20自身而言，第一垂直环栅晶体管10和第二垂直环栅晶体管20并不是指某两类特定栅长的垂直环栅晶体管，第一垂直环栅晶体管10和第二垂直环栅晶体管20仅是指满足前述特定条件下的两类相对的垂直环栅晶体管；例如，在该半导体器件中包括三种不同沟道长度(也即栅长)的垂直环栅晶体管的情况下，则在该三种不同沟道长度的垂直环栅晶体管中，任意两种不同沟道长度的垂直环栅晶体管可以分别视为前述的第一垂直环栅晶体管10和第二垂直环栅晶体管20。
以下对本申请的半导体器件中的第一半导体鳍Z1、第二半导体鳍Z2中隔离半导体图案层1和沟道半导体图案层2的具体设置方式做进一步的说明。
设置方式一
在一些半导体器件中，如图2所示，第二半导体鳍Z2包括依次设置于基板01上的第一隔离半导体图案层a1、第一沟道半导体图案层b1、第二隔离半导体图案层a2；第一隔离半导体图案层a1相对于第二隔离半导体图案层a2靠近基板01。第一半导体鳍Z1包括依次设置于基板01上的第三隔离半导体图案层a3、第二沟道半导体图案层b2、第四隔离半导体图案层a4；第三隔离半导体图案层a3相对于第四隔离半导体图案层a4靠近基板01。其中，第一沟道半导体图案层b1的厚度与第二沟道半导体图案层b2的厚度不同，也即第一垂直环栅晶体管10和第二垂直环栅晶体管20的沟道长度不同。
在该设置方式下，在一些可能实现的方式中，第三隔离半导体图案层a3与第一隔离半导体图案层a1的厚度相同，且第三隔离半导体图案层a3与第一隔离半导体图案层a1中的半导体材料相同；也就是说，为了简化工艺，降低制作成本，在实际制作时，第三隔离半导体图案层a3与第一隔离半导体图案层a1可以通过同一隔离半导体层制备得到，也即第三隔离半导体图案层a3与第一隔离半导体图案层a1同层同材料。
在一些可能实现的方式中，第四隔离半导体图案层a4与第二隔离半导体图案层a2的厚度相同，且第四隔离半导体图案层a4与第二隔离半导体图案层a2中的半导体材料相同；也就是说，为了简化工艺，降低制作成本，在实际制作时，第四隔离半导体图案层a4与第二隔离半导体图案层a2可以通过同一隔离半导体层制备得到，也即第四隔离半导体图案层a4与第二隔离半导体图案层a2同层同材料。
在一些可能实现的方式中，第一沟道半导体图案层b1与第二沟道半导体图案层b2中的半导体材料相同；也就是说，为了简化工艺，降低制作成本，在实际制作时，第一沟道半导体图案层b1与第二沟道半导体图案层b2可以通过同一沟道半导体层，并采用对局部刻蚀减薄的方式制备得到；也即第一沟道半导体图案层b1与第二沟道半导体图案层b2同层同材料。
设置方式二
在一些半导体器件中，如图3所示，第二半导体鳍Z2包括依次设置于基板01上的第一隔离半导体图案层a1、第一沟道半导体图案层b1、第二隔离半导体图案层a2；第一隔离半导体图案层a1相对于第二隔离半导体图案层a2靠近基板01。第一半导体鳍Z1包括 依次设置于基板01上的第五隔离半导体图案层a5、第三沟道半导体图案层b3、第六隔离半导体图案层a6、第四沟道半导体图案层b4、第七隔离半导体图案层a7；第五隔离半导体图案层a5相对于第七隔离半导体图案层a7靠近基板01。其中，第三沟道半导体图案层b3的厚度与第一沟道半导体图案层b1的厚度相同，则必然的有第三沟道半导体图案层b3与第四沟道半导体图案层b4的厚度之和大于第一沟道半导体图案层b1，也即第一垂直环栅晶体管10和第二垂直环栅晶体管20的沟道长度不同。
在该设置方式下，在一些可能实现的方式中，第五隔离半导体图案层a5与第一隔离半导体图案层a1的厚度相同，且第五隔离半导体图案层a5与第一隔离半导体图案层a1中的半导体材料相同；也就是说，为了简化工艺，降低制作成本，在实际制作时，第五隔离半导体图案层a5与第一隔离半导体图案层a1可以通过同一隔离半导体层制备得到；也即第五隔离半导体图案层a5与第一隔离半导体图案层a1同层同材料。
在一些可能实现的方式中，第六隔离半导体图案层a6与第二隔离半导体图案层a2的厚度相同，且第六隔离半导体图案层a6与所述第二隔离半导体图案层a2中的半导体材料相同；也就是说，为了简化工艺，降低制作成本，在实际制作时，第六隔离半导体图案层a6与第二隔离半导体图案层a2可以通过同一隔离半导体层制备得到；也即第六隔离半导体图案层a6与第二隔离半导体图案层a2同层同材料。
在一些可能实现的方式中，第一沟道半导体图案层b1与第三沟道半导体图案层b3在厚度相同的基础上，两者还采用相同的半导体材料；也就是说，为了简化工艺，降低制作成本，在实际制作时，第一沟道半导体图案层b1与第三沟道半导体图案层b3可以通过同一半导体层制备得到；也即第一沟道半导体图案层b1与第三沟道半导体图案层b3同层同材料。
此处需要说明的是，本申请中所涉及的“同层同材料”是指，两个(或者两个以上)图案层可以通过同一薄膜制成，但两个图案层并不绝对处于同一高度位置。可以理解的是，对于同一薄膜层而言，由于其下方可能设置有不同的图案层，从而使得该薄膜本身并不完全处于同一高度位置，因此对于采用同一薄膜制成的多个图案层并不必然处于同一高度位置；例如，图2中的第四隔离半导体图案层a4与第二隔离半导体图案层a2可以通过同一隔离半导体层制备得到，但两者并不处于同一高度位置。
另外，本领域的技术人员可以理解的是，参考图1所示，对于垂直环栅晶体管(如10、20)而言，其在包括半导体鳍(如Z1、Z2)的基础上，还包括其他的部件，例如源极(source，S)、漏极(drain，D)、栅极(gate，G)、阱区(well，W)等。
示意的，参考图1所示，在一些可能实现的方式中，在第一半导体鳍Z1和第二半导体鳍Z2中，在位于每一沟道半导体图案层2两侧的隔离半导体图案层1四周的侧面均设置有侧墙遮蔽体200，在沟道半导体图案层1四周的侧面、且位于两个侧墙遮蔽体200之间依次设置有栅极绝缘层401和栅极层402；对于图2和图3中侧墙遮蔽体200、栅极绝缘层401、栅极层402的具体结构示意可以参考图13和图23，此处不再示意。
本领域的技术人员可以理解的是，对于上述半导体器件的制作而言，其制作工艺一般可以包括前道工艺(front end of line，FEOL)以及位于前道工艺之后进行互连的后道工艺(back end of line，BEOL)。
如图4所示，本申请实施例提供一种半导体器件的前道工艺的制作，包括：
步骤1：在基板01上形成初始半导体层叠结构P1；其中，初始半导体层叠结构P1包括依次交替形成在基板上的至少一个隔离半导体层和至少一个沟道半导体层。
示例性的，初始半导体层叠结构P1可参考图6和图16所示。
关于初始半导体层叠结构P1中隔离半导体层和沟道半导体层的具体设置方式可以参考后续实施例一和实施例二。
步骤2：对初始半导体层叠结构P1进行刻蚀，以形成中间半导体层叠结构P2(；其中，中间半导体层叠结构P2包括有效沟道半导体层C，有效沟道半导体层C位于两层隔离半导体层之间；有效沟道半导体层在第一区域s1具有第一厚度，在第二区域s2具有第二厚度；第一厚度与第二厚度不同，第一区域s1与第二区域s2为不同的区域。
示例性的，对初始半导体层叠结果P1进行刻蚀可以参考图7和图17所示，形成的中间半导体层叠结构可以参考图8和图18所示。关于有效沟道半导体层C的具体设置方式可以参考后续实施例一和实施例二。
步骤3：对中间半导体层叠结构P2进行刻蚀，以在第一区域s1形成第一半导体鳍状结构F1，在第二区域s2形成第二半导体鳍状结构F2。
示例性的，对中间半导体层叠结构P2进行刻蚀形成F1和F2可以参考图9和图19所示。
步骤4：对第一半导体鳍状结构F1、第二半导体鳍状结构F2中的隔离半导体层进行部分刻蚀形成侧墙凹槽100，并在侧墙凹槽100中填充绝缘介质材料形成侧墙遮蔽体200。
示例性的，侧墙凹槽100可参考图10和图20所示，侧墙遮蔽体200可参考图11和图21所示。
步骤5：对位于两个侧墙遮蔽体200之间的沟道半导体层进行刻蚀形成沟道凹槽300，并在沟道凹槽300内形成依次设置的栅极绝缘层401和栅极层402。
示例性的，沟道凹槽300可参考图12和图2所示，依次设置的栅极绝缘层401和栅极层402可参考图13和图23所示。
以下通过具体实施例对前述的前道工艺中的步骤1、步骤2、步骤3、步骤4、步骤5进行具体说明。
实施例一
如图5所示，本实施例提供一种半导体器件中形成多个垂直环栅晶体管的前道工艺，该前道工艺包括：
步骤101(即步骤1)：如图6所示，在基板01上依次形成第一隔离半导体层A1和第一沟道半导体层B1，得到初始半导体层叠结构P1。
示意的，参考图6所示，在一些可能实现的方式中，基板01(也可以称为衬底基板)可以采用硅(Si)衬底(也可称为硅基板)；在Si衬底(01)上先形成SiGe层(即第一隔离半导体层A1)，在SiGe层上再形成Si层(即第一沟道半导体层B1)，从而形成初始半导体层叠结构P1。
当然，参考图6所示，实际中，可以在形成初始半导体层叠结构P1之前，可以对Si衬底上对应多个待形成的垂直环栅晶体管(10、20)的位置，采用离子注入的方式分别形成独立设置的阱区W。
可以理解的是，针对不同类型的垂直环栅晶体管，可以采用不同类型的离子进行注入 形成相应类型的阱区。例如，在对应待形成的N型垂直环栅晶体管的位置，采用硼(B)离子注入形成P型阱区；在对应待形成的P型垂直环栅晶体管的位置，采用磷或砷(P或As)离子注入形成N型阱区。
步骤102(即步骤2)：参考图6到图7、图8所示，对位于第二区域s2的第一沟道半导体层B1进行刻蚀减薄，以形成有效沟道半导体图案层C；并在有效沟道半导体图案层C上依次形成第二隔离半导体层A2、顶层外延隔离半导体层T，得到中间半导体层叠结构P2(参考图8)。其中，有效沟道半导体图案层C位于第一隔离半导体层A1和第二隔离半导体层A2之间，并且有效沟道半导体图案层C在第一区域s1具有第一厚度，在第二区域s2具有第二厚度的，且第一厚度与第二厚度不同。
参考图7所示，可以理解的是，有效沟道半导体图案层C是通过对第一沟道半导体层B1的第二区域s2进行刻蚀减薄后得到的，也就是说，有效沟道半导体图案层C在第一区域s1的第一厚度大于在第二区域s2的第二厚度；从而能够使得有效沟道半导体图案层C后续在位于第一区域s1和第二区域s2形成的垂直环栅晶体管的沟道长度不同(具体可以参考后续相关描述)。
示意的，上述对位于第二区域s2的第一沟道半导体层B1进行刻蚀减薄，以形成有效沟道半导体图案层C的过程可以包括：先在第一沟道半导体层B1的上表面涂覆光刻胶(photoresist，PR)，然后依次采用曝光、显影、刻蚀等工艺完成图案化过程，以对第一沟道半导体层B1的第二区域s2进行减薄，形成具有不同厚度的区域(s1、s2)的有效沟道半导体图案层C(参考图7)。
当然，图7中仅是示意的以有效沟道半导体图案层C具有两个不同厚度的区域为例进行说明的，实际中可以多次涂覆光刻胶，并依次进行曝光、显影、刻蚀等工艺完成图案化过程，以形成具有三个或者三个以上不同厚度区域的有效沟道半导体图案层C；本申请对此不作具体限制，实际中可以根据需要选择设置，以下实施例均是以有效沟道半导体图案层C具有两个不同厚度的区域为例进行说明的。
另外，为了保证顶层外延隔离半导体层T上表面(也即背离基板01一侧的表面)的平整性，以便于后续在顶层外延隔离半导体层T上制作其他膜层；在一些可能实现的方式中，可以在得到上述中间半导体层叠结构P2之后，对顶层外延隔离半导体层T的上表面进行平坦化处理，例如，可以采用化学机械抛光工艺(chemical mechanical polishing，CMP)对顶层外延隔离半导体层T的上表面进行打磨处理，以保证顶层外延隔离半导体层T上表面的平坦性。
步骤103(即步骤3)：参考图8到图9所示，对中间半导体层叠结构P2进行刻蚀，以在第一区域s1形成第一半导体层叠鳍状结构F1，在第二区域s2形成第二半导体层叠鳍状结构F2。
示意的，对中间半导体层叠结构P2进行刻蚀可以包括：先在中间半导体层叠结构P2的上表面涂覆光刻胶，然后依次采用曝光、显影、刻蚀、剥离等工艺完成图案化过程，形成多个独立设置的半导体层叠鳍状结构(F1、F2)。
需要说明的是，在步骤103中形成的多个独立设置的半导体层叠鳍状结构(F1、F2)中，位于前述有效沟道半导体图案层C的部分，分别作为待形成的垂直环栅晶体管的沟道部分；在此情况下，可以理解的是，多个待形成的垂直环栅晶体管的不同沟道长度cl，由 前述有效沟道半导体图案层C的不同区域的厚度决定(也即由步骤102进行控制调节)；对于多个待形成的垂直环栅晶体管的沟道部分的宽度cw而言，可以在对中间半导体层叠结构P2进行图案化的过程中，通过设置曝光工艺中采用的掩膜版的掩膜图案，对各垂直环栅晶体管的沟道部分的宽度cw、形状等分别进行控制(也即由步骤103进行控制调节)。
也就是说，采用本申请的制作方法能够，根据实际的需要，通过一次制程能够对多个垂直环栅晶体管的沟道部分的长度cl和宽度cw分别进行控制调整；同时，根据实际的需要也可以设置多个垂直环栅晶体管的沟道部分的形状，例如，可以为圆柱形、立方体形等；从而增加了垂直环栅晶体管的沟道设计自由度。
步骤104(即步骤4)：参考图9到图10所示，对第一半导体层叠鳍状结构F1、第二半导体层叠鳍状结构F2中，位于有效沟道半导体图案层C两侧的隔离半导体层(A1、A2)进行部分刻蚀形成侧墙凹槽100，并在侧墙凹槽100中填充绝缘介质材料形成侧墙遮蔽体200(参考图10到图11所示)。
示意的，在侧墙凹槽100中形成的侧墙遮蔽体200采用的绝缘介质材料可以为氮化硅、氧化硅或氮氧化硅中的一种或多种。
需要说明的是，参考图10、图11所示，在对位于有效沟道半导体图案层C与基板01之间的侧墙凹槽100采用绝缘介质材料进行填充时，可以直接将绝缘介质材料覆盖在基板01上设置半导体层叠鳍状结构(F1、F2)以外的全部区域；当然，并不限制于此，也可以仅在侧墙凹槽100中填充绝缘介质材料，并在后续的制作工艺中，根据需要在基板01上设置半导体层叠鳍状结构(F1、F2)以外的区域单独制作绝缘层。
步骤105(即步骤5)：参考图11到图12所示，对位于两个侧墙遮蔽体200之间的有效沟道半导体图案层C进行刻蚀形成沟道凹槽300，并在沟道凹槽300内形成依次设置的栅极绝缘层401和栅极层402(参考图12到图13所示)。
在一些可能实现的方式中，为了提高制备得到的垂直环栅晶体管的性能，减小栅极漏电量，降低栅极电容，以及垂直环栅晶体管的关键尺寸；上述步骤105中，在沟道凹槽300内形成依次设置的栅极绝缘层401和栅极层402可以包括：
采用HKMG工艺(high-k metal gate，也即high-k绝缘层+金属栅极工艺)，在沟道凹槽300内形成依次设置的高介电系数绝缘层(401)和金属栅极层(402)，从而完成多个垂直环栅晶体管的前道工艺。
可以理解的是，采用HKMG工艺时，通过刻蚀工艺形成高介电系数绝缘层(401)和金属栅极层(402)时，可以采用各项异性的刻蚀工艺，仅在纵向进行刻蚀，不进行横向刻蚀，从而在两侧的侧墙遮蔽体200的保护下，即可完成高介电系数绝缘层(401)和金属栅极层(402)的制作。
当然，在完成多个垂直环栅晶体管的前道工艺之后，需要进行后道工艺进行互连布线，本申请对于后道工艺的具体制作过程不作限制，实际中可以根据需要选择设置后道工艺的制作流程。
示意的，参考图13到图14所示，在一些可能实现的方式中，可以采用钨(W)先制作与栅极层402连接的栅极连接部403，然后沉积层间介质层(inter layer dielectric，ILD)，并通过刻蚀工艺在层间介质层ILD上对应各垂直环栅晶体管的源极S、漏极D、栅极G位置形成过孔并填充金属(例如钨)，完成源极S、漏极D、栅极G的制作。
实施例二
如图15所示，本实施例提供一种半导体器件中形成多个垂直环栅晶体管的FEOL，该前道工艺包括：
步骤201(即步骤1)：如图16所示，在基板01上依次形成第一隔离半导体层A1、第一沟道半导体层B1、第二隔离半导体层A2、第二沟道半导体层B2、第三隔离半导体层A3、第一外延隔离半导体层T’，以到初始半导体层叠结构P1。
示意的，参考图16所示，在一些可能实现的方式中，基板01(也可以称为衬底基板)可以采用硅(Si)衬底；在Si衬底(01)上依次形成SiGe层(即A1)、Si层(即B1)、SiGe层(即A2)、Si层(即B2)、SiGe层(即A3)、Si层(即T’)，从而形成初始半导体层叠结构P1。
当然，参考图16所示，实际中，可以在形成初始半导体层叠结构P1之前，对Si衬底上对应多个待形成的垂直环栅晶体管的位置，采用离子注入的方式分别形成独立设置的阱区W。
步骤202(即步骤2)：参考图16到图17所示，对初始半导体层叠结构P1进行刻蚀，至少去除第二区域s2中位于第二沟道半导体层B2上方的膜层，得到刻蚀后的初始半导体层叠结构P1’；并在刻蚀后的初始半导体层叠结构P1’的上表面形成顶层外延隔离半导体层T，以得到中间半导体层叠结构P2(参考图18)。
其中，参考图17所示，刻蚀后的初始半导体层叠结构P1’包括有效沟道半导体层C，该有效沟道半导体层C在第二区域s2包括夹在第一隔离半导体层A1和第二隔离半导体层A2之间的一个第一沟道半导体层B1，在第一区域s1包括分别夹在第一隔离半导体层A1和第二隔离半导体层A2之间的第一沟道半导体层B1，以及第二隔离半导体层A2和第三隔离半导体层A3之间的第二沟道半导体层B2。也就是说，有效沟道半导体层C在第一区域s1的厚度为第一沟道半导体层B1和第二沟道半导体层B2的厚度和，在第二区域s2的厚度为第一沟道半导体层B1的厚度。
示意的，上述对初始半导体层叠结构P1进行刻蚀可以包括：先在第一外延隔离半导体层T’的上表面涂覆光刻胶(photoresist，PR)，然后依次采用曝光、显影、刻蚀等工艺，完成对初始半导体层叠结构P1的图案化过程，形成在第一区域s1和第二区域s2具有不同厚度的有效沟道半导体图案层C(参考图17)。
需要说明的是，上述“至少去除设定区域中位于第二沟道半导体层B2上方的膜层”是指，可以仅去除第二区域s2中位于第二沟道半导体层B2上方的膜层，不对第二沟道半导体层B2进行刻蚀；也可以在去除第二区域s2中位于第二沟道半导体层B2上方的膜层的同时，将第二沟道半导体层B2位于第二区域s2的部分进行减薄。
可以理解的是，上述对第二沟道半导体层B2位于第二区域s2的部分进行刻蚀减薄的制作方式，在制作过程中可以采用较低刻蚀精度的制作工艺进行，进而降低了制作工艺要求。
另外，为了保证顶层外延隔离半导体层T的上表面(也即背离基板01一侧的表面)的平整性，以便于后续在顶层外延隔离半导体层T上制作其他膜层；在一些可能实现的方式中，可以在得到上述中间半导体层叠结构P2之后，对顶层外延隔离半导体层T的上表面进行平坦化处理，例如，可以采用化学机械抛光工艺(chemical mechanical polishing， CMP)对顶层外延隔离半导体层T的上表面进行打磨处理(参考图18)。
步骤203(即步骤3)：参考图18到图19所示，对中间半导体层叠结构P2进行刻蚀，以在第一区域s1形成第一半导体层叠鳍状结构F1，在第二区域s2形成第二半导体层叠鳍状结构F2。
示意的，对中间半导体层叠结构P2进行刻蚀可以包括：先在中间半导体层叠结构P2的上表面涂覆光刻胶，然后依次采用曝光、显影、刻蚀、剥离等工艺完成图案化过程，形成多个独立设置的半导体层叠鳍状结构(F1、F2)。
采用本申请的制作方法能够，根据实际的需要，通过一次制程能够对多个垂直环栅晶体管的沟道部分的长度和宽度分别进行控制调整。同时，根据实际的需要也可以设置多个垂直环栅晶体管的沟道部分的形状，例如，可以为圆柱形、立方体形等。
参考图19所示，多个待形成的垂直环栅晶体管的不同的沟道长度cl，由前述有效沟道半导体图案层C的厚度决定(也即由步骤201结合步骤202控制调节)；示意的，由半导体层叠鳍状结构F2形成的垂直环栅晶体管的沟道部分的长度cl为步骤201中形成的第一沟道半导体层B1的厚度，由半导体层叠鳍状结构F1形成的垂直环栅晶体管的沟道部分的长度cl为步骤201中形成的第一沟道半导体层B1和第二沟道半导体层B2的总厚度。
对于待形成的多个垂直环栅晶体管的沟道部分的宽度而言，可以对中间半导体层叠结构P2进行图案化过程中，通过设置曝光工艺中采用的掩膜版的掩膜图案，对各垂直环栅晶体管的沟道部分的宽度、形状等分别进行控制；也即增加了垂直环栅晶体管的沟道设计自由度。
步骤204(即步骤4)：参考图19到图20所示，对第一半导体层叠鳍状结构F1、第二半导体层叠鳍状结构F2中，位于有效沟道半导体图案层中的沟道半导体层(B1、B2)两侧的隔离半导体层进行部分刻蚀形成侧墙凹槽100，并在侧墙凹槽100中填充绝缘介质材料形成侧墙遮蔽体200(参考图21)。
示意的，在侧墙凹槽100中形成的侧墙遮蔽体200采用的绝缘介质材料可以为氮化硅、氧化硅、氮氧化硅中的一种或多种。
需要说明的是，上述在对侧墙凹槽100中填充绝缘介质材料形成侧墙遮蔽体200时，可以在基板01上设置半导体层叠鳍状结构(F1、F2)以外的区域均覆盖绝缘介质材料；当然，并不限制于此，也可以仅在环形侧墙凹槽100中填充绝缘介质材料，并在后续的制作工艺中，根据需要在基板01上设置半导体层叠鳍状结构(F1、F2)以外的区域单独制作绝缘层。
步骤205(即步骤5)：参考图21到图22，对位于两个环形侧墙遮蔽体200之间的沟道半导体层(B1、B2)进行刻蚀形成环形沟道凹槽300，并在环形沟道凹槽300内形成依次设置的栅极绝缘层401和栅极层402(参考图22到图23)。
在一些可能实现的方式中，为了提高制备得到的垂直环栅晶体管的性能，减小栅极漏电量，降低栅极电容，以及垂直环栅晶体管的关键尺寸；上述步骤205中，在环形沟道凹槽300内形成依次设置的栅极绝缘层401和栅极层402可以包括：
采用HKMG工艺(high-k metal gate，也即high-k绝缘层+金属栅极工艺)，在环形沟道凹槽300内形成依次设置的高介电系数绝缘层(401)和金属栅极层(402)，从而完成多个垂直环栅晶体管的前道工艺的制作。
当然，在完成多个垂直环栅晶体管的FEOL之后，需要进行BEOL，进行互连布线工艺，本申请对于后道工艺的具体制作过程不作限制，实际中可以根据需要设置BEOL的制作流程。
示意的，参考图23到图24所示，在一些可能实现的方式中，可以采用钨(W)先制作与栅极层402连接的栅极连接部403，然后沉积层间介质层ILD，并通过刻蚀工艺在层间介质层ILD上对应各垂直环栅晶体管的源极S、漏极D、栅极G位置形成过孔并填充金属(例如钨)，完成源极S、漏极D、栅极G的制作。
需要说明的是，前述实施例一以及实施例二仅是本申请示意的给出的两种形成多个垂直环栅晶体管的FEOL，但本申请并不限制于此，任何基于实施例一以及实施例二的调整或变化都应涵盖在本申请的保护范围内。
例如，相比于实施例二中在步骤201中制作两个沟道半导体层(B1、B2)，从而最终能够得到两种沟道长度(一种为第一沟道半导体层的厚度，另一种为第一沟道半导体层和第二沟道半导体层的厚度和)的垂直环栅晶体管而言，在另一些可能实现的方式中，可以制作三个沟道半导体层(上、中、下)，进而也就可以制作得到三种沟道长度的垂直环栅晶体管，也即一种垂直环栅晶体管的沟道长度为下层沟道半导体层的厚度，一种垂直环栅晶体管的沟道长度为下层和中层沟道半导体层的厚度之和，另一种垂直环栅晶体管的沟道长度为三层沟道半导体层的厚度之和；相关制作过程可以参考实施例二的相关描述，此处不再赘述。
又例如，在一些可能实现的方式中，可以制作两个沟道半导体层，仅对上层的沟道半导体层采用实施例一中步骤102的方式进行刻蚀，也即将上层的沟道半导体层刻蚀为具有不同厚度的区域；在此情况下，图案化后的上层沟道半导体层在不同厚度的区域与下层沟道半导体层的厚度之和，分别作为各垂直环栅晶体管的沟道长度；相关制作过程可以参考
实施例一、实施例二的相关描述，此处不再赘述。
综上所述，采用本申请实施例提供的制作方法，能够通过刻蚀制作出具有不同厚度区域的有效沟道半导体图案层，并将该有效沟道半导体图案层的不同厚度的区域，后续作为垂直环栅晶体管的沟道长度区域；同时在制作过程中通过刻蚀还能够根据实际的需求控制垂直环栅晶体管的沟道形状(例如圆柱形、立方体形等)；也就是说，采用本申请的制作方法能够通过一次制程同时制作成至少两种具有不同沟道长度(栅长)的垂直环栅晶体管，也即增加了垂直环栅晶体管的沟道设计自由度，可以同时形成长沟道环栅晶体管和短沟道环栅晶体管，进而提高半导体器件的应用范围。
另外，需要说明的是，前述实施例均是以隔离半导体层(如A1、A2、A3)采用SiGe，沟道半导体层(如B1、B2)、外延半导体层(如T’、T)均采用Si为例进行说明的，但本申请并不限制于此，根据实际的需要可以对各半导体层采用的半导体材料进行调整；只要保证相邻的半导体层采用的半导体材料不同即可；例如，在一些可能实现的方式中，隔离半导体层(如A1、A2、A3)可以均采用Si，沟道半导体层(如B1、B2)、外延半导体层(如T’、T)可以均采用SiGe(其中，Si、Ge的组分可以根据需求调节)。当然相邻设置的外延半导体层(如T’和T)可以采用相同的半导体材料。
另外，对于前述半导体器件实施例中的相关设置结构，可以参考上述半导体器件制作方法；对于上述半导体器件制作方法中其他的相关内容，可以对应的参考前述半导体器件 实施例中的对应部分，此处不再一一赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种半导体器件，其特征在于，包括：基板以及位于所述基板上的第一半导体鳍和第二半导体鳍；
    所述第一半导体鳍包括层叠设置的多个隔离半导体图案层和至少一个沟道半导体图案层，其中，每一个沟道半导体图案层夹在两个隔离半导体图案层之间；
    所述第二半导体鳍包括依次层叠设置的第一隔离半导体图案层、第一沟道半导体层和第二隔离半导体图案层；
    所述第一半导体鳍中的所有沟道半导体图案层的总厚度与所述第一沟道半导体图案层的厚度不同。
  2. 根据权利要求1所述的半导体器件，其特征在于，
    所述第一半导体鳍中最靠近所述基板的沟道半导体图案层与所述第一沟道半导体图案层中的半导体材料相同。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，
    所述第一半导体鳍包括依次设置于所述基板上的第三隔离半导体图案层、第二沟道半导体图案层、第四隔离半导体图案层；
    所述第二沟道半导体图案层的厚度与所述第一沟道半导体图案层的厚度不同。
  4. 根据权利要求3所述的半导体器件，其特征在于，
    所述第三隔离半导体图案层相对于所述第四隔离半导体图案层靠近所述基板；
    所述第一隔离半导体图案层相对于所述第二隔离半导体图案层靠近所述基板；
    所述第三隔离半导体图案层与所述第一隔离半导体图案层的厚度相同，且所述第三隔离半导体图案层与所述第一隔离半导体图案层中的半导体材料相同；
    所述第四隔离半导体图案层与所述第二隔离半导体图案层的厚度相同，且所述第四隔离半导体图案层与所述第二隔离半导体图案层中的半导体材料相同。
  5. 根据权利要求1或2所述的半导体器件，其特征在于，
    所述第一半导体鳍包括依次设置于所述基板上的第五隔离半导体图案层、第三沟道半导体图案层、第六隔离半导体图案层、第四沟道半导体图案层、第七隔离半导体图案层；
    所述第三沟道半导体图案层的厚度与所述第一沟道半导体图案层的厚度相同。
  6. 根据权利要求5所述的半导体器件，其特征在于，
    所述第五隔离半导体图案层相对于所述第六隔离半导体图案层靠近所述基板；
    所述第一隔离半导体图案层相对于所述第二隔离半导体图案层靠近所述基板；
    所述第五隔离半导体图案层与所述第一隔离半导体图案层的厚度相同，且所述第五隔离半导体图案层与所述第一隔离半导体图案层中的半导体材料相同；
    所述第六隔离半导体图案层与所述第二隔离半导体图案层的厚度相同，且所述第六隔离半导体图案层与所述第二隔离半导体图案层中的半导体材料相同。
  7. 根据权利要求1-6任一项所述的半导体器件，其特征在于，
    在所述第一半导体鳍中，在位于每一所述沟道半导体图案层两侧的隔离半导体图案层四周的侧面均设置有侧墙遮蔽体，在所述沟道半导体图案层四周的侧面、且位于两个所述侧墙遮蔽体之间依次设置有栅极绝缘层和栅极层；
    在所述第二半导体鳍中，所述第一隔离半导体图案层和所述第二隔离半导体图案层四周的侧面均设置有侧墙遮蔽体，在所述第一沟道半导体层四周的侧面、且位于两个所述侧墙遮蔽体之间依次设置有栅极绝缘层和栅极层。
  8. 一种半导体器件的制作方法，其特征在于，包括：
    在基板上形成初始半导体层叠结构；其中，所述初始半导体层叠结构包括依次交替形成在所述基板上的至少一个隔离半导体层和至少一个沟道半导体层；
    对所述初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构；其中，所述中间半导体层叠结构包括有效沟道半导体层，所述有效沟道半导体层位于两层隔离半导体层之间；所述有效沟道半导体层在第一区域具有第一厚度，在第二区域具有第二厚度；所述第一厚度与所述第二厚度不同，所述第一区域与所述第二区域为不同的区域；
    对所述中间半导体层叠结构进行刻蚀，以在所述第一区域形成第一半导体鳍状结构，在所述第二区域形成第二半导体鳍状结构。
  9. 根据权利要求7所述的半导体器件的制作方法，其特征在于，
    所述中间半导体层叠结构的最上层设置有顶层外延隔离半导体层；
    所述在对所述中间半导体层叠结构进行刻蚀之前，所述半导体器件的制作方法还包括：
    对所述顶层外延隔离半导体层的上表面进行平坦化处理。
  10. 根据权利要求8或9所述的半导体器件的制作方法，其特征在于，
    所述在基板上形成初始半导体层叠结构包括：
    在所述基板上依次形成第一隔离半导体层和第一沟道半导体层，以得到所述初始半导体层叠结构；
    所述对所述初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构包括：
    对位于所述第二区域的所述第一沟道半导体层进行刻蚀减薄，以形成所述有效沟道半导体层；
    在所述有效沟道半导体层上依次形成第二隔离半导体层、顶层外延隔离半导体层，以得到所述中间半导体层叠结构。
  11. 根据权利要求8或9所述的半导体器件的制作方法，其特征在于，
    所述在基板上形成初始半导体层叠结构包括：
    在基板上依次形成第一隔离半导体层、第一沟道半导体层、第二隔离半导体层、第二沟道半导体层、第三隔离半导体层和第一外延隔离半导体层，以得到所述初始半导体层叠结构；
    所述对所述初始半导体层叠结构进行刻蚀，以形成中间半导体层叠结构包括：
    对所述初始半导体层叠结构进行刻蚀，至少去除所述第二区域中位于所述第二沟道半导体层上方的膜层，得到刻蚀后的初始半导体层叠结构；所述刻蚀后的初始半导体层叠结构包括所述有效沟道半导体层，所述有效沟道半导体层在所述第二区域包括一个沟道半导体层，在所述第一区域包括两个沟道半导体层；
    在所述刻蚀后的初始半导体层叠结构的上表面形成顶层外延隔离半导体层，以得到所述中间半导体层叠结构。
  12. 根据权利要求11所述的半导体器件的制作方法，其特征在于，
    所述至少去除所述第二区域中位于所述第二沟道半导体层上方的膜层包括：
    去除所述第二区域中位于所述第二沟道半导体层上方的膜层，并减薄所述第二沟道半导体层在所述第二区域的厚度。
  13. 根据权利要求8-12任一项所述的半导体器件的制作方法，其特征在于，
    在所述对所述中间半导体层叠结构进行刻蚀，以在所述第一区域形成第一半导体鳍状结构，在所述第二区域形成第二半导体鳍状结构之后，还包括：
    对所述第一半导体鳍状结构、第二半导体鳍状结构中的隔离半导体层进行部分刻蚀形成侧墙凹槽，并在所述侧墙凹槽中填充绝缘介质材料形成侧墙遮蔽体；
    对位于两个所述侧墙遮蔽体之间的沟道半导体层进行刻蚀形成沟道凹槽，并在所述沟道凹槽内形成依次设置的栅极绝缘层和栅极层。
  14. 根据权利要求13所述的半导体器件的制作方法，其特征在于，
    所述在所述沟道凹槽内形成依次设置的栅极绝缘层和栅极层包括：
    采用HKMG工艺，在所述沟道凹槽内形成依次设置的高介电系数绝缘层和金属栅极层。
  15. 一种电子设备，其特征在于，包括如权利要求1-7任一项所述的半导体器件。
PCT/CN2020/099219 2020-06-30 2020-06-30 半导体器件及其制作方法、电子设备 WO2022000257A1 (zh)

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