TWI579905B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI579905B
TWI579905B TW104134210A TW104134210A TWI579905B TW I579905 B TWI579905 B TW I579905B TW 104134210 A TW104134210 A TW 104134210A TW 104134210 A TW104134210 A TW 104134210A TW I579905 B TWI579905 B TW I579905B
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hydrogen
dielectric material
substrate
trenches
semiconductor structure
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TW201639010A (zh
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周振成
張簡旭珂
吳政達
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台灣積體電路製造股份有限公司
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Description

半導體結構及其製造方法
本揭露有關於一種半導體元件，特別是有關於一種鰭式場效電晶體。
雙閘極金氧半場效電晶體(Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors,Double-Gate MOSFETs)是一種合併兩個閘極到單一元件中的金氧半場效電晶體。該元件因結構包含從基板延伸出來的薄「鰭」而被稱為鰭式場效電晶體。雙閘極意指雙側通道上存在閘極且閘極可從通道兩側來控制。此外，鰭式場效電晶體可降低短通道效應並提供較高的電流。其他種鰭式場效電晶體結構可能同時包含三個或更多的閘極。
依據本揭露之一些實施方式，一種半導體結構的製造方法包含下列步驟：在基板中形成複數個溝槽，其中溝槽定義出至少一鰭狀結構於其間。對鰭狀結構含氫氣體退火。在溝槽中形成介電材料。降低溝槽中的介電材料。
依據本揭露之一些實施方式，一種半導體結構的製造方法包含下列步驟：在具有含氫氣體的環境下退火基板，其中基板具有複數個鰭狀結構以及至少一溝槽，鰭狀結構設置在基板上，且至少一溝槽將鰭狀結構隔開。以介電材料填滿溝槽。移除介電材料的頂部以暴露出鰭狀結構的頂部。
依據本揭露之一些實施方式，一種半導體結構包含：基板，其具有複數個溝槽，以定義出至少一鰭狀結構於其間。氫基終端表面。介電材料，其設置在溝槽中，且環繞該鰭狀結構之底部。
10~90‧‧‧步驟
110‧‧‧硬式罩幕層
112‧‧‧開口
115‧‧‧阻障層
120‧‧‧基板
122‧‧‧溝槽
124‧‧‧鰭狀結構
130‧‧‧第一墊層
140‧‧‧第二墊層
150‧‧‧介電材料
B‧‧‧底面
US‧‧‧頂部
BS‧‧‧埋設部
S‧‧‧側牆
α‧‧‧錐角
第1圖繪示依據本揭露多個實施方式之半導體結構的製造方法流程圖。
第2圖至第9圖繪示依據本揭露多個實施方式之半導體結構在不同階段的橫剖面圖。
以下的說明將提供許多不同的實施方式或實施例來實施本揭露的主題。元件或排列的具體範例將在以下討論以簡化本揭露。當然，這些描述僅為部分範例且本揭露並不以此為限。例如，將第一特徵形成在第二特徵上或上方，此一敘述不但包含第一特徵和第二特徵直接接觸的實施方式，也包含其他特徵形成在第一特徵與第二特徵之間，且在此情形下第一特 徵和第二特徵不會直接接觸的實施方式。此外，本揭露可能會在不同的範例中重複標號或文字。重複的目的是為了簡化及明確敘述，而非界定所討論之不同實施方式及配置間的關係。
此外，空間相對用語如「下面」、「下方」、「低於」、「上面」、「上方」及其他類似的用語，在此是為了方便描述圖中的一個元件或特徵和另一個元件或特徵的關係。空間相對用語除了涵蓋圖中所描繪的方位外，該用語更涵蓋裝置在使用或操作時的其他方位。也就是說，當該裝置的方位與圖式不同(旋轉90度或在其他方位)時，在本文中所使用的空間相對用語同樣可相應地進行解釋。
第1圖繪示依據本揭露多個實施方式之半導體結構的製造方法流程圖。第2圖至第9圖繪示依據本揭露多個實施方式之半導體結構在不同階段的橫剖面圖。製造方法以步驟10開始，步驟10在基板120上形成硬式罩幕層110(如第2圖所示)。方法繼續進行到步驟20，步驟20在基板120中形成溝槽122(如第3圖所示)。下一個是步驟30，步驟30對基板120進行含氫氣體退火(如第3圖所示)。繼續進行到步驟40，步驟40在溝槽122的側牆S及底面B上形成第一墊層130(如第4圖所示)。接著進行步驟50，步驟50在第一墊層130上形成第二墊層140(如第5圖所示)。下一個是步驟60，步驟60以介電材料150填滿溝槽122(如第6圖所示)。繼續進行步驟70，步驟70將位於溝槽122外多餘的介電材料150移除(如第7圖所示)。下一個是步驟80，步驟80移除硬式罩幕層110(如第8圖所示)。 最後是步驟90，步驟90降低溝槽122中的介電材料150(如第9圖所示)。
請參考第2圖。硬式罩幕層110形成在基板120上，且此硬式罩幕層110具有開口112於其中，藉此定義將在後續步驟形成的鰭狀結構。基板120的材質可為半導體材料，例如鑽石(diamond)、矽(Si)、鍺(Ge)、碳化矽(silicon carbide,SiC)、矽鍺(silicon-germanium,SiGe)或上述之任意組合。舉例來說，基板120可為摻雜或未摻雜之塊狀矽。其他如多層結構基板、帶有摻雜物濃度梯度的基板或混和指向基板亦能使用來作為基板120。
硬式罩幕層110的材質可為對水分子(H20)及氧(O)有阻障效果的材料。在一些實施方式中，硬式罩幕層110的材質可為例如氮化矽(Si3N4)。硬式罩幕層110的厚度範圍為約400Å到約2000Å。例如，硬式罩幕層110是由化學氣相沉積(chemical vapor deposition,CVD)、低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)或其他沉積方式所形成。
「約」這個用語可被用於表示任何數量上的調整，且該調整可容許不影響其基本功能之改變。舉例來說，本揭露所揭露之硬式罩幕層110的厚度範圍為約400Å到約2000Å，但只要硬式罩幕層110的阻障能力並未實質上改變，其厚度亦可略小於400Å。
阻障層115可於硬式罩幕層110形成前先被形成在基板120上。阻障層115的材質可為能夠提升硬式罩幕層110與基板120之間黏合力的材料。舉例來說，在一些實施方式中，阻障層115的材質可為氧化矽(SiO2)。阻障層115的厚度範圍為約50Å到約200Å。阻障層115可由例如熱氧化、化學氣相沉積(chemical vapor deposition,CVD)或其他沉積方式所形成。
雖然第2圖繪示為具有夾設在硬式罩幕層110與基板120之間的阻障層115，但此阻障層115也是可以被省略的。在一些實施方式中，若硬式罩幕層110與基板120之間的黏合力是在可接受的程度，硬式罩幕層110也可以直接形成在基板120上而不需要阻障層115。
硬式罩幕層110與阻障層115被圖案化以形成開口112於其中並使部分的基板120暴露出來，其中被暴露出來的部分將在後續步驟中形成溝槽。硬式罩幕層110與阻障層115可藉由光微影(photolithography)及蝕刻製程而形成圖案化結構。光微影及蝕刻製程包括光阻塗佈、曝光、顯影、蝕刻及光阻移除。舉例來說，光阻可以旋轉塗佈(spin coating)的方式塗布於硬式罩幕層110上。接著光阻將被預烤以去除多餘的光阻溶劑。在預烤之後，光阻將被暴露在帶有圖案訊號的光線中。在暴光後，光阻將會產生化學變化，使其一部分可溶於顯影劑中。在顯影之前，可先進行曝光後烘烤(post-exposure bake,PEB)，藉此降低因入射光的破壞性及建設性干涉圖案所造成之駐波現象。接著，顯影劑將被塗佈在光阻上，藉此移除 部分可溶於顯影劑中的光阻。接著，殘餘的光阻將被硬烤以固化剩餘的光阻。硬式罩幕層110及阻障層115沒被殘餘光阻保護到的部分將被蝕刻掉，藉以形成開口112。硬式罩幕層110及阻障層115的蝕刻可藉由例如活性離子蝕刻(reactive-ion etching,RIE)的方式進行。
活性離子蝕刻(reactive-ion etching,RIE)是一種有別於溼式蝕刻的乾式蝕刻方式。活性離子蝕刻使用化學活性電漿以形成開口112。電漿在低壓的環境下(例如：真空)由一電磁場所產生。由化學活性電漿產生的高能離子將撞擊硬式罩幕層110與阻障層115並與其反應。在一些實施方式中，以氟碳(fluorocarbon)或氫氟烴(hydrofluorocarbon)為基礎的活性離子蝕刻可被用來形成開口112。
蝕刻完硬式罩幕層110與阻障層115後，光阻可以例如電漿灰化(plasma ashing)或剝離的方式從硬式罩幕層110上被移除。電漿灰化係使用電漿源以產生單原子活性物質，例如氧或氟。此活性物質和光阻結合後將形成灰燼，此灰燼可被真空幫浦移除。剝離的方式係使用光阻剝離劑，例如丙酮(acetone)或苯酚溶劑(phenol solvent)，將硬式罩幕層110上的光阻移除。
在硬式罩幕層110與阻障層115被圖案化後，基板120上的天然氧化物可藉由清洗製程來移除。在一些實施方式中，當基板120的成分為矽(Si)時，基板120的天然氧化物可以用氫氟酸(hydrofluoric acid,HF)來移除。清洗製程可以選擇 實施或不實施。在一些實施方式中，若基板120上的天然氧化物是可接受的，則清洗製程也可以選擇省略不實施。
請參考第3圖。溝槽122在基板120上形成。溝槽122定義了鰭狀結構124。亦即，溝槽122分離了鰭狀結構124。基板120暴露的部分透過開口112以蝕刻製程移除，例如活性離子蝕刻(reactive-ion etching,RIE)，藉以在基板120上形成溝槽122。
在一些實施方式中，以氯(Cl)或溴(Br)為基礎的活性離子蝕刻(reactive-ion etching,RIE)可用來形成溝槽122。溝槽122至少其中之一的深度範圍為約0.3μm到約0.5μm。溝槽122至少其中之一具有至少一側牆S、一底面B及一錐角α，此錐角α係由側牆S與底面B的延伸平面所夾而成。溝槽122之椎角α的角度為約78°到約88°。
於形成鰭狀結構124後，對鰭狀結構124與基板120進行含氫氣體退火，藉此平滑化溝槽122的側牆S及底面B。也就是說，在一個包含有含氫氣體的環境下，對鰭狀結構124與基板120進行退火。上述之含氫氣體例如可包含蒸汽(H2O)、氨氣(NH3)或其組合。在一些實施方式中，上述之含氫氣體退火的溫度範圍為約攝氏500°至約攝氏1100°。如果含氫氣體退火的溫度低於約攝氏500°，則含氫氣體退火可能無法平滑化溝槽122的側牆S及底面B。若含氫氣體退火的溫度高於攝氏1100°，則含氫氣體退火的過程將實質上增加半導體製程的熱預算。在一些實施方式中，該含氫氣體退火的溫度範圍為 約攝氏790°至約攝氏950°。氫氣的分壓為約1 torr至約900 torr。
「約」這個用語可被用於表示任何數量上的調整，且該調整可容許不影響其基本功能之改變。舉例來說，本揭露所揭露之含氫氣體退火的溫度範圍為約攝氏500°至約攝氏1100°，但只要平滑的能力不產生實質上的改變，含氫氣體退火的溫度亦可略低於攝氏500°。
含氫氣體退火會將溝槽122的側牆S與底面B的至少一部分轉變為氫基終端(hydrogen-terminated)表面。氫基終端(hydrogen-terminated)表面至少有一懸鍵(dangling bond)與至少一氫原子鍵結。當基板120及/或鰭狀結構124的材質為矽(Si)時，氫基終端表面具有至少一矽氫(Si-H)鍵結。
含氫氣體退火能修復基板120及/或鰭狀結構124於蝕刻溝槽122時所產生的結構損傷，並平滑化溝槽122的側牆S與底面B。如果溝槽122的側牆S與底面B是粗糙的，則因粗糙表面所形成的角落或尖端處可能會在鰭狀結構124上造成應力集中而發生破裂。在一些實施方式中，由於溝槽122的側牆S與底面B已藉由含氫氣體退火而平滑化，因此當有撓曲力施加到鰭狀結構124上時，該撓曲力能均勻的分散在鰭狀結構124上，並且避免裂縫的發生甚至成長。在一些實施方式中，當基板120及/或鰭狀結構124的材質為矽(Si)時，溝槽122的側牆S與底面B可能會被平滑化到原子等級的程度。
請參考第4圖。第一墊層130形成在溝槽122的側牆S與底面B上。舉例來說，在一些實施方式中，第一墊層130 的材質可為氧化矽(SiO2)。第一墊層130的厚度範圍為約5Å到約100Å。第一墊層130可以例如臨場熱蒸氣產生技術(in-situ generated steam,ISSG)熱氧化而製成。在一些實施方式中，第一墊層130的形成溫度範圍為約攝氏800°至約攝氏1200°。
雖然第4圖具有形成在溝槽122的側牆S與底面B上的第一墊層130，但此第一墊層130也可以被省略。在一些實施方式中，若基板120及/或鰭狀結構124的結構損傷是在可接受的程度，也可以在沒有第一墊層130的情況下，將介電材料形成在溝槽122中。
在形成第一墊層130後，可對基板120與鰭狀結構124進行退火，以進一步修復基板120及/或鰭狀結構124於蝕刻溝槽122時所產生的結構損傷。在一些實施方式中，基板120與鰭狀結構124可在無氧氣的環境下進行退火。在一些實施方式中，上述之退火的溫度範圍為約攝氏900°至約攝氏1200°。在一些實施方式中，上述退火的時間為約15分鐘到約60分鐘。本段所述的退火可以選擇實施或不實施。在一些實施方式中，若基板120與鰭狀結構124的結構損傷在可接受的程度，此一退火也是可以省略的。
請參考第5圖。第二墊層140形成在第一墊層130上。在一些實施方式中，第二墊層140的材質可為例如氧化矽(SiO2)。第二墊層140的厚度範圍為約10Å到約100Å。第二墊層140可以例如化學氣相沉積(chemical vapor deposition,CVD)，特別是電漿輔助原子層沉積(Plasma-Enhanced Atomic Layer Deposition,PEALD)而形成。
雖然第5圖具有形成在第一墊層130上的第二墊層140，但此第二墊層140也是可以被省略的。在一些實施方式中，若基板120及/或鰭狀結構124的結構損傷是在可接受的程度，也可以在沒有第二墊層140的情況下，將介電材料形成在溝槽122中。
請參考第6圖。介電材料150填滿溝槽122。介電材料150可包含例如氧化矽(SiO2)、氧化氮(Si3N4)、氮氧化矽(SiOxNy)或其組合物。在一些實施方式中，介電材料150可以例如化學氣相沉積(chemical vapor deposition,CVD)的方式形成。在一些實施方式中，介電材料150可為流動性介電材料以改善溝槽填充能力。流動性的填充材料包含例如氫倍半矽氧烷(hydrogen sisesquioxane,HSQ)、聚芳醚(poly-arylene ethers,PAE)、多孔性矽氧化物(也就是乾凝膠或氣凝膠)、甲基倍半矽氧烷(methyl silsesquioxane,MSQ)、甲基倍半矽氧烷(methyl silsesquioxane,MSQ)/氫倍半矽氧烷(hydrogen sisesquioxane,HSQ)、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(perhydro-polysilazane,PSZ)、矽酸鹽(silicate)、矽氧烷(siloxane)或其組合。流動性介電材料可以例如旋轉塗佈的方式形成。
然後，可對流動性介電材料進行固化製程。在固化製程中，流動性介電材料將被烘乾以除去多餘的溶劑，並固化流動性介電材料。在一些實施方式中，固化製程的溫度範圍為約攝氏150°至約攝氏500°。
請參考第7圖。藉由移除製程移除在溝槽122外的多餘介電材料150。在一些實施方式中，多餘的介電材料150可藉由化學機械研磨(chemical mechanical polishing,CMP)的方式而移除。在一些實施方式中，也可以在化學機械研磨後結合電漿回蝕進一步去除多餘的介電材料150。硬式罩幕層110可被當作是研磨終止層，以保護其下的鰭狀結構124免於受到化學機械研磨的傷害。
請參考第8圖，可利用蝕刻製程來移除硬式罩幕層110，上述之蝕刻製程例如可為濕式蝕刻製程。在一些實施方式中，當硬式罩幕層110的材質為氮化矽(Si3N4)時，可使用熱磷酸(H3PO4)來移除硬式罩幕層110。
請參考第9圖。降低溝槽122中的介電材料150。亦即，移除溝槽122中的介電材料150的頂部。舉例來說，可藉由濕式蝕刻製程來移除介電材料150。在一些實施方式中，當介電材料150包含氧化矽(SiO2)時，可使用氫氟酸(HF)來降低溝槽122中的介電材料150。
溝槽122的至少一側牆S將被分離為頂部US與埋設部BS。在降低介電材料150的過程中，位於頂部US上的第一墊層130、第二墊層140與介電材料層150將會被一併移除。甚至，當阻障層115、第一墊層130、第二墊層140與介電材料150的材質本質上相同時，例如材質均為氧化矽(SiO2)時，阻障層115也會在降低介電材料150的過程中被移除。因此，在降低介電材料150後，頂部US將因為沒有第一墊層130、第二 墊層140與介電材料150而暴露，而埋設部BS則仍會被第一墊層130、第二墊層140及/或介電材料150所覆蓋。
由於鰭狀結構124與基板120在第一墊層130形成前被含氫氣體退火，因此存在氫基終端介面於第一墊層130與鰭狀結構124和基板120之間。也就是說，存在於第一墊層130與鰭狀結構124和基板120之間的氫基終端介面有至少一懸鍵結與至少一氫原子鍵結。當鰭狀結構124與基板120的材質為矽(Si)時，存在於第一墊層130與鰭狀結構124和基板120之間的介面具有至少一矽氫(Si-H)鍵結。甚至，當鰭狀結構124與基板120的材質為矽(Si)時，存在於第一墊層130與鰭狀結構124和基板120之間的介面可會被平滑化到原子等級的程度。
在第9圖中，側牆S的至少一埋設部BS與溝槽122的底面150為氫基終端表面。亦即，埋設部BS具有至少一懸鍵與至少一氫原子鍵結，及/或底面B有至少一懸鍵與至少一氫原子鍵結。當鰭狀結構124及/或基板120的材質為矽(Si)時，埋設部BS可具有至少一矽氫(Si-H)鍵結，及/或底面B可具有至少一矽氫(Si-H)鍵結。甚至，當鰭狀結構124及/或基板120的材質為矽(Si)時，埋藏部BS可能會平滑化到原子等級，及/或底面B可能會平滑化到原子等級。
在第9圖中，溝槽122的側牆S的至少一頂部US為氫基終端表面。亦即，頂部US具有至少一懸鍵與至少一氫原子鍵結。當鰭狀結構124的材質為矽(Si)時，頂部US有至少一矽氫(Si-H)鍵結。甚至，當鰭狀結構124的材質為矽(Si)時，頂部US可平滑化到原子等級的程度。
在一些實施方式中，硬式罩幕層110與阻障層115的移除可在降低介電材料150後再進行。也就是說，在頂部US上的第一墊層130、第二墊層140與介電材料150將會先被移除，然後才會移除硬式罩幕層110與阻障層115。
應當理解的是，上述所提實施方式可以透過增加額外的步驟來完成鰭式場效電晶體元件(fin type field effect transistor device,FinFET device)的製造。舉例來說，這些額外的步驟包括：形成閘極介電層、形成閘極、形成源極與汲極區域、形成接觸面、形成互連結構(例如導線、導孔、金屬層與能提供鰭式場效電晶體電路連通的介電層)、形成保護層，與封裝鰭式場效電晶體元件。
為了修復鰭狀結構124在蝕刻溝槽122時所造成的結構損傷，製造者可對鰭狀結構124進行含氫氣體退火。含氫氣體退火能夠平滑化溝槽122的底面B的側牆S。由於溝槽122的底面B與側牆S被含氫氣體退火平滑化，因此當撓曲力施加到鰭狀結構124上時，此撓曲力能被均勻分散到鰭狀結構124上，並且能夠免於裂縫的產生與成長。
雖然本揭露已以實施方式揭露如上，然其並不用以限定本揭露，任何熟習此技藝者，在不脫離本揭露的精神和範圍內，當可作各種的更動與潤飾，因此本揭露的保護範圍當視後附的申請專利範圍所界定者為準。
10~90‧‧‧步驟

Claims (10)

  1. 一種半導體結構的製造方法，包含：在一基板中形成複數個溝槽，其中該些溝槽定義出至少一鰭狀結構於其間；對該鰭狀結構進行含氫氣體退火，其中該鰭狀結構具有至少一氫基終端表面；在該些溝槽中形成一介電材料；以及降低該些溝槽中的該介電材料。
  2. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該含氫氣體退火是在含有水蒸氣、氨氣或上述之任意組合的環境下進行。
  3. 如申請專利範圍第1項所述之半導體結構的製造方法，更包含：於形成該介電材料前及對該鰭狀結構進行含氫氣體退火後，在該些溝槽的側牆及底面上形成至少一第一墊層。
  4. 一種半導體結構的製造方法，包含：在具有含氫氣體的環境下退火一基板，其中該基板具有複數個鰭狀結構以及至少一溝槽，該些鰭狀結構設置在該基板上，且該至少一溝槽將該些鰭狀結構隔開，且該鰭狀結構具有至少一氫基終端表面； 以一介電材料填滿該溝槽；以及移除該介電材料的一頂部以暴露出該些鰭狀結構的頂部。
  5. 一種半導體結構，包含：一基板，具有複數個溝槽，以定義出至少一鰭狀結構於其間，其中該鰭狀結構具有至少一氫基終端(hydrogen-terminated)表面；以及一介電材料，設置在該溝槽中，且環繞該鰭狀結構之一底部。
  6. 如申請專利範圍第5項所述之半導體結構，其中該氫基終端表面具有至少一懸鍵，且該懸鍵與至少一氫原子鍵結。
  7. 如申請專利範圍第5項所述之半導體結構，其中該氫基終端表面平滑化到原子等級程度。
  8. 如申請專利範圍第5項所述之半導體結構，其中該鰭狀結構的材質包含矽(Si)，且該氫基終端表面具有至少一矽氫(Si-H)鍵結。
  9. 如申請專利範圍第5項所述之半導體結構，其中該些溝槽中至少一者具有至少一側牆，該側牆具有一埋 設部被該介電材料所覆蓋，且該埋設部具有至少一懸鍵與至少一氫原子鍵結。
  10. 如申請專利範圍第5項所述之半導體結構，其中該些溝槽中至少一者具有一底面被該介電材料所覆蓋，且該底面有至少一懸鍵與至少一氫原子鍵結。
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