CN105895504B - 具有反锥形的介电结构及其形成方法 - Google Patents
具有反锥形的介电结构及其形成方法 Download PDFInfo
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- CN105895504B CN105895504B CN201610080704.3A CN201610080704A CN105895504B CN 105895504 B CN105895504 B CN 105895504B CN 201610080704 A CN201610080704 A CN 201610080704A CN 105895504 B CN105895504 B CN 105895504B
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
本发明涉及具有反锥形的介电结构及其形成方法。一种用于形成介电结构的方法,包括在衬底之上形成辅助层,以及在辅助层内形成孔。填充材料被沉积到孔中。去除辅助层以形成具有反锥形的介电结构。介电结构的顶部关键尺寸大于底部关键尺寸。
Description
技术领域
本发明总体上涉及半导体制造,并且在特定实施例中涉及具有反锥形(negativetaper)的介电结构及其形成方法。
背景技术
半导体器件用在各种电子和其他应用中。半导体器件包括通过在半导体晶片之上沉积一个或多个类型的材料薄膜并且对材料薄膜图案化以形成集成电路而形成在半导体晶片上的集成电路或者离散器件等。
氧化硅在很多这样的应用中用作绝缘层。例如,氧化硅频繁地用作在金属化层下方以及在有源器件区上方的前金属介电(PMD)层。
氧化硅通常通过热氧化或者通过使用化学气相沉积(CVD)工艺或等离子体增强的CVD工艺来沉积。在沉积氧化硅之后,通常对其进行蚀刻以形成图案化结构。蚀刻可以使用湿法蚀刻来执行,湿法蚀刻通常是各向同性的。所沉积的氧化物中的各向异性特征通常使用诸如反应离子蚀刻等的等离子体蚀刻来制造。
发明内容
根据本发明的实施例,一种用于形成介电结构的方法包括:在衬底之上形成辅助层,以及在辅助层内形成孔。填充材料被沉积到孔中。去除辅助层以形成具有反锥形的介电结构。介电结构的顶部关键尺寸(CD)大于底部CD。
根据本发明的实施例,一种用于形成介电结构的方法包括:在辅助层内形成孔。孔具有正锥形侧壁。掺杂氧化物被沉积到孔中并且与孔接触。去除辅助层以形成具有反锥形侧壁的结构化填充材料。
根据本发明的实施例,一种用于形成介电结构的方法包括:在衬底之上形成辅助层,以及在辅助层内形成第一孔。第一孔以第一深度部分延伸到辅助层中。在第一孔内形成第二孔。第二孔比第一孔更深地延伸到辅助层中。填充材料被沉积到第一孔和第二孔中。去除辅助层以形成具有反锥形的结构化填充材料。
附图说明
为了更完整地理解本发明及其优点,现在将参考结合附图给出的以下描述,在附图中:
图1图示根据本发明的实施例的在掺杂区形成之后并且可选地具有一个或多个金属化层的在制造期间的半导体器件的横截面视图;
图2图示根据本发明的实施例的在衬底之上形成辅助层之后衬底的横截面视图;
图3图示根据本发明的实施例的在对光致抗蚀剂材料图案化之后的在制造期间的半导体器件的横截面视图;
图4图示根据本发明的实施例的在对辅助材料图案化之后的在制造期间的半导体器件的横截面视图;
图5图示根据本发明的实施例的在去除光致抗蚀剂材料之后的在制造期间的半导体器件的横截面视图;
图6图示根据本发明的实施例的在使用填充材料填充开口之后的在制造期间的半导体器件的横截面视图;
图7图示根据本发明的实施例的在对填充材料平面化之后的在制造期间的半导体器件的横截面视图;
图8A和8B图示所制造的介电结构,其中图8A图示根据本发明的实施例的在去除辅助层之后的在制造期间的半导体器件的横截面视图,并且其中图8B图示半导体器件的对应俯视图;
图9图示根据本发明的实施例的在对具有正锥形侧壁的光致抗蚀剂层图案化之后的在制造期间的半导体器件的横截面视图;
图10图示根据本发明的实施例的在蚀刻辅助层之后的在制造期间的半导体器件的横截面视图;
图11图示根据本发明的实施例的在多阶蚀刻工艺之后去除间隔物之后的在制造期间的半导体器件的横截面视图;
图12图示根据本发明的实施例的在使用填充材料填充多阶开口之后的在制造期间的半导体器件的横截面视图;
图13图示根据本发明的实施例的在去除辅助层之后的在制造期间的半导体器件的横截面视图;
图14图示根据本发明的实施例的在可选退火工艺之后的在制造期间的半导体器件的横截面视图;
图15图示根据本发明的实施例的在抗蚀剂材料之上沉积填充材料之后的在制造期间的半导体器件的横截面视图;
图16图示根据本发明的实施例的在抛光工艺之后的在制造期间的半导体器件的横截面视图;以及
图17图示根据本发明的实施例的在去除任何剩余光致抗蚀剂层之后的在制造期间的半导体器件的横截面视图。
具体实施方式
传统的特征具有正锥形(positive taper),换言之,特征的尺寸从底部到顶部增加,其中顶部为背对支承衬底的部分。然而,对于一些应用,需要具有反锥形的介电结构。在具有反锥形的介电结构中,特征的尺寸从底部到顶部(背对支承衬底的部分)增加使得顶部关键尺寸(CD)大于底部CD。传统上没有形成具有反锥形的介电结构的方法。
本发明的实施例用于形成具有反锥形的介电特征。有利地,本发明的实施例提供一种产生这样的结构的成本有效的方式。
图1图示根据本发明的实施例的在掺杂区形成之后并且可选地具有一个或多个金属化层的在制造期间的半导体器件的横截面视图。
图1图示其上方形成有辅助层20的衬底10的横截面视图。衬底10可以是包括形成在其内的掺杂区的半导体衬底。在一些实施例中,衬底10可以包括用于将掺杂区互连的金属化层,并且提供与衬底10内的器件的外部接触。因此,衬底10可以包含沉积在其内部的有源电路装置。有源电路装置可以形成在衬底10中和/或之上,并且包括有源器件区5,有源器件区5可以包括晶体管、电阻器、电容器、电感器或其他用于形成集成电路的部件。有源区还可以包括诸如隔离区等其他结构,例如,有源区可以包括通过隔离区(例如浅沟槽隔离)彼此分离的晶体管(例如CMOS晶体管和/或双极型晶体管)。
接着,在有源器件区5之上沉积金属化(如果存在)以电接触和互连有源器件。金属化和有源器件区5一起形成完整功能的集成电路。换言之,半导体芯片的电气功能可以由互连的有源电路装置来执行。在逻辑器件中,金属化可以包括铜或其他替选材料的很多层,例如九层或更多层。在诸如DRAM等存储器器件中,金属层级的数目可以更少并且可以是铝。有源器件区5还可以形成离散器件的部分,在这种情况下,金属线的层级的数目最小。
在各种实施例中,衬底10可以形成在硅衬底上。替选地,在其他实施例中,衬底10可以形成在碳化硅(SiC)上。在一个实施例中,衬底10可以至少部分形成在氮化镓(GaN)上。例如,衬底10可以包括形成在硅上GaN上的横向晶体管。在另一实施例中,衬底10可以包括形成在体材料GaN衬底上GaN上的竖直晶体管。在替选实施例中,衬底10可以包括绝缘体上半导体衬底(诸如SOI)以及化合物半导体(诸如GaAs、InP、InSb、SbInP等)。
衬底10可以包括外延层,外延层包括异质外延或同质外延层。衬底10的一些示例为体材料单晶硅衬底(或者在其上生长的层或者在其中形成的层)、(100)硅晶片上(110)硅的层、绝缘体上硅(SOI)晶片的层、或者绝缘体上锗(GeOI)晶片的层。在其他实施例中,可以使用诸如硅锗、锗、砷化镓、砷化铟、砷化铟镓、锑化铟等的其他半导体作为衬底10。
图2图示根据本发明的实施例的在衬底之上形成辅助层之后的衬底的横截面视图。
在各种实施例中,辅助层20被配置成相对于具有形成的反锥形的图案化特征而被选择性地去除。在各种实施例中,辅助层20包括绝缘材料。例如,辅助层20包括SiO2,诸如基于原硅酸四乙酯(TEOS)或氟化的TEOS(FTEOS)的氧化物,包括掺杂的硼酸盐玻璃、有机硅酸盐玻璃(OSG)、碳掺杂的氧化物(CDO)、氟化的硅酸盐玻璃(FSG)、旋涂玻璃(SOG)或者低k绝缘材料(例如介电常数大约为4或更小)、或介电扩散阻挡层或蚀刻阻挡层,诸如氮化硅(SiN)、氮氧化硅(SiON)、碳化硅(SiC)或硅碳氮(SiCN),例如其介电常数大约为4或更高,或者其中层的组合或者多个层,作为示例,然而替选地,辅助层20可以包括其他材料。作为示例,辅助层20还可以包括密集SiCOH或者k值大约为3或更低的多孔电介质。辅助层20还可以包括例如k值大约为2.3或更低的超低k(ULK)材料。
在其他实施例中,辅助层20还可以包括无定形材料(诸如无定形碳)以及其他能够选择性地相对于衬底10被去除并且形成反锥形结构的半导体层(诸如SiGe或者锗)。
在其他实施例中,辅助层20还可以是有机材料,诸如聚合物、模制化合物、树脂等。在一个或多个实施例中,辅助层20可以包括聚合物、共聚物、生物聚合物、纤维浸入聚合物(例如树脂中的碳或玻璃纤维)、粒子填充聚合物和其他有机材料中的一种或多种。在一个或多个实施例中,辅助层20包括不是使用模制化合物形成的密封剂以及诸如环氧树脂和/或硅树脂等材料。在各种实施例中,辅助层20可以由任何适当的硬质塑料、热塑性塑料、热固性材料、层压件、环氧材料等制成。
在辅助层20之上沉积光致抗蚀剂层30。光致抗蚀剂层30包括正抗蚀剂层,在正抗蚀剂层中,通过掩膜暴露于光束的光致抗蚀剂层30的部分变为可溶解于光致抗蚀剂显影剂。在各种实施例中,光致抗蚀剂层30可以包括聚甲基丙烯酸甲脂(PMMA)、聚甲基戊二酰亚胺(PMGI)、酚醛树脂等中的一种或多种。光致抗蚀剂层30可以通过在衬底10之上的区域中沉积光致抗蚀剂材料并且接着进行旋涂来形成。
图3图示根据本发明的实施例的在对光致抗蚀剂材料图案化之后的在制造期间的半导体器件的横基面视图。
参考图3,对光致抗蚀剂层30图案化以在光致抗蚀剂层30中形成一个或多个开口31。在一个或多个实施例中,可以使用传统的光刻工艺来对光致抗蚀剂层30图案化。在正抗蚀剂的情况下,使用显影剂溶解暴露于辐射的区域以形成一个或多个开口31。备选地,在负抗蚀剂的情况下,使用显影剂溶解未暴露于辐射的区域以形成一个或多个开口31。
图4图示根据本发明的实施例的在对辅助材料图案化之后的在制造期间的半导体器件的横截面视图。
参考图4,使用光致抗蚀剂层30作为蚀刻掩膜来对辅助层20图案化以在辅助层20中形成第二开口32。第二开口32暴露在下面的衬底10。
在各种实施例中,使用等离子体蚀刻工艺来图案化辅助层20,等离子体蚀刻工艺可以是反应和离子蚀刻工艺的组合。在各种实施例中,可以在单个工艺腔室中图案化辅助层20和光致抗蚀剂层30。在一个实施例中,可以使用相同的等离子体蚀刻工艺和化学物质来图案化辅助层20和光致抗蚀剂层30。
在一个或多个实施例中,可以修改等离子体蚀刻工艺以产生具有正锥形的侧壁,即其中角度α小于90°(当角度α等于90°时,没有锥)。可以调节等离子体工艺以通过控制蚀刻工艺的各向异性来改变锥。
在各种实施例中,可以通过修改等离子体工艺中的沉积和蚀刻的速率来调节锥角度。在典型的等离子体工艺中,沉积和蚀刻两者是竞争性的工艺。沉积可以包括等离子体的离子和物种的沉积以及被去除的材料的重新沉积。例如,可以通过等离子体来氧化正在被蚀刻的衬底的材料并且将其沉积在正在形成的开口的侧壁上。取决于所沉积的材料,沉积材料可以防止或减小侧壁的蚀刻从而增加正在形成的开口32的正锥形。
在另外的实施例中,可以通过修改反应中性物种与离子物种的比率来调节角度β。反应中性物种可以增加各向同性蚀刻,而离子物种可以增加各向异性蚀刻。
在一个或多个实施例中,可以修改用于蚀刻的工艺气体以改变锥角度。用于等离子体蚀刻的工艺气体包括在等离子体蚀刻期间具有聚合物的高堆积的第一成分、以及在等离子体蚀刻期间具有聚合物的低堆积的第二成分。调节第一成分相对于第二成分的气流比率使得第一成分比第二成分多。因此,如所示,有更多的堆积产生正锥形轮廓。例如,在一个实施例中,第一成分包括CHF3,第二成分包括CF4。为了获得竖直轮廓,可以调节工艺气体使得第一成分比第二成分少。
图5图示根据本发明的实施例的在去除光致抗蚀剂材料之后的在制造过程期间的半导体器件的横截面视图。
可以使用例如湿法蚀刻来去除光致抗蚀剂层30以在辅助层30中留下第三开口33。
图6图示根据本发明的实施例的在使用填充材料填充开口之后的在制造过程期间的半导体器件的横截面视图。
在一个或多个实施例中,在第三开口33中沉积填充材料40。过沉积填充材料40以确保完全填充第三开口33并且形成过填充层45。
在各种实施例中,填充材料40包括掺杂有硼和/或磷的掺杂氧化物,诸如SiO2。在一个实施例中,可以使用化学气相沉积(CVD)工艺(诸如亚大气CVD或等离子体增强的CVD工艺)来沉积氧化硅。
在一个或多个实施例中,沉积工艺可以包括载体气体、氧化物种、硅源、硼源和磷源的使用。示例载体气体为氦气。氧化物种可以包括臭氧、氧气、N2O和NO。在各种实施例中,硅源可以是原硅酸四乙酯(TEOS)、硅烷等。
可以使用磷酸三乙酯(TEPO)、亚磷酸三乙酯(TEPi)、磷酸三甲酯(TMOP)、亚磷酸三甲酯(TMPi)和类似的化合物作为磷的源。类似地,可以使用硼酸三乙酯(TEB)、硼酸三甲酯(TMB)和类似的化合物作为硼的源。通常,呈现回流行为的掺杂氧化物具有在4到9%的范围内的磷和硼的组合总掺杂。
在沉积填充材料40(掺杂的氧化硅)之后,执行随后的加热以回流氧化物。加热软化和流动氧化物以解除固有的应力以及将氧化物的化学计量改变为更稳定的成分。可以加热衬底10以减小氧化物的粘性。在一个实施例中,可以将加热工艺执行到大约400℃,例如在400℃到600℃之间。
图7图示根据本发明的实施例的在对填充材料平面化之后的在制造期间的半导体器件的横截面视图。
如先前在图6中所图示的,在回流工艺之后,填充材料40由于填充开口而具有非均匀的顶面。特别地,在第三开口33之上的填充材料40的顶面比在辅助层20之上的填充材料40的顶面低。
参考图7,执行平面化工艺。在一个实施例中,平面化工艺可以是抛光工艺,诸如化学机械平面化(CMP)工艺。在暴露辅助层20的顶面之后停止CMP工艺。在各种实施例中,可以在CMP工艺停止之前通过CMP工艺去除辅助层20的顶部部分。因此,形成嵌入在辅助层20内的介电结构55。
在一些实施例中,如果填充材料40由于所使用的沉积工艺而具有平坦表面,则可以不需要平面化。例如,作为说明,可以使用旋涂工艺作为液体涂覆填充材料40从而形成平坦顶面。在这样的实施例中,也可以使用蚀刻工艺来去除过填充层45。
图8A图示根据本发明的实施例的在去除辅助层之后的在制造期间的半导体器件的横截面视图。图8B图示半导体器件的对应俯视图。
底部关键尺寸(CDB)小于顶部CD(CDT)以产生反锥形。去除辅助层20以留下具有反锥形的介电结构65。因此,使用本发明的实施例,形成了具有反锥形的结构。在各种实施例中,锥角度β可以在5°到30°之间。在一个或多个实施例中,锥角度β可以在10°到40°之间。在替选实施例中,锥角度β可以在15°到30°之间。
如图8B中所图示的,可以沿着长度和宽度方向在两个方向上形成反锥形。
随后的处理可以如传统的半导体处理中那样继续。
图9-10图示本发明的替选实施例,其中也可以形成具有正锥形的光致抗蚀剂层。
本实施例可以遵循图1-2中图示的工艺。
图9图示根据本发明的实施例的在图案化具有正锥形侧壁的光致抗蚀剂层之后的在制造期间的半导体器件的横截面视图。
在一个或多个实施例中,光致抗蚀剂层30的显影可以导致形成具有锥形侧壁的开口110。正锥形侧壁可以通过光刻工艺来获得,光刻工艺可以包括某个抗蚀剂回流工艺步骤。
图10图示根据本发明的实施例的在蚀刻辅助层之后的在制造期间的半导体器件的横截面视图。
如先前所描述的,使用等离子体工艺蚀刻辅助层20以形成具有锥形侧壁的第二开口120。光致抗蚀剂层30的锥形侧壁的存在可以有助于增加辅助层20的侧壁的锥角度。
在各种实施例中,可以使用包括抗蚀剂回拉的工艺序列,其具有用于辅助层20的蚀刻步骤和掩膜层30的掩膜回拉的重复序列。序列可以包括短的各向异性介电层蚀刻(产生浅的竖直轮廓)和短的各向同性抗蚀剂蚀刻(产生横向抗蚀剂回拉和不想要的抗蚀剂减薄)。重复以上序列直到完全蚀刻出轮廓并且不完全消耗抗蚀剂。在这样的工艺流程的结尾,即在层20的完全蚀刻之后,衬底10被暴露并且完全去除掩膜层30。替选地,如果提供充足的掩膜厚度,则可以在等离子体蚀刻工艺期间应用恒定的抗蚀剂回拉。在这样的工艺中,必须向在蚀刻期间用于辅助层20的蚀刻化学物质添加各向同性地侵蚀抗蚀剂的反应物。
虽然竖直抗蚀剂轮廓使得能够在介电层中制造反锥形(图3-8),然而形成辅助层20的等离子体蚀刻工艺对于竖直抗蚀剂轮廓(例如图3)而言是不同的并且是正倾斜的抗蚀剂轮廓(例如图9)。在竖直抗蚀剂轮廓的情况下,用于辅助层20的蚀刻工艺将以更高的工艺气体百分比来运行,这例如将促进在轮廓侧壁处的聚合物堆积从而在辅助层20中获得正锥形轮廓。基于CHF3/CF4的蚀刻化学物质例如需要比用于正锥形抗蚀剂的情况更高的CHF3/CF4气流比率用于竖直抗蚀剂轮廓的情况以最终以辅助层20中的正锥形轮廓结束。
随后的工艺可以遵循图5-8中图示的工艺。
图11图示根据本发明的实施例的在多阶蚀刻工艺之后去除间隔物之后的在制造期间的半导体器件的横截面视图。
本发明的实施例包括多阶开口。例如,在各种实施例中,可以重复部分蚀刻、牺牲层的沉积、形成间隔物、和进一步蚀刻穿过辅助层的多个步骤以在辅助层20中形成阶梯状开口。
作为说明,可以重复包括多个重复的短的各向异性蚀刻以及接着的各向同性蚀刻的序列直到轮廓被蚀刻。图11中图示所得到的示例结构。
替选例为在单个蚀刻步骤中使用高度聚合的蚀刻化学物质的蚀刻,例如CHF3/CF4的气流比率大于1。
图12图示根据本发明的实施例的在使用填充材料填充多阶开口之后的在制造期间的半导体器件的横截面视图。
如在图12中所示,可以向开口中沉积填充材料并且对其进行平面化,如在先前的实施例中所描述的。
图13图示根据本发明的实施例的在去除辅助层之后的在制造期间的半导体器件的横截面视图。
如图13中所图示的,去除辅助层20以留下包括反锥形的介电结构。
图14图示根据本发明的实施例的在可选退火工艺之后的在制造期间的半导体器件的横截面视图。
在各种实施例中,可以执行可选退火以平滑辅助层20的侧壁。例如,高的温度可以促进原子在尖锐角部处运动并且促进角部变圆。示例包括在氢气气氛中退火以增加硅原子的迁移率。可以在快速热退火设备或其他熔炉中例如在300℃到500℃之间进行可选退火。
图15-17图示半导体器件的制造的替选方法,其中沉积填充材料而没有去除抗蚀剂材料。
本实施例可以遵循以上例如在图1-4中描述的工艺。然而,没有像图5那样蚀刻光致抗蚀剂层30。
图15图示根据本发明的实施例的在沉积填充材料之后的在制造期间的半导体器件的横截面视图。
如图15中所图示的,在一个或多个实施例中,可以直接地在光致抗蚀剂层30之上沉积填充材料40。
图16图示根据本发明的实施例的在抛光工艺之后的在制造期间的半导体器件的横截面视图。
可以如先前的实施例中那样执行抛光或平面化。在一个或多个实施例中,平面化工艺可以去除下面的抗蚀剂层30。替选地,如图16中所图示的,可以在CMP工艺完成之后保留抗蚀剂层30的部分。
图17图示根据本发明的实施例的在去除任何残余光致抗蚀剂层之后的在制造期间的半导体器件的横截面视图。
可以如图16所示去除任何残余光致抗蚀剂层30。然后可以如先前实施例中所描述地去除暴露的辅助层20。例如,随后的处理可以如图8中图示地继续。
虽然已经参考说明性实施例描述了本发明,然而本描述并非意在要在限制意义上来理解。本领域技术人员在参考描述时将很清楚说明性实施例的各种修改和组合以及本发明的其他实施例。因此,意图在于,所附权利要求包括任何这样的修改或实施例。
Claims (18)
1.一种用于形成介电结构的方法,所述方法包括:
在衬底之上形成辅助层;
使用等离子体蚀刻在所述辅助层内形成通孔,其中在所述等离子体蚀刻期间的工艺气体包括在所述等离子体蚀刻期间具有聚合物的高堆积的第一成分、以及在所述等离子体蚀刻期间具有聚合物的低堆积的第二成分,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分比所述第二成分多;
将填充材料沉积到所述通孔中;以及
去除所述辅助层以形成具有反锥形的所述介电结构,所述介电结构的顶部关键尺寸(CD)大于底部CD。
2.根据权利要求1所述的方法,其中被沉积到所述通孔中的所述填充材料包括掺杂氧化物。
3.根据权利要求1所述的方法,其中所述等离子体蚀刻包括用于产生正锥形的工艺参数。
4.根据权利要求3所述的方法,其中所述第一成分包括CHF3并且所述第二成分包括CF4。
5.根据权利要求1所述的方法,其中在所述辅助层内形成所述通孔包括:
在所述辅助层之上形成光致抗蚀剂层;
显影所述光致抗蚀剂层以形成开口;以及
使用所述光致抗蚀剂层作为蚀刻掩膜来蚀刻所述辅助层。
6.根据权利要求5所述的方法,其中所述开口包括具有正锥形的侧壁。
7.根据权利要求5所述的方法,其中所述开口包括没有锥的侧壁。
8.根据权利要求5所述的方法,还包括在向所述通孔中沉积所述填充材料之前去除所述光致抗蚀剂层。
9.根据权利要求5所述的方法,还包括:在所述光致抗蚀剂层之上沉积所述填充材料,以及在将所述填充材料沉积到所述通孔中之后去除所述光致抗蚀剂层。
10.一种用于形成介电结构的方法,所述方法包括:
在衬底之上形成辅助层;
使用等离子体蚀刻在所述辅助层内形成通孔,其中在所述蚀刻期间的工艺气体包括在所述蚀刻期间具有聚合物的高堆积的第一成分、以及在所述蚀刻期间具有聚合物的低堆积的第二成分,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分比所述第二成分少;
将填充材料沉积到所述通孔中;以及
去除所述辅助层以形成具有反锥形的所述介电结构,所述介电结构的顶部关键尺寸(CD)大于底部CD。
11.一种用于形成介电结构的方法,所述方法包括:
使用等离子体蚀刻在辅助层内形成通孔,所述通孔具有正锥形侧壁,其中在所述等离子体蚀刻期间的工艺气体包括在所述等离子体蚀刻期间具有聚合物的高堆积的第一成分、以及在所述等离子体蚀刻期间具有聚合物的低堆积的第二成分,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分比所述第二成分多;
将掺杂氧化物沉积到所述通孔中并且使其与所述通孔接触;以及
去除所述辅助层以形成具有反锥形侧壁的结构化填充材料。
12.一种用于形成介电结构的方法,所述方法包括:
在衬底之上形成辅助层;
使用等离子体蚀刻在所述辅助层内形成第一孔,所述第一孔以第一深度部分延伸到所述辅助层中;
在所述第一孔内形成第二孔,所述第二孔比所述第一孔更深地延伸到所述辅助层中,其中在所述等离子体蚀刻期间的工艺气体包括在所述等离子体蚀刻期间具有聚合物的高堆积的第一成分、以及在所述等离子体蚀刻期间具有聚合物的低堆积的第二成分,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分与所述第二成分具有不同的量;
将填充材料沉积到所述第一孔和所述第二孔中;以及
去除所述辅助层以在所述衬底上形成结构化填充材料,所述结构化填充材料具有反锥形。
13.根据权利要求12所述的方法,其中所述结构化填充材料的顶部关键尺寸(CD)大于底部CD。
14.根据权利要求12所述的方法,还包括:
在所述第二孔内形成第三孔,所述第三孔比所述第二孔更深地延伸到所述辅助层中,其中将所述填充材料沉积到所述第一孔和所述第二孔中包括将所述填充材料沉积到所述第三孔中。
15.根据权利要求12所述的方法,其中形成所述辅助层包括形成包括具有正锥形的侧壁的开口。
16.根据权利要求15所述的方法,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分比所述第二成分多。
17.根据权利要求12所述的方法,其中形成所述辅助层包括形成包括没有锥的侧壁的开口。
18.根据权利要求17所述的方法,其中所述第一成分相对于所述第二成分的气流比率使得所述第一成分比所述第二成分少。
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