TWI527124B - 用於場效電晶體裝置之自動對準接點 - Google Patents

用於場效電晶體裝置之自動對準接點 Download PDF

Info

Publication number
TWI527124B
TWI527124B TW100112069A TW100112069A TWI527124B TW I527124 B TWI527124 B TW I527124B TW 100112069 A TW100112069 A TW 100112069A TW 100112069 A TW100112069 A TW 100112069A TW I527124 B TWI527124 B TW I527124B
Authority
TW
Taiwan
Prior art keywords
contact portion
gate stack
layer
conductive contact
deposited
Prior art date
Application number
TW100112069A
Other languages
English (en)
Other versions
TW201203384A (en
Inventor
郭德超
海安屈威弗列德Ｅ
王辛惠
黃愷洸漢
Original Assignee
萬國商業機器公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 萬國商業機器公司 filed Critical 萬國商業機器公司
Publication of TW201203384A publication Critical patent/TW201203384A/zh
Application granted granted Critical
Publication of TWI527124B publication Critical patent/TWI527124B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Composite Materials (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

用於場效電晶體裝置之自動對準接點
本發明涉及半導體場效電晶體。
半導體場效電晶體(FETs)包含源極、汲極及閘極，其常常電性地接觸至金屬接點。如果在製造程序中金屬接點錯位，金屬接點之製造可能導致接點間之短路。
在本發明之一第一態樣中，形成一場效電晶體之方法包含：在一基板上形成一閘極堆疊、在該基板上鄰接於該閘極堆疊之相對側面處，形成一間隙物、在該基板上鄰接該閘極堆疊之一第一面上之該間隙物處，形成一矽化物源極、在該基板上鄰接該閘極堆疊之一第二面之該間隙物處，形成一矽化物汲極、在該暴露之矽化物源極區域及該暴露之矽化物汲極區域上，磊晶成長矽、在該閘極堆疊之一硬遮罩層和該間隙物上，形成一襯墊層、移除該襯墊層之一部分，以暴露該硬遮罩層之一部分、移除該硬遮罩層之該等暴露部分，以暴露該閘極堆疊之一矽層、移除暴露之矽，以暴露該閘極堆疊之一金屬層之一部份、該矽化物源極區域及該矽化物汲極區域，以及在該閘極堆疊之該暴露金屬、該暴露之矽化物源極區域及該暴露之矽化物汲極區域層之上沉積一導電材料。
在本發明之另一態樣中，一場效電晶體裝置包含：沉積在一基板上之閘極堆疊、沉積在該閘極堆疊之第一末端上之第一接點部分，沉積在該閘極堆疊之第二末端之上之第二接點部分，該第一接點部分沉積在離該第二接點部分之距離d處，而寬度為w之一第三接點部分沉積在該設備之一源極區域中，該距離d大於該寬度w。
本發明之該等技術實現額外之諸特徵以及諸優點。本發明之其他諸實施例以及諸態樣將在此細述，並視為本所請發明之一部分。為了更加了解本發明之該諸優點及該諸特徵，可參照該描述及該諸圖示。
第1A圖和第1B圖分別以剖視圖和上視圖圖示形成場效電晶體之方法。第1A圖圖示多個沉積在矽基板102上之閘極堆疊100，該基板可包含矽部分及絕緣層上矽晶(silicon-on-insulator;SOI)溝槽部分501(如下述之第5A圖所示)。閘極堆疊100順著縱軸x平行排列(如圖1B所示)。閘極堆疊100包含介電層104(諸如沉積在基板102上之高介電值材料)。金屬層106(諸如沉積在介電層104上之氮化鉭)。沉積在金屬層106上之矽層108及硬遮罩層110(諸如沉基在矽層108上之氮化矽材料)。間隙物112在基板102上沿著閘極堆疊100之側邊形成。間隙物112可由如氮化物形成，並可包含任何層數及層中之任何材料組合。在所圖示之實施例中，間隙物112包含兩層間隙金屬。源極區域(S)和汲極區域(D)係形成在基板102上鄰接間隙物112處。源極區域和汲極區域包含矽化物114(諸如在源極區域和汲極區域上形成之二矽化鎢或二矽化鎳)。
第2A圖和第2B圖圖示後續在源極區域和汲極區域之暴露之矽化物114上，矽磊晶成長之所得構造。磊晶成長產生由矽化物114所延伸之暴露矽區域202。
第3A圖和第3B圖圖示後續在閘極堆疊100、矽區域202及間隙物112上，沉積襯墊層302之所得構造。襯墊層302可包含如氧化層者。
第4A圖和第4B圖圖示後續將襯墊層302之一部分移除，以暴露矽區域202之部分後的所得構造。襯墊層302之該部分可藉由(諸如化學機械拋光(chemical mechanical polishing;CMP)或其他合適之機械或化學程序所移除)。
第5A圖和第5B圖圖示後續將襯墊層302之多部分移除，以暴露硬遮罩層110之部分後的所得構造。移除襯墊層302之一部分，形成由硬遮罩層110及襯墊層302所定義之之空腔502。
第6A圖和第6B圖圖示後續將硬遮罩層110之暴露部分移除，而暴露矽層108之部分後的所得構造。硬遮罩層110之暴露部分可藉由蝕刻程序(諸如反應性離子蝕刻(reactive ion etching;RIE)或其他用以蝕刻硬遮罩層110材料之合適蝕刻程序)所移除。
第7A圖、第7B圖和第7C圖圖示後續將(圖6A之)矽層(圖6B之)108之暴露部分和矽區域202移除之所得構造。暴露之矽可藉由(諸如用以移除矽之RIE程序或任何其他合適之)蝕刻程序所移除。矽層108之多個暴露部分之移除，暴露金屬層106之部分，且增加空腔502之深度，使空腔502由襯墊層302、間隙物112及金屬層106所定義。而矽區域202之移除，暴露矽化物114源極區域和汲極區域，並在襯墊層302中形成空腔702。空腔702係由襯墊層302及矽化物114所定義。
第8A圖、第8B圖和第8C圖圖示後續在(第7A圖和第7C圖之)空腔502及空腔702內形成導電接點802及802a之所得構造。導電接點802及802a可藉由在空腔502及空腔702內並在暴露之襯墊層302上，沉積一層金屬材料(諸如銀、金或鋁)所形成。拋光程序(諸如CMP或其他合適程序)可用來由襯墊層302移除金屬材料，且在其他實施例中，可用來自襯墊層302之一部分移除金屬材料，以定義接點802及802a。接點802及802a和裝置之源極、汲極及閘極(G)區域電性地接觸。
參閱第8B圖，源極及汲極區域接點802沿著如線8C所示之橫軸排列，線8C係與(第1B圖之)閘極堆疊100縱軸x相垂直，且和閘極堆疊100之中間相交。閘極區域接點802g沿如直線8A及直線y所示之平行軸排列，該等直線和平行閘極堆疊100之縱軸x相垂直。閘極區域接點802g在閘極堆疊之末端以距離d相隔。源極及汲極區域接點802之寬度為w。在所圖示之實施例中，該距離d大於該寬度w。閘極區域接點802g距離源極由汲極區域接點802之偏移量，減少製造程序中接點802及802g間短路之發生。
本文之用語僅用來描述特定實施例，而並非意欲限制本發明。本文所使用單數形「一」及「該」亦意欲包含複數形，除非上下文有清楚地指出。應理解，在此說明書中所使用之術語「包含」及/或「包括」指明所具有之特徵、整體、步驟、操作、要素及/或元件，但非排除一或多個其他特徵、整體、步驟、操作、要素元件及/或其群體之呈現或添加。
以下請求項中之所有手段或步驟功能用語元件之相應結構、材料、動作、及均等物，意欲包含任何用於執行該功能之相應結構、材料、動作與其他特定所請求元件之組合。本發明所揭示內容之目的係在於圖示及描述，並非意欲為詳盡徹底之揭示或將本發明侷限於所揭示之形式。許多不偏離本發明之範疇及精神之修改及變化對於熟習此項技藝者乃顯而易見。所選擇描述之實施例係為能最佳地解釋發明原理及實際應用者，且為使其他熟習此項技藝者能理解本發明具有適於所預期之特殊用途之各式變化之各式實施例。
本文描繪之流程圖僅為一示例。本文描述之流程圖或步驟(或操作)可有許多不偏離該發明之範疇及精神之變化。例如，可依不同順序執行步驟，或可增加、刪除或修改步驟。所有此等變化皆視為該所請發明之一部分。
儘管本案已描述該發明之較佳實施例，應理解熟習此項技藝者可在現在及未來進行各式落在以下請求項之範疇中之改進及增強。此等請求項應被詮釋成，得以為被首次描述之發明維持適當的保護。
100．．．閘極堆疊
102．．．矽基板/基板
104．．．介電層
106．．．金屬層
108．．．矽層
110．．．硬遮罩層
112．．．間隙物
114．．．矽化物
202．．．矽區域
302．．．襯墊層
501．．．絕緣層上矽晶溝槽部分
502．．．空腔
702．．．空腔
802．．．導電接點
802g．．．導電接點
在本說明書最後之諸請求項中，特別指出並明確地請求被視為本發明之標的。根據以上結合附圖之詳細描述，本案之前述與其他諸特徵和諸優點將更加顯而易見，其中：
第1A圖至第8C圖圖示形成一場效電晶體裝置之一方法和一所得構造。
100．．．閘極堆疊
102．．．矽基板/基板
104．．．介電層
106．．．金屬層
108．．．矽層
110．．．硬遮罩層
112．．．間隙物
114．．．矽化物
D．．．汲極區域
S．．．源極區域

Claims (6)

  1. 一種場效電晶體裝置，該裝置包含：沉積在一基板上之一閘極堆疊，該閘極堆疊具有一縱軸平行於該基板的一頂表面；沉積在該閘極堆疊的一頂表面之一第一末端處之一第一導電接點部分；沉積在該閘極堆疊的該頂表面之一第二末端處之一第二導電接點部分，該第一導電接部分沉積在沿著該縱軸離該第二導電接點部分之一距離d處；以及沉積在鄰近該閘極堆疊的一第一側之一源極區域上、寬度為w之一第三導電接點部分，該第三導電接點部分的該寬度w係由沿著平行於該縱軸的一方向所定義，其中該距離d大於該第三導電接點部分的該寬度w，致使該第一和該第二導電接點部分相隔離且沿著平行於該縱軸的該方向偏離該第三導電接點部分的相對端。
  2. 如請求項1所述之裝置，其中該第一導電接點部分及該第二導電接點部分與該閘極堆疊之一金屬層接觸。
  3. 如請求項1所述之裝置，其中該裝置包含沉積在該裝置之一汲極區域中、寬度為w的一第四導電接點部 分。
  4. 如請求項1所述之裝置，其中該源極區域包含一矽化物材料。
  5. 如請求項1所述之裝置，其中該第三導電接點部分係沿一橫軸排列，該橫軸對準該閘極堆疊之一中間橫截軸。
  6. 如請求項1所述之裝置，其中該閘極堆疊包含：沉積該在基板上之一介電層、沉積該在介電層上之一金屬層、沉積在該金屬層上之該矽層，以及沉積在該矽層上之一硬遮罩層。
TW100112069A 2010-04-09 2011-04-07 用於場效電晶體裝置之自動對準接點 TWI527124B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/757,201 US8367508B2 (en) 2010-04-09 2010-04-09 Self-aligned contacts for field effect transistor devices

Publications (2)

Publication Number Publication Date
TW201203384A TW201203384A (en) 2012-01-16
TWI527124B true TWI527124B (zh) 2016-03-21

Family

ID=44760300

Family Applications (2)

Application Number Title Priority Date Filing Date
TW100112069A TWI527124B (zh) 2010-04-09 2011-04-07 用於場效電晶體裝置之自動對準接點
TW104127119A TWI538064B (zh) 2010-04-09 2011-04-07 用於場效電晶體裝置之自動對準接點

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW104127119A TWI538064B (zh) 2010-04-09 2011-04-07 用於場效電晶體裝置之自動對準接點

Country Status (7)

Country Link
US (2) US8367508B2 (zh)
JP (1) JP5764198B2 (zh)
CN (1) CN102822976B (zh)
DE (1) DE112011100421B4 (zh)
GB (1) GB2492514C (zh)
TW (2) TWI527124B (zh)
WO (1) WO2011126682A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8664077B2 (en) * 2012-02-14 2014-03-04 Nanya Technology Corp. Method for forming self-aligned overlay mark
US8901627B2 (en) 2012-11-16 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Jog design in integrated circuits
US9324709B2 (en) * 2013-08-19 2016-04-26 Globalfoundries Inc. Self-aligned gate contact structure
US9337284B2 (en) * 2014-04-07 2016-05-10 Alpha And Omega Semiconductor Incorporated Closed cell lateral MOSFET using silicide source and body regions
CN108987261B (zh) * 2017-06-01 2022-05-17 联华电子股份有限公司 半导体结构及其制造方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133664A (ja) * 1984-12-03 1986-06-20 Nec Corp 半導体集積回路
JPH0513017Y2 (zh) * 1985-10-04 1993-04-06
WO1997014185A1 (en) 1995-10-11 1997-04-17 Paradigm Technology, Inc. Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts
JPH1079505A (ja) * 1996-09-05 1998-03-24 Hitachi Ltd 半導体集積回路装置の製造方法
US6207543B1 (en) 1997-06-30 2001-03-27 Vlsi Technology, Inc. Metallization technique for gate electrodes and local interconnects
JPH11177089A (ja) * 1997-12-16 1999-07-02 Hitachi Ltd 半導体装置の製造方法
US20020031909A1 (en) 2000-05-11 2002-03-14 Cyril Cabral Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
US6503833B1 (en) 2000-11-15 2003-01-07 International Business Machines Corporation Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby
JP3669919B2 (ja) * 2000-12-04 2005-07-13 シャープ株式会社 半導体装置の製造方法
US6403485B1 (en) 2001-05-02 2002-06-11 Chartered Semiconductor Manufacturing Ltd Method to form a low parasitic capacitance pseudo-SOI CMOS device
US6518151B1 (en) 2001-08-07 2003-02-11 International Business Machines Corporation Dual layer hard mask for eDRAM gate etch process
US6627502B1 (en) * 2002-10-24 2003-09-30 Taiwan Semiconductor Manufacturing Company Method for forming high concentration shallow junctions for short channel MOSFETs
JP2004152790A (ja) * 2002-10-28 2004-05-27 Toshiba Corp 半導体装置、及び、半導体装置の製造方法
US6800530B2 (en) 2003-01-14 2004-10-05 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
DE10345374B4 (de) * 2003-09-30 2006-08-10 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauteil mit einem Nickel/Kobaltsilizidgebiet, das in einem Siliziumgebiet gebildet ist und Verfahren zu seiner Herstellung
US7098114B1 (en) 2004-06-22 2006-08-29 Integrated Device Technology, Inc. Method for forming cmos device with self-aligned contacts and region formed using salicide process
TW200620478A (en) 2004-08-20 2006-06-16 Koninkl Philips Electronics Nv Self-aligned epitaxially grown bipolar transistor
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
KR100629356B1 (ko) * 2004-12-23 2006-09-29 삼성전자주식회사 필라 패턴을 갖는 플래시메모리소자 및 그 제조방법
US7470943B2 (en) 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US20070178634A1 (en) * 2006-01-31 2007-08-02 Hyung Suk Jung Cmos semiconductor devices having dual work function metal gate stacks
US7615831B2 (en) 2007-10-26 2009-11-10 International Business Machines Corporation Structure and method for fabricating self-aligned metal contacts
US8159038B2 (en) 2008-02-29 2012-04-17 Infineon Technologies Ag Self aligned silicided contacts
JP2009302320A (ja) * 2008-06-13 2009-12-24 Renesas Technology Corp 半導体装置およびその製造方法
US20100038715A1 (en) 2008-08-18 2010-02-18 International Business Machines Corporation Thin body silicon-on-insulator transistor with borderless self-aligned contacts
US8062975B2 (en) * 2009-04-16 2011-11-22 Freescale Semiconductor, Inc. Through substrate vias
JP2011146465A (ja) * 2010-01-13 2011-07-28 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
US8673725B2 (en) * 2010-03-31 2014-03-18 Tokyo Electron Limited Multilayer sidewall spacer for seam protection of a patterned structure

Also Published As

Publication number Publication date
GB201219007D0 (en) 2012-12-05
TW201203384A (en) 2012-01-16
GB2492514A (en) 2013-01-02
US8367508B2 (en) 2013-02-05
CN102822976A (zh) 2012-12-12
JP5764198B2 (ja) 2015-08-12
GB2492514B (en) 2014-06-11
TWI538064B (zh) 2016-06-11
DE112011100421B4 (de) 2013-09-05
CN102822976B (zh) 2016-09-07
JP2013524529A (ja) 2013-06-17
US20110248321A1 (en) 2011-10-13
GB2492514C (en) 2014-06-18
DE112011100421T5 (de) 2012-11-22
US20120280322A1 (en) 2012-11-08
TW201545241A (zh) 2015-12-01
WO2011126682A1 (en) 2011-10-13
US8901626B2 (en) 2014-12-02

Similar Documents

Publication Publication Date Title
US11682697B2 (en) Fin recess last process for FinFET fabrication
US8679902B1 (en) Stacked nanowire field effect transistor
TWI485848B (zh) 半導體裝置及其製造方法
JP5017795B2 (ja) 電界効果トランジスタの製造方法
CN107039435B (zh) 鳍式场效应晶体管结构及其制造方法
TWI661561B (zh) 用於非平面電晶體之源極／汲極接點（三）
US20120193712A1 (en) FinFET STRUCTURE HAVING FULLY SILICIDED FIN
US7781274B2 (en) Multi-gate field effect transistor and method for manufacturing the same
JP2013069885A (ja) 半導体装置およびその製造方法
JP2006522486A5 (zh)
CN107346782B (zh) 鳍型场效应晶体管及其制造方法
WO2011079595A1 (zh) 鳍式晶体管结构及其制作方法
US20060006466A1 (en) Semiconductor device and method of manufacturing the same
WO2011097782A1 (zh) 鳍式晶体管结构及其制作方法
TWI527124B (zh) 用於場效電晶體裝置之自動對準接點
WO2012100463A1 (zh) 一种形成半导体结构的方法
KR20200050424A (ko) 반도체 디바이스 및 방법
CN108695382B (zh) 半导体装置及其制造方法
JP4193097B2 (ja) 半導体装置およびその製造方法
US8928091B2 (en) Field-effect-transistor with self-aligned diffusion contact
US9299825B2 (en) Semiconductor device with surrounding gate transistor
WO2014071664A1 (zh) FinFET及其制造方法
JP5286416B2 (ja) 半導体装置およびその製造方法
JP2011066362A (ja) 半導体装置
TWI670770B (zh) 用於形成自對準接觸物的擴大犧牲閘極覆蓋物

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees