TWI520342B - 半導體結構與鰭式場效電晶體的製造方法 - Google Patents

半導體結構與鰭式場效電晶體的製造方法 Download PDF

Info

Publication number
TWI520342B
TWI520342B TW103100916A TW103100916A TWI520342B TW I520342 B TWI520342 B TW I520342B TW 103100916 A TW103100916 A TW 103100916A TW 103100916 A TW103100916 A TW 103100916A TW I520342 B TWI520342 B TW I520342B
Authority
TW
Taiwan
Prior art keywords
semiconductor material
semiconductor
active region
fin active
elements
Prior art date
Application number
TW103100916A
Other languages
English (en)
Other versions
TW201434156A (zh
Inventor
戴爾 馬克 凡
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201434156A publication Critical patent/TW201434156A/zh
Application granted granted Critical
Publication of TWI520342B publication Critical patent/TWI520342B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2011—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline insulating material, e.g. sapphire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

半導體結構與鰭式場效電晶體的製造方法
本發明係有關於半導體裝置的製造方法。
鍺(germanium,Ge)本身在IV與III-V族半導體中具有最高的電洞移動率(hole mobility)，且其具有高於矽(Si)兩倍的電子遷移率(electron mobility)，因此，鍺被視為能在未來取代矽而作為互補式金氧半(CMOS)場效電晶體節點(node)之p通道的材料。可預期的是，高遷移率通道將與Si基週邊整合一起，例如，輸入/輸出(I/O)、靜電放電(electrostatic discharges,ESD)。因此，整合Ge通道於Si晶圓上係必須的。
因為Ge與Si之間存在有很大的晶格失配(lattice mismatch)，不易在Si上生長低缺陷(low-defective)的Ge磊晶。尤其可能會在磊晶成長期間產生各種缺陷。舉例來說，在磊晶成長的Ge層中形成穿透錯位(threading dislocation)缺陷。目前使用各種方法以降低異-磊晶(hetero-epitaxy)相關的缺陷，例如，穿透錯位缺陷、堆積缺陷(stacking faults)、或點缺陷(point defects)等。然而，已知的方法仍有許多顧慮以及伴隨著裝置品質與可靠度的缺點。舉例來說，在已知的方法中，穿透錯位缺陷雖已被抑制，然而，並未被消除。因為這些缺陷可被電性活化，所形成的電晶體可能仍會遭受到較高的接面漏電流 (junction leakage)。
因此，亟需一種結構與方法以解決上述問題，以提高效能並降低接合洩漏。
本發明一實施例提供一種半導體結構，包括：一半導體基底，其具有一第一半導體材料；多個淺溝隔離(shallow trench isolation,STI)元件，形成於半導體基底中；以及一鰭型主動區，磊晶生長於半導體基底上，鰭型主動區具有一第二半導體材料；其中第一半導體材料具有一第一晶格常數，而第二半導體材料具有不同於第一晶格常數的第二晶格常數，且鰭型主動區更包括一氟劑。
本發明另一實施例提供一種半導體結構，包括：多個STI元件，形成一矽基底中，用以定義出矽基底中兩個相鄰STI元件之間的矽區域；一主動區，其具有磊晶生長於矽區域上且從相鄰的STI元件凸出的一半導體材料；其中矽基底具有一第一晶格常數，而半導體材料具有一第二晶格常數，且主動區更包括一非活性摻雜劑。
本發明又一實施例提供一種鰭式場效電晶體(FinFET)的製造方法，包括：形成多個STI元件於具有一第一半導體材料的一半導體基底中，進而定義出藉由STI元件而分隔的多個半導體元件；凹蝕半導體元件；磊晶生長一第二半導體材料於被凹蝕的半導體元件上，以形成具有半導體材料的多個鰭式主動區，其中第二半導體材料與第一半導體材料具有一晶格失配(lattice mismatch)，晶格失配產生多個穿透錯位缺陷 於鰭式主動區中；以及對鰭式主動區進行一氟佈植製程，以將形成於鰭式主動區中的穿透錯位缺陷去活化。
100、250‧‧‧半導體結構
110‧‧‧半導體基底
112‧‧‧隔離元件
114‧‧‧半導體區域
W‧‧‧寬度
Hs、H‧‧‧高度
116‧‧‧凹口
118‧‧‧頂表面
120‧‧‧第二半導體材料
122‧‧‧鰭主動區
124‧‧‧離子佈植製程
222、262‧‧‧缺陷
252‧‧‧閘極
254‧‧‧閘疊
256‧‧‧閘間隔物
258‧‧‧輕度摻雜汲極元件
260‧‧‧重度摻雜汲極元件
264‧‧‧區域
第1~6圖為根據一或多個實施例繪示出半導體結構在不同的製作階段之剖面示意圖。
第7圖為根據一實施例而繪示出第6圖的半導體結構之製造方法的流程圖。
第8圖為根據一實施例而繪示出第6圖磊晶生長的半導體材料之示意圖。
第9圖為根據一實施例繪示出部份具有鰭型結構之半導體結構的上視圖。
第10圖為根據一實施例而繪示出第9圖之半導體結構的截面圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。再者，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特 徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。
第1~6圖為根據一或多個實施例繪示出半導體結構100在不同的製作階段之剖面示意圖。一實施例中，半導體結構100包括一或多個場效電晶體(field effect transistor,FET)。第7圖為根據一或多個實施例繪示出半導體結構100的製造方法200之流程圖。以下將同時搭配第1~7圖而敘述半導體結構100與方法200。
請參照第1圖，半導體結構100包括第一半導體材料所形成的半導體基底110。在此實施例中，第一半導體材料為矽。此外，第一半導體材料可包括其他適合的半導體材料，一實施例中，半導體基底110包括由合適技術所形成的埋入介電材料層，用以提供隔離(isolation)，形成埋入介電材料層的合適技術可例如，被稱為氧離子佈植隔離(separation by implanted oxygen)的技術。一些實施例中，基底110可為半導體覆絕緣體，例如，矽覆絕緣體(silicon on insulator,SOI)。
請參照第1圖與第7圖，方法200藉由在半導體基底110中形成多個隔離元件112而從步驟202開始。在此實施例中，隔離元件112為淺溝隔離(shallow trench isolation,STI)元件。
STI元件112形成於半導體基底110中並定義出各個半導體區域114。半導體區域114藉由STI元件112而彼此分開並隔離。此外，在此步驟中，半導體基底110的頂表面與 STI元件112的頂表面為共平面。一些實施例中，STI元件112的形成包括，形成具有多個開口的硬遮罩，開口定義出STI元件的區域；透過開口而蝕刻半導體基底110以行程多個溝槽(trench)；沉積介電材料以填入溝槽；以及進行化學機械研磨(chemical mechanical polishing,CMP)製程。一實施例中，STI元件112的深度範圍為約30~250nm。
在一實施例中，STI元件112的形成進一步包括在CMP之後移除硬遮罩。在另一實施例中，硬遮罩包括由熱氧化(thermal oxidation)形成的氧化矽層、以及在氧化矽層上藉由化學氣相沉積(chemical vapor deposition,CVD)形成的氮化矽層。在又一實施例中，在CMP製程後移除硬遮罩。
在另一實施例中，介電材料的沉積包括對溝槽進行熱氧化、以及以介電材料填入溝槽(例如，由CVD填入氧化矽)。在一例子中，用以填充溝槽的CVD製程包括高密度電漿CVD(high density plasma CVD,HDPCVD)。
特別的是，半導體區域114被設計為可在隨後的磊晶成長期間達到高寬比捕獲(aspect ratio trapping,ART)的尺寸。ART技術與半導體區域114的尺寸將在之後的製造階段作進一步的詳述。在此例子中，STI元件112之高度“Hs”為約100~300nm。在另一例子中，每一半導體區域114之寬度“W”為約5~50nm。半導體區域114的寬度W為跨越兩個相鄰的STI元件112的尺寸。
可在半導體基底110上形成其他元件。在一例子中，在半導體基底中的半導體區域114之範圍內，藉由一或多 到佈植製程或其他合適的摻雜技術而形成不同的摻雜區域(例如，n井與p井)。
請參照第2圖與第7圖，方法200之步驟204藉由選擇性地(selectively)凹蝕半導體基底110相對於STI元件112的第一半導體材料，因而在STI元件112中產生多個凹口116。在此實施例中，凹蝕步驟包括以蝕刻移除位於STI元件112之間的半導體區域114之頂部部份。凹蝕半導體區域114的蝕刻包括乾蝕刻、溼蝕刻、或其他合適的蝕刻技術。在一例子中，凹蝕半導體區域114的蝕刻包括氣態鹽酸(氣態HCl)。
被凹蝕的半導體區域114之頂表面118大抵上低於STI元件112的表面。在一例子中，被凹蝕的半導體區域114之頂表面118大抵上低於STI元件112的頂表面且高於STI元件112的底表面。在此例子中，凹蝕的深度為約100~300nm。
如第2圖所示，每一凹口116的尺寸包括寬度W與高度H。凹口116的高寬比係定義為H/W。在此實施例中，為了達到高寬比捕獲，凹口經設計以使其高寬比H/W大於1.4。
請參照第3圖與第7圖，方法200之步驟206藉由磊晶成長製程而在凹蝕的半導體區域114上形成第二半導體材料120。第二半導體材料的成份不同於第一半導體材料。因此，磊晶成長製程為異磊晶(hetero epitaxy)成長製程。特別的是，第一半導體材料具有第一晶格常數(lattice constant)而第二半導體材料具有不同於第一晶格常數的第二晶格常數。因此，第一與第二半導體材料之間存在有失配(mismatch)。在一例子中，失配為4%或更大。晶格常數的失配導致缺陷產生於第二 半導體材料120中。在此情況下，缺陷包括穿透錯位缺陷與點缺陷，這些缺陷係位於第一與第二半導體材料之間的界面，且這些缺陷會向上延伸。
在一實施例中，第二半導體材料不同於第一半導體材料，且第二半導體材料帶有晶格常數失配以產生應變效應(strained effect)與增強遷移率(mobility)。在其他實施例中，為了整合III-V族化合物半導體的主動區域於矽基底，進而產生較佳的效能(高速或高頻率)，係使用成熟的矽製造技術，且第一半導體材料包括矽，而第二半導體材料包括III-V族化合物半導體。
在一實施例中，半導體基底110包括矽，而第二半導體材料120包括鍺(Ge)或鍺化矽(例如，Si50Ge50)。
在另一實施例中，在用於p型FET的半導體區域中磊晶成長出的第二半導體材料120包括鍺化矽、碳鍺化矽、鍺、矽、或前述之組合等半導體材料。在另一實施例中，在用於n型FET的半導體區域中磊晶成長出的第二半導體材料120包括磷化矽、碳化矽、矽、或前述之組合等半導體材料。
在又一實施例中，用於p型FET的第二半導體材料120與用於n型FET的第二半導體材料120兩者皆存在，係藉由不同且分開的磊晶成長製程並使用相對應的半導體材料。以一例子來說，在第一組半導體區域114中的第二半導體材料120係用於p型FET，而在第二組半導體區域114中的第二半導體材料120係用於n型FET。
在又一實施例中，第二半導體材料120包括III-V 族化合物半導體材料，例如，磷化銦(InP)、砷化銦鎵(Indium Gallium Arsenide,InGaAs)、砷化銦。為了促進本實施例，n型FET的通道區係形成於第二半導體材料中。
磊晶成長製程選擇性地在半導體區域114中的第一半導體材料上生長晶質的第二半導體材料。第二半導體材料120填充於凹口116。為了確保凹口116完全地填滿，第二半導體材料過量地成長至一大範圍，這使得過量的第二半導體材料形成於STI元件112上方。在一例子中，位於STI元件112上方過量部份的第二半導體材料之厚度為約100~1000nm。在另一例子中，過量部份之厚度為約500nm。
因凹口116具有特定的高寬比H/W(在此實施例中，高寬比為大於1.4)，藉由STI元件112的側壁將穿透錯位捕獲(trap)於第二半導體材料120的底部部份，而使第二半導體材料120之頂部部份無缺陷。因此，這種技術稱為高寬比捕獲(aspect ratio trapping,ART)。
請參照第4圖與第7圖，在方法200之步驟208中，進行研磨(polishing)製程以移除位於STI元件112上方過量部份的第二半導體材料120。在此實施例中，研磨製程為施加在第二半導體材料120上的化學機械研磨(chemical mechanical polishing,CMP)，用以移除多餘的部份以及平坦化半導體結構100之頂表面。
請參照第5圖與第7圖，在方法200之步驟212中，凹蝕STI元件112以形成鰭型(fin-like)主動區(或鰭(fin)主動區)122。進行蝕刻製程以選擇性地(selectively)蝕刻STI 元件112，以凹蝕STI元件。蝕刻製程包括濕蝕刻或其他用以選擇性地蝕刻STI元件112的合適蝕刻製程。一實施例中，當STI包括氧化矽，蝕刻製程則係利用氫氟酸(hydrofluoric,HF)溶液。在一例子中，塗上2%的氫氟酸溶液以凹蝕STI元件112約兩分鐘。
如上所述，穿透錯位無法觸及到第二半導體材料120。因鰭型場效電晶體(fin-like field effect transistor,FINFET)本質上具有高高寬比，因此，這種技術較適用於FINFET。
請參照第6圖與第7圖，在方法200之步驟214中，進行離子佈植製程124以導入非活性(inactive)摻雜劑至鰭主動區122。在此實施例中，在非活性佈植後執行退火製程。特別的是，非活性摻雜劑具有小尺寸，能使如穿透錯位的缺陷去活化(deactivate)。退火製程有助於進一步地使非活性摻雜劑分佈，以有效地將穿透錯位缺陷去活化。應注意的是，非活性摻雜劑不同於n型或p型摻質，且非活性摻雜劑不具有n型或p型摻質的效果。不論第二半導體材料120為p型、n型、或中性，非活性摻雜劑不會改變第二半導體材料120的摻雜型態。離子佈植製程與退火製程係設計以大量地分佈非活性摻雜劑於鰭主動區122的底部部份中。較佳的是，非活性摻雜劑在垂直方向的摻雜濃度峰值(peak)與缺陷區域一致。在一例子中，摻雜濃度峰值大抵上係靠近第一與第二半導體材料之間的界面。
在此實施例中，非活性摻雜劑為氟。在第二半導體材料為鍺的實施例中，藉由佈植製程以將氟導入鰭主動區 122，氟能量(fluorine energy)為約20~200KeV，而氟劑量為約1x1012/cm2~1x1016/cm2。為了促進本實施例，退火製程的退火溫度為約400~700℃。因此，所形成的鰭主動區122的非活性摻雜輪廓具有約1x1017/cm3~1x1021/cm3的摻雜濃度峰值且其位於垂直位置(從頂表面)為約100~500nm處。
在第二半導體材料為鍺化矽(Si50Ge50)的實施例中，藉由氟能量(fluorine energy)為約10~80KeV且氟劑量為約1x1012/cm2~1x1016/cm2的佈植製程以將氟導入鰭主動區122。為了促進本實施例，退火製程的退火溫度為約500~900℃。因此，所形成的鰭主動區122的非活性摻雜輪廓具有為約1x1017/cm3~1x1021/cm3的摻雜濃度峰值且其位於垂直位置(從頂表面)為約100~500nm處。
在其他實施例中，亦可另外使用其他小尺寸的非活性摻雜劑以達到相同目的。舉例來說，可使用氯、硫、或硒作為非活性摻雜劑。
如上所述，即使有高寬比捕獲技術，穿透錯位仍存在。這些缺陷被抑制在鰭主動區122之底部部份位於第一與第二半導體材料之間的界面處，然而，實驗顯示這些缺陷具有電活性(electrically active)且會造成通道漏電(channel leakage)。非活性摻雜劑有效地減少這些缺陷的活性。如第8圖所示之鰭主動區122的示意圖，繪示出半導體材料120的一部份。在此例子中，半導體材料120為鍺(第8圖之大點)。鰭主動區122係晶質結構且其包括示範性(exemplary)的缺陷222。非活性摻雜劑(第8圖之小點)分佈至缺陷222且將缺陷 222去活化。
方法200包括其它步驟216以形成各種裝置元件，例如，配置閘疊、源極與汲極元件以形成各種FinFET。步驟216亦包括形成內連線結構，用以使FET與其他裝置連接，進而形成功能電路。以下將搭配第9圖與第10圖對步驟216作進一步的詳述。第9圖為根據本發明不同方面中的一實施例而製作的半導體結構250之上視圖。第10圖為根據本發明不同方面中的一實施例而製作的半導體結構250之剖面示意圖，其是由第9圖中的截線A-A’而得。一實施例中，半導體結構250為半導體結構100範例的一部份。
在基底110與鰭主動區122上方形成閘極252。閘極252包括閘疊254，閘疊254具有閘介電層與在閘介電層上方的閘電極層。閘介電層包括介電材料，例如，氧化矽、氧化鍺、高介電常數材料層、或前述之組合。在另一實施例中，閘介電層包括界面(interfacial)層(例如，氧化矽層或氧化鍺層)、以及在界面層上的高介電常數材料層。閘電極層包括導電材料層，例如，摻雜的多晶矽、金屬、金屬合金、或前述之組合。
可藉由一步驟形成閘疊254，步驟包括形成閘介電層、在閘介電層上形成閘電極層、以及圖案化閘電極層與閘介電層。閘疊254的形成可進一步包括閘替換(gate replacement)步驟，以將先形成的閘疊替換成高介電常數材料與金屬。當閘介電層與閘電極層在隨後的製作階段中皆被替換時，閘替換步驟可包括後閘極(gate last)操作、或後高介電常數材料(high last)操作。
閘極252亦可包括形成於閘疊254之側壁上的閘間隔物(gate spacer)256，閘間隔物256可藉由一步驟而形成，包括沉積、與異向性(anisotropic)蝕刻。
步驟216亦包括在鰭主動區122上形成各種源極與汲極元件。源極與汲極元件係形成於閘極252之兩側，且源極與汲極元件與閘極252被配置以形成FinFET。源極與汲極元件可包括輕摻雜汲極(lightly doped drain,LDD)元件258與重摻雜汲極元件(heavily doped drain,HDD)260兩者。源極與汲極元件係藉由離子佈植製程或其他合適的技術所形成。在閘疊252下方的鰭主動區122中形成通道，通道係被定義在源極與汲極元件之間。在一例子中，閘極252與源極與汲極元件係藉由一步驟所形成，包括形成閘疊254、形成LDD元件258、形成閘間隔物256、以及形成HDD元件260。
在一實施例中，步驟216亦包括在基底110上形成內連線結構，以提供電性路徑並連接各種裝置以形成功能電路。
內連線結構包括水平導電元件(金屬線)與垂直導電元件(例如，導孔與接點)。內連線結構又被稱為鋁內連線，其包括導電材料，例如，鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物、或前述之組合。可藉由物理氣相沉積(或濺鍍)、化學氣相沉積、或前述之組合等製程形成鋁內連線。其他製作鋁內連線的技術可包括微影(photolithography)處理與蝕刻以圖案化導電材料而形成垂直(導孔與接點)與水平連線(金屬線)。除此之外，可使用多層銅內連線，包括銅、銅合金、 鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物、或前述之組合。可藉由化學氣相沉積、濺鍍、電鍍或其他合適的製程形成多層銅內連線。用於多層內連線結構的金屬矽化物可包括矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鉑、矽化鉺、矽化鈀、或前述之組合。
內連線結構進一步包括用以隔離各種導電元件(金屬線、導孔、與接點)的層間介電層(interlayer dielectric或inter-lever dielectric,ILD)。ILD可為具有低介電常數(low-k)的材料，例如，介電常數小於約3.5的材料。ILD可包括二氧化矽、氮化矽、氮氧化矽、聚亞醯胺、旋塗式玻璃(spin-on glass,SOG)、氟摻雜矽玻璃(fluoride-doped silicate glass,FSG)、碳摻雜氧化矽、低介電常數材料、及/或其他合適的材料。可藉由一技術形成ILD，包括旋轉塗佈、濺鍍、或其他合適的製程。
可在方法200之前、期間、與之後執行其他製造步驟。
以各種實施例在上文對半導體結構及其製造方法200作敘述。不同實施例可呈現不同的優點。舉例來說，可降低或消除伴隨著缺陷的接面漏電流(junction leakage)。第10圖繪示出鰭主動區122的缺陷(穿透錯位)262。穿透錯位產生於在半導體基底110的第一半導體材料與鰭主動區122的第二半導體材料之間的界面，且穿透錯位會向上延伸。然而，因為特殊設計的鰭主動區122之高寬比，藉由STI元件的側壁而將穿透錯位抑制(trapped)在鰭主動區122的底部區域。此外，植入鰭主動區122中的非活性摻雜劑(在本例中為氟摻雜劑)有效地將 被抑制的穿透錯位去活化(與其他可能的缺陷)。因此，可大幅地降地或消除源極至主體(drain-to-bulk)漏電電流(例如，區域264的漏電)，進而改善對應的裝置之閉態(off-state)漏電。
本發明可用在不同的應用，其中整合不同的半導體材料以增強效能。在一例子中，這些應用包括應變式(strained)FinFET，例如鍺覆矽的n型FinFET。另一些例子中，這些應用包括形成在III-V上的高速與高頻裝置，例如，邏輯電路、記憶裝置、感測裝置、射頻裝置、或其他整合不同的半導體材料之裝置。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於後續本發明的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
100‧‧‧半導體結構
110‧‧‧半導體基底
112‧‧‧隔離元件
120‧‧‧第二半導體材料
122‧‧‧鰭主動區
124‧‧‧離子佈植製程

Claims (10)

  1. 一種半導體結構，包括：一半導體基底，其具有一第一半導體材料；多個淺溝隔離(shallow trench isolation,STI)元件，形成於該半導體基底中；以及一鰭型主動區，磊晶生長於該半導體基底上，該鰭型主動區具有一第二半導體材料；其中該第一半導體材料具有一第一晶格常數，而該第二半導體材料具有不同於該第一晶格常數的第二晶格常數，且該鰭型主動區更包括一非活性摻雜劑，其中該非活性摻雜劑係擇自於下列所組成之族群：硫及硒。
  2. 如申請專利範圍第1項所述之半導體結構，其中：該些STI元件具有一第一頂表面，而該鰭型主動區具有一第二頂表面，該第二頂表面不與該第一頂表面共平面且該第二頂表面從該些STI元件凸出；以及該些STI元件具有一第一底表面，而該鰭型主動區具有不與該第一底表面共平面的一第二底表面。
  3. 如申請專利範圍第2項所述之半導體結構，其中：具有該第二半導體材料的該鰭型主動區的一寬度W跨越兩個相鄰的STI元件，且該鰭型主動區的高度H係由該第二頂表面至該第二底表面的距離而測定，其中：該非活性摻雜劑具有從該第二頂表面至該第二底表面的濃度輪廓；以及該濃度輪廓具有一峰值，該峰值大抵上靠近該第二底表面。
  4. 如申請專利範圍第2項所述之半導體結構，更包括多個穿透錯位缺陷，分佈於該鰭型主動區中，其中藉由該非活性摻雜劑而將該些穿透錯位缺陷去活化，其中該些穿透錯位缺陷係分佈於該鰭型主動區的底部，且該些穿透錯位缺陷從該第二底表面向上延伸。
  5. 如申請專利範圍第1項所述之半導體結構，其中：該第一半導體材料為矽；以及該第二半導體材料包括鍺，其中：該第一半導體材料為矽；以及該第二半導體材料包括鍺化矽(SiGe)、磷化銦(InP)、砷化鎵銦(InGaAs)、或砷化銦(InAs)。
  6. 如申請專利範圍第1項所述之半導體結構，其中該非活性摻雜劑具有一濃度峰值，其靠近第一半導體材料與第二半導體材料之間的一界面。
  7. 如申請專利範圍第1項所述之半導體結構，其中：該些STI元件具有一第一底表面，而該主動區具有不與該第一底表面共平面的一第二底表面；具有該第二半導體材料的該鰭型主動區的一寬度W跨越兩個相鄰的STI元件，且主動區的高度H係由該主動區的一頂表面至該第二底表面的距離而測定；以及H/W比大於1.4。
  8. 一種鰭式場效電晶體(FinFET)的製造方法，包括：形成多個STI元件於具有一第一半導體材料的一半導體基底中，進而定義出藉由該些STI元件而分隔的多個半導體元件； 凹蝕該些半導體元件；磊晶生長一第二半導體材料於被凹蝕的該些半導體元件上，以形成具有該半導體材料的多個鰭式主動區，其中該第二半導體材料與該第一半導體材料具有一晶格失配(lattice mismatch)，該晶格失配產生多個穿透錯位缺陷於該鰭式主動區中；以及對該鰭式主動區進行一非活性摻雜劑之佈植製程，以將形成於該鰭式主動區中的該些穿透錯位缺陷去活化，其中該非活性摻雜劑係擇自於下列所組成之族群：硫及硒。
  9. 如申請專利範圍第8項所述之鰭式場效電晶體的製造方法，更包括：進行一研磨製程，以在磊晶生長該第二半導體材料後移除過多的該第二半導體材料；以及在此之後，凹蝕該STI元件。
  10. 如申請專利範圍第8項所述之鰭式場效電晶體的製造方法，更包括在進行該非活性摻雜劑之佈植製程後，對該鰭式主動區中的該非活性摻雜劑進行一退火製程，其中：該第一半導體材料為矽；磊晶生長該第二半導體的步驟包括磊晶生長鍺化矽；以及該退火製程之退火溫度為約500~900℃。
TW103100916A 2013-02-27 2014-01-10 半導體結構與鰭式場效電晶體的製造方法 TWI520342B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/779,286 US9184233B2 (en) 2013-02-27 2013-02-27 Structure and method for defect passivation to reduce junction leakage for finFET device

Publications (2)

Publication Number Publication Date
TW201434156A TW201434156A (zh) 2014-09-01
TWI520342B true TWI520342B (zh) 2016-02-01

Family

ID=51369578

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103100916A TWI520342B (zh) 2013-02-27 2014-01-10 半導體結構與鰭式場效電晶體的製造方法

Country Status (4)

Country Link
US (2) US9184233B2 (zh)
KR (1) KR101489081B1 (zh)
CN (1) CN104008962B (zh)
TW (1) TWI520342B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425276B (zh) * 2013-09-04 2017-06-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN105493253B (zh) 2013-09-25 2019-11-29 英特尔公司 用于finfet架构的用固态扩散源掺杂的隔离阱
US9184087B2 (en) 2013-12-27 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming FinFETs with different fin heights
US9450096B2 (en) 2014-04-10 2016-09-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9214358B1 (en) * 2014-10-30 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Equal gate height control method for semiconductor device with different pattern densites
KR101587430B1 (ko) * 2014-12-05 2016-01-22 (재)한국나노기술원 실리콘(001) 기판 상에 반도체 에피층 성장방법
CN107004709B (zh) * 2014-12-22 2021-10-15 英特尔公司 防止子沟道漏电流的半导体装置
US9379243B1 (en) * 2015-02-19 2016-06-28 Intermational Business Machines Corporation Field-effect transistor with aggressively strained fins
US9443729B1 (en) * 2015-03-31 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming FinFET devices
KR102310082B1 (ko) * 2015-04-27 2021-10-08 삼성전자주식회사 핀 바디 및 에피택시얼 막을 포함하는 반도체 소자
DE112015006974T5 (de) 2015-09-25 2019-01-24 Intel Corporation Verfahren zum Dotieren von Finnenstrukturen nicht planarer Transsistorenvorrichtungen
CN106601619B (zh) * 2015-10-16 2019-10-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
US9960053B2 (en) 2015-12-15 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET doping methods and structures thereof
CN106971977B (zh) * 2016-01-13 2020-01-31 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10522365B2 (en) * 2016-01-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for reducing scratch defects in chemical mechanical planarization
CN109417033B (zh) * 2016-06-28 2022-03-18 株式会社索思未来 半导体装置以及半导体集成电路
KR102301850B1 (ko) * 2016-11-24 2021-09-14 삼성전자주식회사 액티브 패턴 구조물 및 액티브 패턴 구조물을 포함하는 반도체 소자
US10163628B1 (en) * 2017-05-31 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Lattice-mismatched semiconductor substrates with defect reduction
SG11202001191VA (en) * 2017-09-03 2020-03-30 Applied Materials Inc Conformal halogen doping in 3d structures using conformal dopant film deposition
US10658174B2 (en) 2017-11-21 2020-05-19 Lam Research Corporation Atomic layer deposition and etch for reducing roughness
US10734238B2 (en) 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
US10515815B2 (en) * 2017-11-21 2019-12-24 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation
US10446394B2 (en) 2018-01-26 2019-10-15 Lam Research Corporation Spacer profile control using atomic layer deposition in a multiple patterning process
CN110970300B (zh) * 2018-09-29 2023-09-22 中芯国际集成电路制造(上海)有限公司 堆叠环栅鳍式场效应管及其形成方法
US11373870B2 (en) * 2019-06-27 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device including performing thermal treatment on germanium layer
US11195724B1 (en) * 2020-07-01 2021-12-07 Nanya Technology Corporation Method of manufacturing semiconductor structure

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126732A (en) * 1977-08-16 1978-11-21 The United States Of America As Represented By The Secretary Of The Navy Surface passivation of IV-VI semiconductors with As2 S3
FR2650704B1 (fr) * 1989-08-01 1994-05-06 Thomson Csf Procede de fabrication par epitaxie de couches monocristallines de materiaux a parametres de mailles differents
CN1253929C (zh) * 2003-03-04 2006-04-26 松下电器产业株式会社 半导体装置及其制造方法
US6927106B2 (en) * 2003-10-29 2005-08-09 Texas Instruments Incorporated Methods for fabricating a triple-gate MOSFET transistor
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
KR20050089621A (ko) * 2004-03-05 2005-09-08 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조방법
US20080121932A1 (en) * 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
US8338887B2 (en) * 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US7466009B2 (en) * 2006-06-05 2008-12-16 Texas Instruments Incorporated Method for reducing dislocation threading using a suppression implant
US20080054361A1 (en) * 2006-08-30 2008-03-06 Infineon Technologies Ag Method and apparatus for reducing flicker noise in a semiconductor device
US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20080111185A1 (en) * 2006-11-13 2008-05-15 International Business Machines Corporation Asymmetric multi-gated transistor and method for forming
US8076228B2 (en) * 2007-01-29 2011-12-13 Infineon Technologies Ag Low noise transistor and method of making same
CN101560693A (zh) * 2009-04-22 2009-10-21 浙江碧晶科技有限公司 一种含有掺杂元素的太阳能级硅晶体的制备方法
US8338884B2 (en) * 2009-05-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Selective epitaxial growth of semiconductor materials with reduced defects
US20110062492A1 (en) * 2009-09-15 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology
EP2315239A1 (en) * 2009-10-23 2011-04-27 Imec A method of forming monocrystalline germanium or silicon germanium
US8021949B2 (en) * 2009-12-01 2011-09-20 International Business Machines Corporation Method and structure for forming finFETs with multiple doping regions on a same chip
US8455929B2 (en) * 2010-06-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of III-V based devices on semiconductor substrates
US8062963B1 (en) * 2010-10-08 2011-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device having an epitaxy region
US8349716B2 (en) * 2010-10-25 2013-01-08 International Business Machines Corporation Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device
US8901537B2 (en) * 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
US8871670B2 (en) * 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces
KR20140024303A (ko) * 2011-03-04 2014-02-28 모자이크 크리스탈즈 리미티드 금속-비금속 화합물의 계면활성제 결정 성장을 위한 방법
WO2012149111A1 (en) 2011-04-26 2012-11-01 The Regents Of The University Of California Methods of promoting cns neuronal repair by inhibiting lrp-1
US8624326B2 (en) * 2011-10-20 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8912606B2 (en) * 2012-04-24 2014-12-16 Globalfoundries Inc. Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
US8680576B2 (en) * 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8828834B2 (en) * 2012-06-12 2014-09-09 Globalfoundries Inc. Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
US8674413B1 (en) * 2012-11-07 2014-03-18 Globalfoundries Inc. Methods of forming fins and isolation regions on a FinFET semiconductor device
US8772117B2 (en) * 2012-12-05 2014-07-08 Globalfoundries Inc. Combination FinFET and planar FET semiconductor device and methods of making such a device
US8815659B2 (en) * 2012-12-17 2014-08-26 Globalfoundries Inc. Methods of forming a FinFET semiconductor device by performing an epitaxial growth process
US8815685B2 (en) * 2013-01-31 2014-08-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits having confined epitaxial growth regions
US8853008B1 (en) * 2013-03-14 2014-10-07 Intermolecular, Inc. Counter-doped low-power FinFET

Also Published As

Publication number Publication date
US9184233B2 (en) 2015-11-10
KR101489081B1 (ko) 2015-02-02
KR20140107080A (ko) 2014-09-04
TW201434156A (zh) 2014-09-01
CN104008962B (zh) 2017-12-19
US9806176B2 (en) 2017-10-31
US20160056270A1 (en) 2016-02-25
CN104008962A (zh) 2014-08-27
US20140239347A1 (en) 2014-08-28

Similar Documents

Publication Publication Date Title
TWI520342B (zh) 半導體結構與鰭式場效電晶體的製造方法
TWI622129B (zh) 半導體結構及其製造方法
TWI648856B (zh) 半導體結構及其製造方法
US9070742B2 (en) FinFet integrated circuits with uniform fin height and methods for fabricating the same
TWI390708B (zh) 積體電路
US9373697B2 (en) Spacer replacement for replacement metal gate semiconductor devices
KR20180069703A (ko) 반도체 디바이스 및 방법
US11355603B2 (en) Methods and structures of novel contact feature
KR20160040411A (ko) FinFET 및 FinFET을 형성하는 방법
US9177956B2 (en) Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture
TW201635517A (zh) 具有替代通道材料之電性絕緣鰭片結構及其製法
US11749742B2 (en) Self-aligned inner spacer on gate-all-around structure and methods of forming the same
US9385051B2 (en) Method for the formation of a FinFET device having partially dielectric isolated fin structure
CN110034070B (zh) 具有嵌入式存储器件的结构、集成电路结构及其制造方法
KR20160100202A (ko) FinFET 디바이스의 구조물 및 형성 방법
US20180114863A1 (en) Finfet transistor gate and epitaxy formation
WO2013143032A1 (zh) 半导体器件及其制造方法
US9099570B2 (en) Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices
US11749744B2 (en) Fin structure for vertical transport field effect transistor
TWI671909B (zh) 防止子通道漏電流的設備
JP2012039003A (ja) 半導体装置
JP2011228596A (ja) 半導体装置及びその製造方法
JP5689606B2 (ja) 半導体装置及びその製造方法