TWI517320B - 晶片封裝體 - Google Patents
晶片封裝體 Download PDFInfo
- Publication number
- TWI517320B TWI517320B TW103127571A TW103127571A TWI517320B TW I517320 B TWI517320 B TW I517320B TW 103127571 A TW103127571 A TW 103127571A TW 103127571 A TW103127571 A TW 103127571A TW I517320 B TWI517320 B TW I517320B
- Authority
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- Taiwan
- Prior art keywords
- chip package
- recess
- wire
- semiconductor substrate
- extends
- Prior art date
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- 239000000758 substrate Substances 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 65
- 238000007789 sealing Methods 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 82
- 235000012431 wafers Nutrition 0.000 description 31
- 238000000034 method Methods 0.000 description 22
- 238000005530 etching Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
Classifications
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/3157—Partial encapsulation or coating
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- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本發明係有關於一種晶片封裝體,特別為有關於以晶圓級封裝製程所形成之晶片封裝體。
傳統晶片封裝體的製程涉及多道的圖案化製程與材料沉積製程,不僅耗費生產成本,亦需較長的製程時間。
因此,業界亟需更為簡化與快速的晶片封裝技術。
本發明實施例係提供一種晶片封裝體,包括一半導體基底,具有一第一表面及與其相對的一第二表面。一介電層位於半導體基底的第一表面上,其中介電層包括一開口,露出一導電墊。一側邊凹陷至少位於半導體基底之一第一側邊,且由第一表面朝第二表面延伸。一上凹陷至少位於導電墊外側的介電層之一第一側邊。一導線電性連接導電墊,且延伸至上凹陷及側邊凹陷。
100‧‧‧半導體基底
100a‧‧‧第一表面
100b‧‧‧第二表面
101、102、103、104‧‧‧半導體基底的側邊
110‧‧‧晶片區
120‧‧‧預定切割區
130‧‧‧介電層
150、152‧‧‧導電墊
160‧‧‧絕緣層
200、200a、200b、210‧‧‧側邊凹陷
220、230‧‧‧凹陷
250‧‧‧密封環
250a、250b、250c、250d‧‧‧密封環的邊
300、301、302、305、306、307‧‧‧導線
303a、303b、304a、304b‧‧‧導線的部分
401A、401B、402、403A、404‧‧‧罩幕層
403B‧‧‧圖案化罩幕層
410、430‧‧‧黏著層
420‧‧‧暫時基底
440‧‧‧支撐基底
500‧‧‧晶片封裝體
600‧‧‧電路板
610‧‧‧接觸墊
620‧‧‧導電結構
Aa、Ab‧‧‧底部面積
Da、Db‧‧‧凹陷深度
SC‧‧‧切割道
X、X’‧‧‧距離
第1A圖係繪示出根據本發明一實施例之晶片封裝體的平面示意圖。
第1B圖係繪示出沿著第1A圖中的剖線1B-1B’的剖面示意圖。
第2至6圖係繪示出側邊凹陷之設置的各種實施例的平面示意圖。
第7A及8A圖係繪示出具有密封環之晶片封裝體的不同實施例的平面示意圖。
第7B及8B圖係分別繪示出沿著第7A及8A圖中的剖線7B-7B’及8B-8B’的剖面示意圖。
第9-12圖係繪示出導線的各種實施例的平面示意圖。
第13、14A、15A、16A-1、16A-2及17至22圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第14B、15B及16B圖係繪示出不同於第14A、15A、16A-1及16A-2圖的另一實施例的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是,本發明提供許多可供應用的發明概念,其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。此外,在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明,不代表所討論之不同實施例及/或結構之間具有任何關連性。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此,例如在本發明之晶片封裝體的
實施例中,其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components),例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完
成封裝步驟後,再予以切割成獨立的封裝體,然而,在一特定實施例中,例如將已分離之半導體晶片重新分布在一承載晶圓上,再進行封裝製程,亦可稱之為晶圓級封裝製程。另外,上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓,以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
以下配合第1A及1B圖說明本發明一實施例之晶片
封裝體,其中第1A圖係繪示出根據本發明一實施例之晶片封裝體的平面示意圖,且第1B圖係繪示出沿著第1A圖中的剖線1B-1B’的剖面示意圖。
在本實施例中,晶片封裝體包括一半導體基底
100、複數導電墊150、一介電層130、一絕緣層160、複數導線300、一側邊凹陷200。半導體基底100具有一第一表面100a及與其相對的一第二表面100b,且包括一晶片區110及圍繞晶片區110的一預定切割區120,其中晶片區110內包括一裝置區115,如第1A圖所示。裝置區115中可包括(但不限於)感測元件,例如影像感測元件。在一實施例中,半導體基底100為一矽晶圓,以利於進行晶圓級封裝。
導電墊150設置於晶片區110內的半導體基底100
的第一表面100a上。導電墊150可包括單層或多層之導電層,且透過內部線路(未繪示)而與裝置區115電性連接。
介電層130位於晶片區110內的半導體基底100的
第一表面100a上,且可包括多層介電層之疊層及/或位於頂部之保護層(passivation layer)。介電層130具有開口露出導電墊150,且介電層130還具有一上凹陷,位於導電墊150外側的介電層130之第一側邊(其與半導體基底100之第一側邊101為同一側),上凹陷露出半導體基底100的第一表面100a,如第1B圖所示。
側邊凹陷200位於預定切割區120內。在一實施例中,側邊凹陷200由深側邊凹陷200a及淺側邊凹陷200b組成,其形成階梯狀側邊凹陷。側邊凹陷200位於半導體基底100之第一側邊101,而橫跨第一側邊101之全部長度,如第1A圖所示。側邊凹陷200由第一表面100a朝第二表面100b延伸,如第1B圖所示。雖然第1A圖繪示出深側邊凹陷200a及淺側邊凹陷200b
皆橫跨第一側邊101之全部長度,然而在某些實施例中,可僅有深側邊凹陷200a橫跨第一側邊101之全部長度。另外,可以理解的是,第1A及1B圖中側邊凹陷的數量僅作為範例說明,並不限定於此,其實際數量取決於設計需求。舉例來說,在一實施例中,晶片封裝體具有僅由深側邊凹陷200a所形成之懸崖狀側邊凹陷,而未包括淺側邊凹陷200b。在另一實施例中,晶片封裝體具有由三個以上的連續側邊凹陷所形成之多階側邊凹陷。
絕緣層160位於介電層130上,且延伸至介電層130
的開口內而覆蓋一部分的導電墊150,並進一步沿著淺側邊凹陷200b之側壁與底部延伸至深側邊凹陷200a之側壁與底部,如第1B圖所示。
導線300設置於半導體基底100的第一表面100a
上,且位於裝置區115之外的絕緣層160上。導線300延伸至未被絕緣層160完全覆蓋的導電墊150而與其電性連接,且更延伸至介電層130內的上凹陷,並進一步沿著淺側邊凹陷200b之側壁與底部延伸至深側邊凹陷200a之側壁與底部上的絕緣層160上,如第1B圖所示。在本實施例中,每一導電墊150分別電性連接至每一導線300,如第1A圖所示。
在一實施例中,如第21及22圖所示,晶片封裝體
可進一步設置於電路板600上,延伸至側邊凹陷200之側壁與底部的導線300可透過導電結構620(例如,第21圖所繪示的焊線及第22圖所繪示的焊球),與電路板600上之接觸墊610電性連接。
根據上述實施例,晶片封裝體的第一側邊101具有
側邊凹陷200,其上表面低於半導體基底100的第一表面100a,因此當晶片封裝體透過導電結構620與電路板600電性連接時,能夠降低導電結構620之高度,進而有效降低晶片封裝體的整體尺寸。另外,由於側邊凹陷200橫跨半導體基底100的第一側邊101之全部長度或寬度,因此可增加晶片封裝體之輸出訊號的布局彈性。
回到第1A圖,深側邊凹陷200a及淺側邊凹陷200b
之底部分別具有底部面積Aa及Ab,底部最接近第二表面100b的深側邊凹陷200a之底部面積Aa大於淺側邊凹陷200b之底部面積Ab。在另一實施例中,晶片封裝體之同一側邊可包括三個以上的連續側邊凹陷而形成多階側邊凹陷,且每一側邊凹陷之底部分別具有一底部面積,底部最接近第二表面100b的側邊凹陷之底部面積最大。由於底部最接近第二表面100b的側邊凹陷之底部面積最大,因此晶片封裝體能夠採用多種電性連接的方式。
如第1B圖所示,深側邊凹陷200a及淺側邊凹陷
200b之底部與側壁頂端之間分別具有凹陷深度Da及Db,底部最接近第二表面100b的深側邊凹陷200a之凹陷深度Da大於淺側邊凹陷200b之凹陷深度Db。在另一實施例中,晶片封裝體之同一側邊可包括三個以上的連續側邊凹陷而形成多階側邊凹陷,且每一側邊凹陷之底部與側壁頂端之間分別具有一凹陷深度,底部最接近第二表面100b的側邊凹陷之凹陷深度最大。由於底部最接近第二表面100b的側邊凹陷之凹陷深度最大,因此
可減少晶片封裝體之面積損耗。
第2至6圖係繪示出側邊凹陷之設置的各種實施例
的平面示意圖,其中相同於第1A圖的部件係使用相同的標號並省略其說明,且為了清楚顯示相對位置關係,第2至6圖中並未繪示出絕緣層160及導線300。
第2圖係繪示出側邊凹陷200橫跨第一側邊101之
全部長度,且更延伸至與第一側邊101相鄰之第二側邊102的至少一部份。第3圖係繪示出側邊凹陷200橫跨第一側邊101之全部長度,且更延伸至與第一側邊101相鄰之兩側邊102及104的至少一部份。在其他實施例中,側邊凹陷200可連續地延伸而橫跨半導體基底100的兩側邊、三側邊或四側邊的全部長度。
第4圖係繪示出晶片封裝體包括獨立的兩個側邊
凹陷200及210的一實施例。側邊凹陷200及210分別位於半導體基底100的相對兩側邊101及103,且各自橫跨側邊101及103之全部長度。同樣地,側邊凹陷200及210可更延伸至相鄰的第二側邊102的至少一部分或相鄰的兩側邊102及104的各至少一部分。例如,如第5圖所示,側邊凹陷200更延伸至相鄰的第二側邊102的至少一部分。如第6圖所示,側邊凹陷200更延伸至相鄰的兩側邊102及104的各至少一部分。因此,本發明所屬技術領域中具有通常知識者可以理解,雖然未繪示於圖式中,只要側邊凹陷延伸橫跨半導體基底100的一側邊的全部長度或寬度,側邊凹陷200及210皆可具有其他的配置方式。
以下配合第7A、7B、8A及8B圖說明具有密封環之
晶片封裝體的不同實施例,其中第7A及8A圖係繪示出具有密
封環之晶片封裝體的平面示意圖,且第7 B及8 B圖係分別繪示出沿著第7A及8A圖中的剖線7B-7B’及8B-8B’的剖面示意圖。
第7A、7B、8A及8B圖中相同於第1A及1 B圖的部件係使用相同的標號並省略其說明。
請參照第7A及7B圖,晶片封裝體更包括一密封環
250,設置於半導體基底100的第一表面100a上的介電層130內,而位於半導體基底100與絕緣層160之間。密封環250之形狀為四邊形,且圍繞導電墊150。導線300跨越密封環250而延伸至介電層130內的上凹陷及側邊凹陷200。在一實施例中,密封環802之材質為導電材料。在第7A及7B圖的實施例中,側邊凹陷200僅位於預定切割區120內,且密封環250的每一邊250a、250b、250c及250d分別與半導體基底100之每一側邊101、102、103及104之間的距離X相同。
在第7A及7B圖的實施例中,側邊凹陷200僅位於預
定切割區120內,而不會占用晶片區110之面積,因此可節省半導體晶圓之面積,使得半導體基底100可具有較大之布局面積而可整合更多元件,進而提升晶片封裝體之效能。在一實施例中,可採用較細之切割刀進行切割,保留位於預定切割區120中之部分的半導體基底100及所形成之側邊凹陷200。
第8A及8B圖的晶片封裝體的結構類似於第7A及
7B圖的晶片封裝體的結構,差異在於側邊凹陷200除了位於預定切割區120且更延伸至晶片區110內,使得密封環250中接近第一側邊101的一邊250a與第一側邊101之間的距離X’大於密封環250的其餘三邊250b、250c及250d分別與半導體基底100之
其餘三邊102、103及104之間的距離X。
需注意的是,第7A及7B、8A及8B圖的密封環配置
可與上述第1A及1B、2至6圖的側邊凹陷配置互相組合而產生各種變化例。舉例來說,如第10圖所示,將第8A及8B圖的實施例與第2圖的實施例互相組合時,側邊凹陷200延伸至與第一側邊101相鄰之第二側邊102的至少一部份,且更延伸至晶片區110內,使得密封環250中接近第一側邊101的一邊250a與第一側邊101之間的距離X’以及接近第二側邊102的一邊250b與第二側邊102之間的距離X’,皆大於密封環250的其餘兩邊250c及250d分別與半導體基底100之其餘兩邊103及104之間的距離X。
請參照第9圖,其繪示出導電墊151未電性連接至導線300,而可透過植球的方式,形成外部的電性連接結構。請再參照第10圖,當側邊凹陷200橫跨第一側邊101之全部長度,且更延伸至與第一側邊101相鄰之第二側邊102的至少一部份時,一導線301直接延伸至位於第二側邊102的側邊凹陷200,而進一步透過其他導電結構(例如,焊線或焊球)而與其他構件(例如,電路板上之接觸墊)電性連接。如此一來,可有效縮短導線的導電路徑,增加訊號傳遞速度,並可節省所佔用之半導體基底100的表面面積。
在一實施例中,一導線302延伸至位於第二側邊102的側邊凹陷200,且更從第二側邊102的側邊凹陷200內延伸至位於第一側邊101的側邊凹陷200內,因此可增加導線的布局彈性,且可節省所佔用之半導體基底100的表面面積。
請參照第11圖,在一實施例中,晶片封裝體的絕
緣層160可能具有凸起或溝槽,延伸至絕緣層160的凸起上或溝槽內的導線300可包括鄰近於凸起或溝槽的一第一部分303a及與其連接的一第二部分303b。此時,導線300的第一部分303a的橫向寬度大於第二部分303b的橫向寬度。在另一實施例中,導線300包括鄰近於介電層130內的上凹陷或側邊凹陷200a之側壁頂端及側壁底端的一第一部分304a及與其連接的一第二部分304b。此時,第一部分304a的橫向寬度大於第二部分304b的橫向寬度,因此可避免斷線而增加導線300之可靠度。
請參照第12圖,在一實施例中,延伸至側邊凹陷
200的導線305電性連接至兩個導電墊150及152。在另一實施例中,,延伸至側邊凹陷200的兩導線306及307可彼此電性接觸。
本發明所屬技術領域中具有通常知識者可以理
解,第9至12圖的實施例可與上述第1A及1B、2至6、7A及7B、8A及8B圖的實施例互相結合。雖然未繪示於圖式中,只要側邊凹陷延伸橫跨半導體基底100的一側邊的全部長度或寬度,導線及導電墊皆可具有其他的配置方式。
以下配合第13、14A、14B、15A、15B、16A-1、
16A-2、16B及17至20圖說明本發明實施例之晶片封裝體的製造方法,其中第13、14A、15A、16A-1、16A-2及17至20圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖,且第14B、15B及16B圖係繪示出不同於第14A、15A、16A-1及16A-2圖的另一實施例的剖面示意圖。
請參照第13圖,提供一半導體基底100(例如,半導
體晶圓),其具有一第一表面100a及與其相對的一第二表面
100b,且包括複數晶片區110及分離晶片區110的預定切割區120,其中預定切割區120內定義有一切割道SC。每一晶片區110內包括一裝置區115,裝置區115中可包括(但不限於)感測元件,例如影像感測元件。在一實施例中,半導體基底100為一矽晶圓,以利於進行晶圓級封裝。
導電墊150設置於晶片區110內的半導體基底100
的第一表面100a上。導電墊150可包括單層或多層之導電層,且透過內部線路(未繪示)而與裝置區115電性連接。
介電層130形成於晶片區110內的半導體基底100
的第一表面100a上,且可包括多層介電層之疊層及/或位於頂部之保護層。介電層130具有開口露出導電墊150。
請參照第14A圖,在介電層130上形成遮罩層
401A(例如,圖案化光阻層)。遮罩層401A具有露出預定切割區120的介電層130之開口。接著,進行蝕刻製程,移除第一部分的介電層130,而露出預定切割區120內部分的半導體基底100。
接著,請參照第15A圖,在移除遮罩層401A之後,
在介電層130上形成遮罩層402,其具有露出預定切割區120內部分的半導體基底100之開口。接著,進行蝕刻製程,移除露出之半導體基底100,形成一凹陷200。在一實施例中,可採用斜角度乾蝕刻製程來形成凹陷200。
凹陷220位於預定切割區120內,且由第一表面100a朝第二表面100b延伸,並延伸於部分的遮罩層402之下。在一實施例中,所形成之凹陷220之側壁及底部可能凹凸不平而呈現鋸齒狀輪廓。
接著,請參照第16A-1圖,在移除遮罩層402之後,
選擇性進行蝕刻製程(例如,毯覆式蝕刻製程),以使凹陷220之側壁及底部之輪廓平滑化。在一實施例中,在平滑化凹陷220之側壁及底部之輪廓期間,所採用之蝕刻製程可移除介電層130下方之部分的半導體基底100,進而形成另一凹陷230。凹陷220及230之側壁及底部大抵平滑,可利於後續於其上形成材料層。
接著,請參照第16A-2圖,在介電層130上形成遮
罩層403A,其具有露出凹陷220及230以及第二部分的介電層130之開口。接著,進行蝕刻製程,移除第二部分的介電層130,而露出凹陷220及230以及晶片區110內部分的半導體基底100。在一實施例中,所露出之半導體基底100之第一表面100a與凹陷220及230之底部為大抵彼此平行之平面。
第14B、15B及16B圖係繪示出不同於第14A、15A、
16A-1及16A-2圖的另一實施例的剖面示意圖。第14B圖中的遮罩層401B的開口大於第14A圖中的遮罩層401A的開口,以同時移除第一及第二部分的介電層130。接著,如第15B圖所示,在移除遮罩層401B之後,在介電層130上形成遮罩層402,並進行蝕刻製程,形成一凹陷220。在一實施例中,可採用斜角度乾蝕刻製程來形成凹陷220。
接著,請參照第16B圖,在移除遮罩層402之後,
在介電層130上形成圖案化遮罩層403B,並進行蝕刻製程(例如,毯覆式蝕刻製程),以使凹陷220之側壁及底部之輪廓平滑化。在一實施例中,在平滑化凹陷220之側壁及底部之輪廓期
間,所採用之蝕刻製程可移除一部分的半導體基底100,進而形成另一凹陷230。
請參照第17圖,在移除遮罩層403A或圖案化遮罩
層403B之後,在介電層130上形成絕緣層160。絕緣層160延伸至介電層130的開口內而覆蓋導電墊150,並進一步沿著凹陷230之側壁與底部延伸至凹陷220之側壁與底部。接著,在絕緣層160上形成遮罩層404,其具有露出導電墊150上方的部分的絕緣層160之開口,並進行蝕刻製程,移除部分的絕緣層116,以露出部分的導電墊150。
接著,請參照第18圖,在移除遮罩層404之後,在
絕緣層160上形成導線300。導線300延伸至露出的導電墊150而與其電性連接,並進一步延伸至凹陷220之側壁與底部上的絕緣層160上。在一實施例中,導線300未與切割道SC重疊,以利後續切割製程之進行。
接著,沿著切割道SC,從半導體基底100的第一表
面100a朝第二表面100b,移除部分的絕緣層160及半導體基底100,以形成切割道SC的溝槽。切割道SC的溝槽通過凹陷220之底部,將凹陷220切割為分離的深側邊凹陷200a,且將凹陷230切割為分離的淺側邊凹陷200b。深側邊凹陷200a及淺側邊凹陷200b組成階梯狀的側邊凹陷200。
可以理解的是,側邊凹陷的實際數量取決於設計
需求。舉例來說,在一實施例中,未進行毯覆式蝕刻製程,而於半導體基底100內形成由深側邊凹陷200a所構成之懸崖狀側邊凹陷。在另一實施例中,可透過進行多次蝕刻製程,在半導
體基底100內形成由三個以上的連續側邊凹陷所構成之多階側邊凹陷。
請參照第19圖,透過黏著層410,將暫時基底420
固定於半導體基底100之第一表面100a上,並以暫時基底420為支撐,對半導體基底100之第二表面100b進行薄化製程,例如機械研磨製程或化學機械研磨製程,以減少半導體基底100的厚度,並露出切割道SC的溝槽,從而形成複數彼此分離之晶片封裝體。在一實施例中,暫時基底420可為玻璃基底或矽晶圓。
請參照第20圖,在半導體基底100之第二表面100b
上設置黏著層430及支撐基底440,且移除黏著層410及暫時基底420。在一實施例中,黏著層430中僅有面向半導體基底100之第一表面100a的表面具有黏性。在一實施例中,沿著切割道SC的溝槽進行切割製程,移除部分的黏著層430及支撐基底440,以將晶片封裝體500彼此分離。
在一實施例中,如第21圖所示,可進一步將電路
板600設置於晶片封裝體500的半導體基底100的第二表面100b上,且透過導電結構620,例如焊線,將延伸至側邊凹陷200的導線300電性連接至電路板600上的接觸墊610。在另一實施例中,如第22圖所示,導電結構620可為焊球。在其他實施例中,可採用導電層、導電塊、其他適合的導電結構或上述之組合作為導電結構620。在本實施例中,導電結構620可低於介電層130內的上凹陷上方的導線300。
根據上述晶片封裝體的製造方法,每一晶片封裝
體500具有側邊凹陷200位於晶片封裝體500的半導體基底100
之第一側邊101,且至少橫跨第一側邊101之全部長度,如第1A圖所示。由於側邊凹陷200的上表面低於半導體基底100的第一表面100a,因此當晶片封裝體透過導電結構620與電路板600電性連接時,能夠降低導電結構620之高度,進而有效降低晶片封裝體的整體尺寸。另外,由於側邊凹陷200橫跨半導體基底100的第一側邊101之全部長度或寬度,因此可增加晶片封裝體之輸出訊號的布局彈性。
本發明所屬技術領域中具有通常知識者可以理解,上述晶片封裝體的製造方法可應用於前述第1A及1B、2至6、7A及8A、7B及8B、9至12圖的各種實施例之晶片封裝體。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基板
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧晶片區
120‧‧‧預定切割區
130‧‧‧介電層
150‧‧‧導電墊
160‧‧‧絕緣層
200、200a、200b‧‧‧側邊凹陷
300‧‧‧導線
Da、Db‧‧‧深度
Claims (22)
- 一種晶片封裝體,包括:一半導體基底,具有一第一表面及與其相對的一第二表面;一介電層,位於該半導體基底的該第一表面上,其中該介電層包括一開口,露出一導電墊;一側邊凹陷,至少位於該半導體基底之一第一側邊,由該第一表面朝該第二表面延伸;一上凹陷,至少位於該導電墊外側的該介電層之一第一側邊;以及一導線,電性連接該導電墊,且延伸至該上凹陷及該側邊凹陷。
- 如申請專利範圍第1項所述之晶片封裝體,其中該側邊凹陷更延伸至與該第一側邊相鄰的一第二側邊的至少一部分。
- 如申請專利範圍第2項所述之晶片封裝體,其中該導線延伸至位於該第二側邊的該側邊凹陷。
- 如申請專利範圍第3項所述之晶片封裝體,其中該導線更從該第二側邊的該側邊凹陷延伸至位於該第一側邊的該側邊凹陷。
- 如申請專利範圍第1項所述之晶片封裝體,其中該側邊凹陷更延伸至與該第一側邊相鄰之兩側邊的各至少一部分。
- 如申請專利範圍第1項所述之晶片封裝體,其中該晶片封裝體包括獨立的兩個側邊凹陷,分別位於該半導體基底的相對兩側邊,且各自橫跨該側邊之全部長度。
- 如申請專利範圍第6項所述之晶片封裝體,其中該等側邊凹陷中的至少一者更延伸至相鄰的一側邊的至少一部分。
- 如申請專利範圍第6項所述之晶片封裝體,其中該等側邊凹陷中的至少一者更延伸至相鄰的兩側邊的各至少一部分。
- 如申請專利範圍第1項所述之晶片封裝體,其中該晶片封裝體包括連續的複數側邊凹陷,位於該導電墊外側,且其中每一側邊凹陷之一底部與一側壁頂端之間具有一凹陷深度,該底部最接近該第二表面的一第一側邊凹陷之該凹陷深度最大。
- 如申請專利範圍第1項所述之晶片封裝體,其中該晶片封裝體包括連續的複數側邊凹陷,位於該導電墊外側,且其中每一側邊凹陷之一底部具有一底部面積,該底部最接近該第二表面的一第一側邊凹陷之該底部面積最大。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一密封環,圍繞該導電墊,其中該密封環之形狀為一四邊形,且其中該導線跨越該密封環而延伸至該上凹陷及該側邊凹陷。
- 如申請專利範圍第11項所述之晶片封裝體,其中該密封環的每一邊分別與該半導體基底之每一側邊之間的距離相同。
- 如申請專利範圍第11項所述之晶片封裝體,其中該密封環中接近該第一側邊的一邊與該第一側邊之間的距離大於該密封環的其餘三邊分別與該半導體基底之其餘三邊之間的 距離。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一絕緣層,設置於該導線下方且位於該介電層及該半導體基底上方,其中該導線延伸至該絕緣層的一凸起上或一溝槽內,且該導線包括鄰近於該凸起或該溝槽的一第一部分及與其連接的一第二部分,且其中該第一部分的橫向寬度大於該第二部分的橫向寬度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該導線包括鄰近於該上凹陷或該側邊凹陷之一側壁頂端及一側壁底端的一第一部分及與其連接的一第二部分,且其中該第一部分的橫向寬度大於該第二部分的橫向寬度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該導線更電性連接至另一導電墊。
- 如申請專利範圍第1項所述之晶片封裝體,其中該上凹陷露出該半導體基底的該第一表面。
- 如申請專利範圍第17項所述之晶片封裝體,其中該導線包括一第一部分及與其連接的一第二部分,且其中該第一部分的橫向寬度大於該第二部分的橫向寬度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該導線包括一第一部分及與其連接的一第二部分,且其中該第一部分的橫向寬度大於該第二部分的橫向寬度。
- 如申請專利範圍第19項所述之晶片封裝體,更包括一電路板,其中該導線透過一導電結構電性連接至該電路板上的一接觸墊。
- 如申請專利範圍第20項所述之晶片封裝體,其中該導電結構為一焊線或一焊球。
- 如申請專利範圍第20項所述之晶片封裝體,其中該導電結構低於該上凹陷上方的該導線。
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TW200917391A (en) * | 2007-06-20 | 2009-04-16 | Vertical Circuits Inc | Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication |
TWI536525B (zh) * | 2010-05-11 | 2016-06-01 | 精材科技股份有限公司 | 晶片封裝體 |
CN103107153B (zh) * | 2011-11-15 | 2016-04-06 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
TWI546921B (zh) * | 2013-03-14 | 2016-08-21 | 精材科技股份有限公司 | 晶片封裝體及其形成方法 |
EP2838114A3 (en) * | 2013-08-12 | 2015-04-08 | Xintec Inc. | Chip package |
-
2014
- 2014-08-11 EP EP14180536.6A patent/EP2838114A3/en not_active Withdrawn
- 2014-08-12 CN CN201410394689.0A patent/CN104377184B/zh active Active
- 2014-08-12 TW TW103127571A patent/TWI517320B/zh active
- 2014-08-12 CN CN201420453275.6U patent/CN204045570U/zh not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI707463B (zh) * | 2019-08-28 | 2020-10-11 | 大陸商長江存儲科技有限責任公司 | 半導體元件及其製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104377184A (zh) | 2015-02-25 |
CN104377184B (zh) | 2018-01-09 |
EP2838114A2 (en) | 2015-02-18 |
CN204045570U (zh) | 2014-12-24 |
EP2838114A3 (en) | 2015-04-08 |
TW201507081A (zh) | 2015-02-16 |
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