TWI707463B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI707463B
TWI707463B TW108136316A TW108136316A TWI707463B TW I707463 B TWI707463 B TW I707463B TW 108136316 A TW108136316 A TW 108136316A TW 108136316 A TW108136316 A TW 108136316A TW I707463 B TWI707463 B TW I707463B
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substrate
temporary
semiconductor structure
insulating layer
layer
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TW108136316A
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TW202109852A (zh
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陳赫
子群 華
術 伍
王永慶
肖亮
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大陸商長江存儲科技有限責任公司
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Abstract

提供了一種半導體元件及其製造方法。半導體元件包括半導體結構和輸入/輸出銲墊。半導體結構包括第一基底和導電層，其中，第一基底具有彼此相對的第一表面和第二表面，導電層設置在第一基底的第一表面上，並且導電層包括一個或複數個第一導線。半導體結構具有穿過第一基底並且暴露出一個或複數個第一導線的凹陷，並且輸入/輸出銲墊設置在一個或複數個第一導線上並且在凹陷中。

Description

半導體元件及其製造方法
本發明有關於一種半導體元件及其製造方法。
透過改進製程技術、電路設計、程式設計演算法和製造製程使平面儲存單元縮小到了更小的尺寸。但是，隨著儲存單元的特徵尺寸接近下限，平面製程和製造技術變得更加困難，而且成本更加高昂。因此，針對平面儲存單元的儲存密度接近上限。
三維(3D)儲存架構能夠解決平面儲存單元中的密度限制。3D儲存架構包括儲存陣列以及用於控制去往和來自儲存陣列元件的訊號的周邊元件。 參考第1圖，其示出了常規3D記憶體裝置的輸入/輸出(I/O)銲墊(pad)結構。 在常規3D記憶體裝置的I/O銲墊結構10中，用於形成儲存陣列元件14的基底12可以被蝕穿，以形成用於將在基底12下方的儲存陣列元件14電連接到基底12上的I/O銲墊16的通孔(through hole)12h。為了形成I/O銲墊結構10，絕緣層18被進一步形成在基底12的與儲存陣列元件14相反的表面12a上，使得形成於絕緣層18上的I/O銲墊16能夠與具有形成於其中的一些元件(例如，摻雜區)的基底12絕緣。此外，通孔12h被形成為透過絕緣層18和基底12，並且在每個通孔12h中形成貫穿矽接觸(TSC)20和襯墊(liner)層22，其中，襯墊層22位於TSC 20和基底12之間，用於使它們相互絕緣。TSC 20穿透基底12並且將I/O銲墊16電連接到 儲存陣列元件14的形成於基底12的與表面12a相反的另一表面12b上的貫穿陣列接觸14c。鈍化層(passivation layer)24形成於I/O銲墊16上，並且具有暴露出I/O銲墊16的開口24a。
然而，下文的描述中的一些缺陷仍然存在於常規I/O銲墊結構10中。 第一，在I/O銲墊16和基底12之間生成的寄生電容將強烈地影響3D記憶體裝置的操作速度或者用於儲存或讀取3D記憶體裝置中的資料的速度，並且因此，為了減小所述影響，可以增加絕緣層18的厚度，以減小寄生電容，但是寄生電容還存在於TSC 20和基底12之間。第二，在絕緣層18的厚度被增加到例如大於1.4微米時，增加了穿過絕緣層18和基底12的每個通孔12h的深寬比，由此顯著地放大了製程難度。第三，由於絕緣層18的增加的厚度，需要更加先進的技術，諸如，用於形成具有穿過基底12的更大深寬比的通孔12h的機器、用於將鎢膠填充到具有更大深寬比的通孔12h中的機器、用於在具有更大深寬比的通孔12h中沉積襯墊層22的機器等等。因而，不能進一步減小3D記憶體裝置的成本。第三，隨著科技進步，需要增加儲存堆疊的層的數量。在這樣的情況下，在貫穿陣列接觸14c中的兩個貫穿陣列接觸之間的空間變得更小，使得每一個通孔12h的開口將更小，並且在TSC 20和基底12之間的空間被減小，由此增加了寄生電容，並且使3D記憶體裝置的操作速度變慢。出於此原因，不同技術代不能連續地共用相同的架構。第四，由於每一個通孔12h的開口受到在貫穿陣列接觸14c中的兩個貫穿陣列接觸之間的空間的限制，所以每一個通孔12h的開口較小並且受限，使得由製程誤差產生的通孔12h的較小的偏差可能引起貫穿陣列接觸14c與I/O銲墊16之間的開路或在儲存陣列元件14中的電流洩露。
在本發明中描述了半導體元件及其製造方法的實施例。
根據本發明的實施例，公開了一種半導體元件。半導體元件包括第一半導體結構和輸入/輸出銲墊。第一半導體結構包括第一基底和導電層，其中，第一基底具有彼此相對的第一表面和第二表面，導電層設置在第一基底的第一表面上，並且導電層包括一個或複數個第一導線。輸入/輸出銲墊設置在一個或複數個第一導線上。第一半導體結構具有穿過第一基底並且暴露出一個或複數個第一導線的凹陷，並且輸入/輸出銲墊設置在凹陷中。
在一些實施例中，半導體元件還包括設置在第一基底的第二表面上的第一絕緣層，並且第一絕緣層具有對應於凹陷的開口。
在一些實施例中，第一半導體結構還包括在第一基底的第一表面和導電層之間的第二絕緣層，其中，凹陷穿過第二絕緣層。
在一些實施例中，輸入/輸出銲墊的厚度小於第二絕緣層的厚度。
在一些實施例中，第一半導體結構還包括在第一基底上的周邊元件。
在一些實施例中，導電層還包括電連接到一個或複數個周邊元件的至少兩個第二導線。
在一些實施例中，輸入/輸出銲墊直接接觸一個或複數個第一導線。
在一些實施例中，一個或複數個第一導線的寬度大於凹陷的底部的寬度。
在一些實施例中，半導體元件還包括鍵合到第一半導體結構的第二半導體結構。
在一些實施例中，第二半導體結構包括第二基底和複數個NAND串，並且NAND串設置在導電層和第二基底之間。
在一些實施例中，第一半導體結構還包括在第一基底上的周邊元件，並且NAND串中的一個NAND串電連接到一個或複數個周邊元件。
根據本發明的實施例，公開了一種半導體元件的製造方法，並且所 述半導體元件的製造方法包括：提供暫時性半導體結構，其中，暫時性半導體結構包括暫時性基底和導電層，暫時性基底具有第一表面，導體層被設置在暫時性基底的第一表面上，並且導電層包括一個或複數個第一導線；在暫時性半導體結構中形成凹陷，以形成第一半導體結構和第一基底，其中，凹陷穿過第一基底並且暴露出一個或複數個第一導線；以及在凹陷中並且在一個或複數個第一導線上形成輸入/輸出銲墊。
在一些實施例中，製造方法還包括將暫時性基底的與第一表面相對的表面變薄，以在提供暫時性半導體結構和形成凹陷之間形成第二表面。
在一些實施例中，製造方法還包括在提供暫時性半導體結構和形成凹陷之間，在暫時性基底上形成第一絕緣層，其中，第一絕緣層具有暴露出暫時性基底的開口。
在一些實施例中，暫時性半導體結構還包括在暫時性基底的第一表面和導電層之間的暫時性絕緣層，並且形成凹陷包括將暫時性絕緣層圖案化為形成第二絕緣層。
在一些實施例中，形成輸入/輸出銲墊包括：在第一絕緣層、凹陷的側壁以及一個或複數個第一導線上沉積導電材料層；以及去除導電材料層的在第一絕緣層和凹陷的側壁上的部分。
在一些實施例中，輸入/輸出銲墊是直接形成於一個或複數個第一導線上的。
在一些實施例中，提供第一半導體結構包括提供暫時性半導體結構，提供暫時性半導體結構包括提供鍵合到暫時性半導體結構的第二半導體結構。
本領域技術人員根據所述描述、申請專利範圍和本公開內容的圖式 能夠理解本公開內容的其他方面。
對於本領域普通技術人員而言，在閱讀了下文對在各圖式和繪畫中示出的較佳實施例的詳細描述之後，本發明的這些和其他目標將無疑將變得顯而易見。
1、2:半導體元件
10:輸入/輸出銲墊結構
102:第一半導體結構
102R:凹陷
16、104:輸入/輸出銲墊
104m:導電材料層
106:周邊元件
106a、242:摻雜區
106b:閘極結構
108:周邊互連層
110:第一基底
110a:第一表面
110b:第二表面
112、112a、112b、248a、248b:導電層
112T1:第一導線
112T2:第二導線
232、238、250a、250b:介電質層
18、114a、114b、114c、118:絕緣層
116、116a、116b、246a、246b:接觸層
12:基底
12a、12b:表面
12h:通孔
14、228:儲存陣列元件
14c:貫穿陣列接觸
20:貫穿矽接觸
22:襯墊層
222:NAND串
224:第二半導體結構
226:第二基底
230:導體層
234:源極接觸
236:字元線接觸
24、120:鈍化層
154、240:隔離區
244:陣列互連層
24a、110P、114P、118P、120P:開口
252:鍵合介面
302:暫時性半導體結構
308:暫時性周邊互連層
310:暫時性基底
310b:第三表面
314a:暫時性絕緣層
DR:元件區
PR:銲墊區
S12~S20:步驟
W1、W2:寬度
T1、T2:厚度
X、Y:方向
被併入本文並且形成說明書的部分的圖式示出了本發明的實施例並且與說明書一起進一步用以解釋本發明的原理，並且使相關領域的技術人員能夠做出和使用本發明。
第1圖示出了常規3D記憶體裝置的輸入/輸出銲墊結構。
第2圖示意性地示出了根據本發明的第一實施例的示例性半導體元件的截面圖。
第3圖示意性地示出了根據本發明的第一實施例的示例的半導體元件的截面圖。
第4圖是根據本發明的第一實施例的半導體元件的示例性製造方法的流程圖。
第5圖到第8圖示意性地示出了半導體元件的示例性製造步驟。
第9圖示意性地示出了根據本發明的第二實施例的示例性半導體元件。
雖然討論了特定的配置和佈置，但應理解，這可以僅為了說明性目的而完成。相關領域中的技術人員將認識到：在不偏離本發明的精神和範圍的情況下，其它配置和佈置可以被使用。對相關領域中的技術人員將顯而易見的是，本發明也可以在各種其它應用中被使用。
注意，在本說明書中對“一個實施例”、“實施例”、“示例實施例”、“一些實施例”等的提及指示所描述的實施例可以包括特定特徵、結構或特性，但每個實施例可能不一定包括特定特徵、結構或特性。此外，這樣的短語不一定指相同的實施例。此外，當結合實施例描述特定特徵、結構或特性時，不管是否被明確描述，在相關領域中的技術人員的知識內會結合其它實施例來影響這樣的特徵、結構或特性。
通常，可以至少部分地從在上下文中的用法來理解術語。例如，至少部分地根據上下文，如在本文使用的術語“一個或複數個”可以用於在單數意義上描述任何特徵、結構或特性或可以用於在複數意義上描述特徵、結構或特性的組合。類似地，至少部分地根據上下文，術語例如“一(a)”、“一個(an)”和“所述(the)”再次可以被理解為傳達單數用法或傳達複數用法。
應容易理解，在本發明中的“在……上(on)”、“在……上面(above)”和“在……之上(over)”的含義應以最廣泛的方式被解釋，使得“在……上”不僅意指“直接在某物上”，而且還包括“在某物上”，在其之間有中間特徵或層的含義，以及“在……上面”或“在……之上”不僅意指“在某物上面”或“在某物之上”的含義，而且還可以包括其“在某物上面”或“在某物之上”，在其之間沒有中間特徵或層(即，直接在某物上)的含義。
除了在圖式中描繪的定向以外，空間相對術語意欲還包括在使用或操作中的元件的不同定向。裝置可以以另外方式被定向(旋轉90度或在其它定向處)，並且在本文使用的空間相對描述符可以相應地同樣被解釋。
如在整個本申請中所用的那樣，以允許的意義(例如，意味著具有可能性)而非強制的意義(例如，意味著必須)使用詞語“可以”。詞語“包括(include)”、“包含(including)”、以及“含有(includes)”指示開放的關係，並且因此意味著包括但不限於。類似地，詞語“具有(have)”、“有 (having)”、以及“帶有(has)”也指示開放的關係，並且因此意味著具有但不限於。本文中採用的詞語“第一”、“第二”、“第三”等是指區分不同要素的標籤，並且可以不必具有根據其數值指示的排序含義。
在本發明當中，可以對下述說明中描述的不同實施例中的不同技術特徵進行合併、替代以及相互混合，以構成另一實施例。
參考第2圖，其示意性地示出了根據本發明的第一實施例的示例性半導體元件的截面圖。如第2圖中所示，在本實施例中提供的半導體元件1包括第一半導體結構102和輸入/輸出(I/O)銲墊104，其中，第一半導體結構102具有用於設置I/O銲墊104的凹陷102R，所述I/O銲墊104電連接到外部電路或元件，以在半導體元件1和外部電路或元件之間傳遞電信號。在第2圖中示出了一個I/O銲墊104，但是本發明的I/O銲墊104的數量不限於此，並且可以有複數個。在本實施例中，第一半導體結構102包括第一基底110以及一個或複數個導電層112，其中，第一基底110具有彼此相對的第一表面110a和第二表面110b，並且導電層112設置在第一基底110的第一表面110a上。導電層112可以包括被凹陷102R暴露出的一個或複數個第一導線112T1，並且I/O銲墊104設置在第一導線112T1上並且與第一導線112T1電連接。透過將I/O銲墊104設置到凹陷102R內，能夠減小在I/O銲墊104和第一基底110之間生成的寄生電容。第一半導體結構102可以例如是周邊元件結構，所以第一半導體結構102可以包括第一基底110和在第一基底110的第一表面110a上的周邊互連層108，並且導電層112被包括在周邊互連層108中。第一半導體結構102可以進一步包括在第一基底110的第一表面110a上並且在周邊互連層108和第一基底110之間的周邊元件106。第一基底110例如可以包括矽(例如，單晶矽)、矽鍺(SiGe)、砷化鎵(GaAs)、鍺(Ge)、絕緣體上矽(SOI)或任何其他適當材料。導電層112可以例如包括導體材料，所述導體材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。
應當指出，在第2圖中增加了方向X和Y，以進一步示出半導體元件1中的部件的空間關係。第一基底110包括沿方向X(橫向或寬度方向)橫向延伸的兩個橫向表面(例如，第一表面110a和第二表面110b)。如本文所用，一個部件(例如，層或元件)在半導體元件的另一部件(例如，層或元件)“上”、“以上”或“之下”是在另一方向Y(垂直方向或厚度方向)上相對於半導體元件的基底(例如，第一基底110)來確定的。貫穿本公開內容應用相同的概念來描述空間關係。
在本實施例中，第一基底110可以具有元件區DR和銲墊區PR。元件區DR用於形成周邊元件106，以及銲墊區PR用於形成凹陷102R和I/O銲墊104，使得周邊元件106不因凹陷102R和I/O銲墊104的形成而受到影響或損害。因此，第一基底110可以被蝕穿，以具有對應於凹陷102R的開口110P。
周邊元件106可以包括一個或複數個電晶體。在第2圖所示的實施例中，示出了一個電晶體作為示例，但不限於此。周邊元件106可以例如包括摻雜區106a和閘極結構106b。摻雜區106a設置在第一基底110中。閘極結構106b可以被設置在第一基底110和周邊互連層108之間。
周邊互連層108包括導電層112以及一個或複數個絕緣層，使得周邊元件106可以電連接至I/O銲墊104或其他元件，例如，下文的儲存陣列元件。在第2圖所示的實施例中，示出了一個導電層112和兩個絕緣層114a、114b作為示例，但不限於此。絕緣層114a和絕緣層114b中的每個絕緣層可以包括介電質材料，諸如氧化矽、氮化矽、氮氧化矽、任何其他適當的介電質材料或者它們的任何組合。導電層112設置在第一基底110的第一表面110a上並且在絕緣層114a和絕緣層114b之間，並且絕緣層114a設置在導電層112和第一基底110之間，使得導電層112的一些部分可以透過絕緣層114a與第一基底110電隔離。
在本實施例中，凹陷102R進一步穿過在第一基底110和導電層112之 間的絕緣層114a，並且暴露出第一導線112T1，使得絕緣層114a具有對應於凹陷102R的開口114P。例如，開口110P、開口114P、被暴露的第一導線112T1和絕緣層114b的部分可以形成凹陷102R。
此外，半導體元件1可以進一步包括設置在第一基底110的第二表面110b上的另一絕緣層118，其中，絕緣層118具有對應於凹陷102R的開口118P。 換言之，開口118P暴露出凹陷102R。因此，I/O銲墊104可以透過開口118P和凹陷102R形成在導體層112上，並且透過被設置在凹陷102R中來電連接到被暴露的第一導線112T1。例如，I/O銲墊104可以直接接觸第一導線112T1。在第2圖所示的實施例中，相互隔開的被暴露的第一導線112T1的數量是複數個，並且I/O銲墊104電連接至多個第一導線112T1，但不限於此。在一些實施例中，被暴露的第一導線112T1的數量可以為一個，並且第一導線112T1的寬度可以與凹陷102R的底部的寬度相同或不同。較佳地，第一導線112T1的寬度可以大於凹陷102R的底部的寬度，使得第一導線112T1可以在形成凹陷102R時起到蝕刻停止層的作用。 在一些實施例中，導電層112可以是周邊互連層108內的導電層中的最接近第一基底110的一個導電層，但不限於此。在一些實施例中，導電層112可以進一步包括電連接到周邊元件106至少兩個第二導線112T2。在一些實施例中，被凹陷102R穿過的絕緣層的數量可以是複數個。在一些實施例中，I/O銲墊104的厚度T1可以小於絕緣層114a的厚度T2，使得在I/O銲墊104和第一基底110之間的間隔可以被增大，以減小其間的寄生電容。
在一些實施例中，周邊互連層108可以進一步包括至少一個接觸層116，用於將周邊元件106電連接到導電層112。例如，接觸層116包括穿過絕緣層114a的接觸插塞。在一些實施例中，周邊互連層108可以進一步包括在導電層112之下的接觸層，但不限於此。導電層116可以例如包括導體材料，所述導體材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。
在一些實施例中，半導體元件1可以進一步包括用於保護絕緣層118、第一半導體結構102和I/O銲墊104的鈍化層120。鈍化層120具有暴露出I/O銲墊104的開口120P，使得I/O銲墊104能夠透過開口120P電連接至外部電路或元件。
半導體元件可以例如是記憶體裝置或者任何其他適當元件。參考第3圖，其示意性地示出了根據本發明的第一實施例的示例的半導體元件的截面圖。如第3圖所示，在本示例中提供的半導體元件1是NAND快閃記憶體裝置，但不限於此。NAND快閃記憶體裝置中的儲存單元是以在第一基底110之下垂直延伸的複數個NAND串222的形式提供的。在本示例中，半導體元件1可以進一步包括第二半導體結構224，以及第二半導體結構224包括第二基底226和儲存陣列元件228。第二基底226被設置為與第一基底110的第一表面110a相對，並且儲存陣列元件228形成在第二基底226上並且在第一基底110和第二基底226之間。第二基底226例如可以包括矽(例如，單晶矽)、矽鍺(SiGe)、砷化鎵(GaAs)、鍺(Ge)、絕緣體上矽(SOI)或任何其他適當材料。
儲存陣列元件228可以包括設置在導電層112和第二基底226之間的NAND串222。NAND串222垂直地延伸穿過多個導體層230和複數個介電質層232。每個導體層230與介電質層232中對應的一個介電質層可以形成一對。每個導體層230可以在兩側與兩個介電質層232相鄰，並且每一介電質層232可以在兩側與兩個導體層230相鄰。導體層230可以包括導體材料，諸如鎢(W)、鈷(Co)、銅(Cu)、鋁(Al)、摻雜矽、矽化物、任何其他適當導體材料或者它們的任何組合。介電質層232可以包括介電質材料，諸如氧化矽、氮化矽、氮氧化矽、任何其他適當的介電質材料或者它們的任何組合。此外，儲存陣列元件228還可以包括源極接觸234、字元線接觸236和介電質層238，其中，源極接觸234垂直地延伸穿過導體層230和介電質層232，字元線接觸236在介電質層238內垂直地延 伸，並且每個字元線接觸236與對應的導體層230接觸，以單獨地定址儲存陣列元件228的對應字元線。應當指出，第2圖中所示的儲存陣列元件228是用作示例，並且本領域技術人員瞭解儲存陣列元件228可以具有其他結構，所以在本文中將不再詳述儲存陣列元件228的結構或其變型。在一些實施例中，隔離區240和摻雜區242可以形成在第二基底226中。
如第2圖中所示，半導體元件1可以進一步包括陣列互連層244，用於將儲存陣列元件228電連接到周邊元件106和/或I/O銲墊104。例如，NAND串222中的一個NAND串通過陣列互連層244和周邊互連層108來電連接到周邊元件106。陣列互連層244設置在儲存陣列元件228上並且與周邊互連層108接觸。陣列互連層244可以包括一個或複數個接觸層(例如，接觸層246a、246b)、一個或複數個導電層(例如，導電層248a、248b)以及一個或複數個介電質層(例如，介電質層250a、250b)。接觸層246a、246b以及導電層248a、248b可以包括導體材料，所述導體材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。 介電質層250a、250b可以包括介電質材料，所述介電質材料包括但不限於氧化矽、氮化矽、低k介電質或其任何組合。
在本示例中，周邊互連層108可以包括複數個導電層112(例如，導電層112a、112b)、複數個接觸層116(例如，接觸層116a、116b)以及複數個介電質層(例如，絕緣層114a、114b、114c)。在一些實施例中，接觸層116的數量和介電質層的數量不限於複數個，並且可以基於導電層112的數量來調整。 鍵合介面252可以形成在周邊互連層108的絕緣層114c與陣列互連層244的介電質層250a之間。鍵合介面252還可以形成在陣列互連層244的導體層248a與周邊互連層108的導體層112b之間。換言之，第一半導體結構102在鍵合介面252處鍵合到第二半導體結構224。在一些實施例中，第一半導體結構102還可以包括形成在第一基底110中的用於將不同部件隔開的隔離區154。
如上文所提及的，與第1圖所示的常規記憶體裝置相比，半導體元件1可以具有下述優點。第一，由於I/O銲墊104直接設置在凹陷102R中，所以I/O銲墊104不存在於第一基底110的開口110P中。因此，能夠減小在I/O銲墊104和第一基底110之間生成的寄生電容，由此改善半導體元件1的操作速度或者用於儲存或讀取半導體元件1中的資料的速度。第二，不需要增加絕緣層118的厚度來減小寄生電容，使得能夠降低用於形成絕緣層118的成本，並且不需要較高的深寬比。因而，對I/O銲墊104的形成不受穿過絕緣層和基底的通孔的較高的深寬比限制，並且在增加NAND串222的密度時能夠使用於形成I/O銲墊104的製程難度變得容易。第三，由於凹陷102R形成在包括周邊元件106的第一半導體結構108上，因此凹陷102R的寬度(例如，處於70μm到80μm的範圍內)不限於與NAND串222或TSC的寬度類似或相同，而且在微影製程中使用的曝光光線不限於具有非常小的波長。例如，用於形成凹陷102R的微影製程可以使用I線(I-line)曝光(例如，365nm)。由於此原因，將不會發生由於製程誤差在貫穿陣列接觸與I/O銲墊之間的開路或者在半導體元件中的電流洩漏。出於此原因，不需要更加先進的技術，諸如用於形成具有穿過基底的更大深寬比的通孔的機器、用於將鎢膠填充到具有更大深寬比的通孔中的機器、用於在具有更大深寬比的通孔中沉積襯墊層的機器等等。第四，在增加導體層230和介電質層232的數量以升級儲存容量時，不同的技術代仍然能夠容易地共用相同的半導體元件1。
第4圖是根據本發明的第一實施例的半導體元件的示例性製造方法的流程圖。第5圖到第8圖以及第2圖示意性地示出了半導體元件的示例性製造步驟，其中為了清楚起見，第6圖到第8圖忽略了第一半導體結構和第二半導體結構的部分，但是本發明不限於此。應當指出，第4圖中所示的步驟不是窮舉的，並且也可以在所例示的步驟中的任何步驟之前、之後或者之間進行其他步驟。 在本實施例中提供的半導體元件1的製造方法包括以下步驟S12~S20。如第4圖和 第5圖所示，進行步驟S12，以提供暫時性半導體結構302。暫時性半導體結構302包括暫時性基底310、暫時性絕緣層314a以及一個或複數個導電層112。暫時性半導體結構302與第一半導體結構102的不同之處在於：半導體結構302的暫時性基底310在步驟S12中未被變薄和蝕穿，所以暫時性半導體結構302不具有凹陷102R，並且暫時性基底310不具有開口110P。在一些實施例中，暫時性基底310的厚度在步驟S12中可以大於第一基底110的厚度。在本實施例中，暫時性基底310具有彼此相對的第一表面110a和第三表面310b，暫時性周邊互連層308和周邊元件106形成於暫時性基底310的第一表面110a上。在步驟S12中，暫時性周邊互連層308與上文提及的周邊互連層108的不同之處在於：暫時性絕緣層314a未被蝕穿，以致不具有開口114P。在本實施例中，周邊元件106與上文提及的類似或相同，並且將不再對其做多餘的描述。
在步驟S12中，還提供了第二半導體結構224，並且所述第二半導體結構224被鍵合到暫時性半導體結構302。由於第二半導體結構224與上文提及的相同，所以將不重複地對第二半導體結構224做詳細描述。
如第4圖、第5圖和第6圖中所示，可選擇性地進行步驟S14以將暫時性基底310的第三表面310b變薄，以形成第二表面110b。例如，將第一基底310變薄可以包括進行化學機械平坦化(CMP)製程或者任何其他適當製程。
在將暫時性基底310變薄之後，進行步驟S16，以在經變薄的暫時性基底310的第二表面110b上形成絕緣層118，其中，絕緣層118具有暴露出暫時性基底310的第二表面110b的開口118P。例如，形成絕緣層118可以包括沉積絕緣材料並且將絕緣材料層圖案化。對絕緣材料層的沉積可以例如採用化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、原子層沉積(ALD)製程或者任何其他適當的沉積製程。對絕緣材料層的圖案化可以例如採用使用光遮罩(例如I線遮罩)的微影製程。在一些實施例中，可以在提供暫時性半導體結構302 之後直接進行步驟S16。
在形成絕緣層118之後，可以進行步驟S18，以在暫時性半導體結構302的銲墊區PR中形成凹陷102R。具體而言，形成凹陷102R可以包括：將被暴露的暫時性基底310圖案化，以在暫時性基底310中形成開口110P，由此形成前述的具有開口110P的第一基底110。對暫時性基底310的圖案化可以例如採用蝕刻製程，所述蝕刻製程使用絕緣層118作為遮罩。形成凹陷102R還可以包括將被開口110P暴露出的暫時性絕緣層314a的一部分圖案化，以在形成開口110P之後形成開口114P並且暴露出第一導線112T1，由此形成具有開口114P的前述絕緣層114a。相應地，能夠形成上文提及的第一半導體結構102，並且能夠形成上文提及的周邊互連層108。對暫時性絕緣層314a的圖案化可以例如採用相對於絕緣層118、第一基底110和導電層112對暫時性絕緣層314a進行選擇性蝕刻的蝕刻製程。在一些實施例中，周邊互連層308還可以包括在導電層112和暫時性絕緣層314a之間的蝕刻停止層，使得對暫時性絕緣層314a的蝕刻能夠停止在蝕刻停止層處，並且能夠保護在第一跡線112T1之間的絕緣層114b。在一些實施例中，蝕刻製程可以相對於絕緣層114b具有對暫時性絕緣層314a的高蝕刻選擇性。
如第4圖和第8圖所示，可以進行步驟S20，以在凹陷102R中並且在第一導線112T1上形成I/O銲墊104。具體地，如第7圖所示，形成I/O銲墊104包括：在絕緣層118、凹陷102R的側壁以及第一導線112T1上沉積導電材料層104m。換言之，導電材料層104m從絕緣層118的頂表面延伸到開口118P的側壁、開口110P的側壁、開口114P的側壁和I/O銲墊104上。對導電材料層104m的沉積可以使用CVD製程、PVD製程、ALD製程或者任何其他適當沉積製程。隨後，如第8圖中所示，形成I/O銲墊104還包括將導電材料層104m圖案化，以去除導電材料層104m的在絕緣層118上和凹陷102R的側壁上的部分。
如第2圖所示，在形成I/O銲墊104之後，還可以將鈍化層120形成到 絕緣層118、開口110P的側壁、開口114P的側壁和I/O銲墊104上，並且然後，鈍化層120被圖案化為具有暴露出I/O銲墊104的開口120P。相應地，形成本實施例的半導體元件1。
下文的描述將詳細闡述本公開內容的不同實施例。為了簡化描述，採用等同的符號標記下述實施例中的每個實施例的相同部件。為了使在實施例之間的差異更易於理解，下文的描述將詳細闡述在不同實施例之間的相異之處，並且將不重複地描述等同的特徵。
參考第9圖，其示意性地示出了根據本發明的第二實施例的示例性半導體元件。如第9圖中所示，本實施例中提供的半導體元件2與先前實施例的不同之處在於：第一導線112T1的寬度W1可以大於凹陷102R的底部的寬度W2，因此第一導線112T1可以在形成凹陷102R時起到蝕刻停止層的作用。
透過使用所公開的半導體元件及其製造方法，能夠減小在I/O銲墊和第一基底之間生成的寄生電容，由此改善記憶體裝置的操作速度或者用於儲存或讀取在記憶體裝置中的資料的速度。此外，不需要增加第一基底上的絕緣層的厚度來減小寄生電容，使得能夠降低用於形成絕緣層的成本，並且不需要較高的深寬比。因而，對I/O銲墊的形成不受較高的深寬比的限制，並且能夠在增加NAND串的密度時使用於形成I/O銲墊的製程難度變得容易。由於凹陷形成在包括周邊元件的第一半導體結構上，所以第一半導體結構的凹陷的寬度不限於與NAND串或TSC的寬度類似或相同，在微影製程中使用的曝光光線能夠具有較大波長。此外，將不會發生由於製程誤差在貫穿陣列接觸與I/O銲墊之間的開路或者在半導體元件中的電流洩漏，並且不需要更加先進的技術。此外，在增加導體層和介電質層的數量以升級儲存容量時，不同的技術代仍然能夠容易地使用相同的架構。
特定實施例的前述描述將這樣充分地揭露其他人可以透過將在本領 域的技能範圍內的知識應用於各種應用(例如特定的實施例)，來容易修改和/或適應的本發明的一般性質，而沒有過度的實驗並且不偏離本發明的一般概念。因此，基於本發明和在本文提出的指導，這樣的適應和修改旨在在所公開的實施例的等效形式的含義和範圍內。應理解，本文的短語或術語是為了描述而不是限制的目的，使得本說明書的術語或短語應由技術人員按照本發明和指導來解釋。
上面借助於用於說明特定功能的實現方式及其關係的功能構建塊，描述了本發明的實施例。在本文為了描述的方便，這些功能構建塊的邊界已經被任意限定。可以定義替代的邊界，只要特定功能及其關係被適當地進行。
發明內容和摘要部分可以闡述如發明人所設想的本發明的一個或複數個但不是全部示例性實施例，並且因此不旨在以任何方式限制本發明和所附申請專利範圍。
本領域的技術人員將容易地發現在遵循本發明的教導的同時可以對所述元件和方法做出很多修改和變更。相應地，應當將上文的公開內容視為僅由所附申請專利範圍的公認範圍來限定。
1:半導體元件
102:第一半導體結構
102R:凹陷
104:輸入/輸出銲墊
106:周邊元件
106a:摻雜區
106b:閘極結構
108:周邊互連層
110:第一基底
110a:第一表面
110b:第二表面
112:導電層
112T1:第一導線
112T2:第二導線
114a、114b、118:絕緣層
116:接觸層
120:鈍化層
110P、114P、118P、120P:開口
DR:元件區
PR:銲墊區
T1、T2:厚度
X、Y:方向

Claims (16)

  1. 一種半導體元件，包括：第一半導體結構，其包括第一基底、導電層和絕緣層，其中，所述第一基底具有彼此相對的第一表面和第二表面，所述導電層設置在所述第一基底的所述第一表面上，所述導電層包括一個或複數個第一導線，且所述絕緣層位於所述第一基底的所述第一表面和所述導電層之間；以及設置在所述一個或複數個第一導線上的輸入/輸出銲墊；其中，所述第一半導體結構具有穿過所述第一基底與所述絕緣層並且暴露出所述一個或複數個第一導線的凹陷，所述輸入/輸出銲墊被設置在所述凹陷中，且所述輸入/輸出銲墊的厚度小於所述絕緣層的厚度。
  2. 根據申請專利範圍第1項所述的半導體元件，還包括設置在所述第一基底的所述第二表面上的另一絕緣層，其中，所述另一絕緣層具有對應於所述凹陷的開口。
  3. 根據申請專利範圍第1項所述的半導體元件，其中，所述第一半導體結構還包括在所述第一基底上的周邊元件。
  4. 根據申請專利範圍第3項所述的半導體元件，其中，所述導電層還包括電連接到所述周邊元件的至少兩個第二導線。
  5. 根據申請專利範圍第1項所述的半導體元件，其中，所述輸入/輸出銲墊直接接觸所述一個或複數個第一導線。
  6. 根據申請專利範圍第1項所述的半導體元件，其中，所述一個或複數個第一導線的寬度大於所述凹陷的底部的寬度。
  7. 根據申請專利範圍第1項所述的半導體元件，還包括鍵合到所述第一半導體結構的第二半導體結構。
  8. 根據申請專利範圍第7項所述的半導體元件，其中，所述第二半導體結構包括第二基底和複數個NAND串，並且所述NAND串設置在所述導電層和所述第二基底之間。
  9. 根據申請專利範圍第8項所述的半導體元件，其中，所述第一半導體結構還包括在所述第一基底上的周邊元件，並且NAND串中的一個NAND串電連接到所述周邊元件。
  10. 一種半導體元件的製造方法，包括：提供暫時性半導體結構，其中，所述暫時性半導體結構包括暫時性基底、導電層和暫時性絕緣層，所述暫時性基底具有第一表面，所述導體層被設置在所述暫時性基底的所述第一表面上，所述導電層包括一個或複數個第一導線，且暫時性絕緣層位於所述暫時性基底的所述第一表面和所述導電層之間；在所述暫時性半導體結構中形成凹陷，以形成第一半導體結構和第一基底，其中，所述凹陷穿過所述第一基底並且暴露出所述一個或複數個第一導線，且形成所述凹陷包括將所述暫時性絕緣層圖案化，以形成絕緣層；以及在所述凹陷中並且在所述一個或複數個第一導線上形成輸入/輸出銲墊，其 中所述輸入/輸出銲墊的厚度小於所述絕緣層的厚度。
  11. 根據申請專利範圍第10項所述的半導體元件的製造方法，還包括將所述暫時性基底的與所述第一表面相對的表面變薄，以在提供所述暫時性半導體結構和形成所述凹陷之間形成第二表面。
  12. 根據申請專利範圍第10項所述的半導體元件的製造方法，還包括在提供所述暫時性半導體結構和形成所述凹陷之間，在所述暫時性基底上形成另一絕緣層，其中，所述另一絕緣層具有暴露出所述暫時性基底的開口。
  13. 根據申請專利範圍第12項所述的半導體元件的製造方法，其中，形成所述輸入/輸出銲墊包括：在所述另一絕緣層、所述凹陷的側壁以及所述一個或複數個第一導線上沉積導電材料層；以及去除所述導電材料層在所述另一絕緣層和所述凹陷的側壁上的部分。
  14. 根據申請專利範圍第13項所述的半導體元件的製造方法，其中，所述輸入/輸出銲墊是直接形成於所述一個或複數個第一導線上。
  15. 根據申請專利範圍第10項所述的半導體元件的製造方法，其中，提供所述暫時性半導體結構包括提供鍵合到所述暫時性半導體結構的第二半導體結構。
  16. 根據申請專利範圍第15項所述的半導體元件的製造方法，其中，所述第二半導體結構包括第二基底和複數個NAND串，並且所述NAND串被設置在所述導電層和所述第二基底之間。
TW108136316A 2019-08-28 2019-10-08 半導體元件及其製造方法 TWI707463B (zh)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200414483A (en) * 2003-01-15 2004-08-01 Fujitsu Ltd Memiconductor device, three-dimensionally mounted semiconductor devices, and method of manufacturing semiconductor device
US20160005743A1 (en) * 2013-04-08 2016-01-07 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
TWI517320B (zh) * 2013-08-12 2016-01-11 精材科技股份有限公司 晶片封裝體
TWI563545B (en) * 2011-06-27 2016-12-21 Semiconductor Components Ind Method of making an insulated gate semiconductor device and structure
US20170085267A1 (en) * 2011-05-18 2017-03-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
US20170103989A1 (en) * 2015-10-07 2017-04-13 Silicon Storage Technology, Inc. Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
TWI602273B (zh) * 2013-07-31 2017-10-11 台灣積體電路製造股份有限公司 半導體裝置
TWI632656B (zh) * 2014-02-13 2018-08-11 台灣積體電路製造股份有限公司 半導體裝置及半導體裝置製造方法
TWI667744B (zh) * 2017-07-07 2019-08-01 南韓商三星電子股份有限公司 扇出型半導體封裝模組

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006093367A (ja) * 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
US7563714B2 (en) 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
JP5439901B2 (ja) * 2009-03-31 2014-03-12 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5998459B2 (ja) * 2011-11-15 2016-09-28 ローム株式会社 半導体装置およびその製造方法、電子部品
JP6012262B2 (ja) * 2012-05-31 2016-10-25 キヤノン株式会社 半導体装置の製造方法
JP2014175348A (ja) * 2013-03-06 2014-09-22 Toshiba Corp 不揮発性半導体記憶装置
US9117879B2 (en) * 2013-12-30 2015-08-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102198857B1 (ko) * 2014-01-24 2021-01-05 삼성전자 주식회사 랜딩 패드를 구비하는 반도체 소자
KR102282138B1 (ko) * 2014-12-09 2021-07-27 삼성전자주식회사 반도체 소자
US10038026B2 (en) * 2015-06-25 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for bonding improvement
US9923011B2 (en) * 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10109666B2 (en) * 2016-04-13 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for backside illuminated (BSI) image sensors
KR102597436B1 (ko) * 2016-09-07 2023-11-03 주식회사 디비하이텍 후면 조사형 이미지 센서 및 그 제조 방법
KR102373616B1 (ko) * 2017-07-06 2022-03-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN109390373B (zh) * 2017-08-08 2020-09-29 上海视欧光电科技有限公司 封装结构及其封装方法
CN107658317B (zh) * 2017-09-15 2019-01-01 长江存储科技有限责任公司 一种半导体装置及其制备方法
US10283548B1 (en) * 2017-11-08 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS sensors and methods of forming the same
US10354980B1 (en) * 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
CN109314116B (zh) * 2018-07-20 2019-10-01 长江存储科技有限责任公司 用于形成三维存储器件的方法
CN109155320B (zh) * 2018-08-16 2019-09-10 长江存储科技有限责任公司 三维存储器件的嵌入式焊盘结构及其制造方法
KR20210083328A (ko) * 2019-02-11 2021-07-06 양쯔 메모리 테크놀로지스 씨오., 엘티디. 확산 불가능한 전도성 재료로 제조된 본딩 컨택을 갖는 본딩된 반도체 구조 및 이를 형성하기 위한 방법
US11069703B2 (en) * 2019-03-04 2021-07-20 Sandisk Technologies Llc Three-dimensional device with bonded structures including a support die and methods of making the same
US10714497B1 (en) * 2019-03-04 2020-07-14 Sandisk Technologies Llc Three-dimensional device with bonded structures including a support die and methods of making the same
US10985169B2 (en) * 2019-03-04 2021-04-20 Sandisk Technologies Llc Three-dimensional device with bonded structures including a support die and methods of making the same
JP2020155487A (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体記憶装置およびその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200414483A (en) * 2003-01-15 2004-08-01 Fujitsu Ltd Memiconductor device, three-dimensionally mounted semiconductor devices, and method of manufacturing semiconductor device
US20170085267A1 (en) * 2011-05-18 2017-03-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
US20190044516A1 (en) * 2011-05-18 2019-02-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
TWI563545B (en) * 2011-06-27 2016-12-21 Semiconductor Components Ind Method of making an insulated gate semiconductor device and structure
US20160005743A1 (en) * 2013-04-08 2016-01-07 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
TWI602273B (zh) * 2013-07-31 2017-10-11 台灣積體電路製造股份有限公司 半導體裝置
TWI517320B (zh) * 2013-08-12 2016-01-11 精材科技股份有限公司 晶片封裝體
TWI632656B (zh) * 2014-02-13 2018-08-11 台灣積體電路製造股份有限公司 半導體裝置及半導體裝置製造方法
US20170103989A1 (en) * 2015-10-07 2017-04-13 Silicon Storage Technology, Inc. Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
TWI667744B (zh) * 2017-07-07 2019-08-01 南韓商三星電子股份有限公司 扇出型半導體封裝模組

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US11430775B2 (en) 2022-08-30
TW202109852A (zh) 2021-03-01
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