CN112968011A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN112968011A
CN112968011A CN202110467208.4A CN202110467208A CN112968011A CN 112968011 A CN112968011 A CN 112968011A CN 202110467208 A CN202110467208 A CN 202110467208A CN 112968011 A CN112968011 A CN 112968011A
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substrate
semiconductor structure
temporary
recess
insulating layer
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CN202110467208.4A
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CN112968011B (zh
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陈赫
华子群
伍术
王永庆
肖亮
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Abstract

提供了一种半导体器件及其制造方法。半导体器件包括半导体结构和输入/输出焊盘。半导体结构包括第一衬底和导电层，其中，第一衬底具有彼此相对的第一表面和第二表面，导电层设置在第一衬底的第一表面上，并且导电层包括一个或多个第一迹线。第一半导体结构具有穿过第一衬底并且暴露出一个或多个第一迹线的凹陷，并且输入/输出焊盘设置在一个或多个第一迹线上并且在凹陷中。

Description

半导体器件及其制造方法
本申请是申请日为2019年8月28日、申请号为201980001905.1、发明名称为“半导体器件及其制造方法”的申请的分案申请。
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
通过改进工艺技术、电路设计、编程算法和制造工艺使平面存储单元缩小到了更小的尺寸。但是，随着存储单元的特征尺寸接近下限，平面工艺和制造技术变得更加困难，而且成本更加高昂。因此，针对平面存储单元的存储密度接近上限。
三维(3D)存储架构能够解决平面存储单元中的密度限制。3D存储架构包括存储阵列以及用于控制去往和来自存储阵列器件的信号的外围器件。参考图1，其示出了常规3D存储器件的输入/输出(I/O)焊盘(pad)结构。在常规3D存储器件的I/O焊盘结构10中，用于形成存储阵列器件14的衬底12可以被蚀穿，以形成用于将在衬底12下方的存储阵列器件14电连接到衬底12上的I/O焊盘16的通孔(through hole)12h。为了形成I/O焊盘结构10，绝缘层18被进一步形成在衬底12的与存储阵列器件14相反的表面12a上，使得形成于绝缘层18上的I/O焊盘16能够与具有形成于其中的一些元件(例如，掺杂区)的衬底12绝缘。此外，通孔12h被形成为通过绝缘层18和衬底12，并且在每个通孔12h中形成贯穿硅触点(TSC)20和衬(liner)层22，其中，衬层22位于TSC 20和衬底12之间，用于使它们相互绝缘。TSC 20穿透衬底12并且将I/O焊盘16电连接到存储阵列器件14的形成于衬底12的与表面12a相反的另一表面12b上的贯穿阵列触点14c。钝化层(passivation layer)24形成于I/O焊盘16上，并且具有暴露出I/O焊盘16的开口24a。
然而，下文的描述中的一些缺陷仍然存在于常规I/O焊盘结构10中。第一，在I/O焊盘16和衬底12之间生成的寄生电容将强烈地影响3D存储器件的操作速度或者用于存储或读取3D存储器件中的数据的速度，并且因此，为了减小所述影响，可以增加绝缘层18的厚度，以减小寄生电容，但是寄生电容还存在于TSC 20和衬底12之间。第二，在绝缘层18的厚度被增加到例如大于1.4微米时，增加了穿过绝缘层18和衬底12的每个通孔12h的高宽比，由此显著地放大了工艺难度。第三，由于绝缘层18的增加的厚度，需要更加先进的技术，诸如，用于形成具有穿过衬底12的更大高宽比的通孔12h的机器、用于将钨胶填充到具有更大高宽比的通孔12h中的机器、用于在具有更大高宽比的通孔12h中沉积衬层22的机器等等。因而，不能进一步减小3D存储器件的成本。第三，利用先进技术，需要增加存储堆叠的层的数量。在这样的情况下，在贯穿阵列触点14c中的两个贯穿阵列触点之间的空间变得更小，使得每一个通孔12h的开口将更小，并且在TSC 20和衬底12之间的空间被减小，由此增加了寄生电容，并且使3D存储器件的操作速度变慢。出于该原因，不同技术代不能连续地共享相同的架构。第四，由于每一个通孔12h的开口受到在贯穿阵列触点14c中的两个贯穿阵列触点之间的空间的限制，所以每一个通孔12h的开口较小并且受限，使得由工艺误差产生的通孔12h的较小的偏差可能引起贯穿阵列触点14c与I/O焊盘16之间的开路或在存储阵列器件14中的电流泄露。
发明内容
在本发明中描述了半导体器件及其制造方法的实施例。
根据本发明的实施例，公开了一种半导体器件。半导体器件包括第一半导体结构和输入/输出焊盘。第一半导体结构包括第一衬底和导电层，其中，第一衬底具有彼此相对的第一表面和第二表面，导电层设置在第一衬底的第一表面上，并且导电层包括一个或多个第一迹线。输入/输出焊盘设置在一个或多个第一迹线上。第一半导体结构具有穿过第一衬底并且暴露出一个或多个第一迹线的凹陷，并且输入/输出焊盘设置在凹陷中。
在一些实施例中，半导体器件还包括设置在第一衬底的第二表面上的第一绝缘层，并且第一绝缘层具有对应于凹陷的开口。
在一些实施例中，第一半导体结构还包括在第一衬底的第一表面和第一导电层之间的第二绝缘层，其中，凹陷穿过第二绝缘层。
在一些实施例中，输入/输出焊盘的厚度小于第二绝缘层的厚度。
在一些实施例中，第一半导体结构还包括在第一衬底上的外围器件。
在一些实施例中，导电层还包括电连接到一个或多个外围器件的至少两个第二迹线。
在一些实施例中，输入/输出焊盘直接接触一个或多个第一迹线。
在一些实施例中，一个或多个迹线的宽度大于凹陷的底部的宽度。
在一些实施例中，半导体器件还包括键合到第一半导体结构的第二半导体结构。
在一些实施例中，第二半导体结构包括第二衬底和多个NAND串，并且NAND串设置在导电层和第二衬底之间。
在一些实施例中，第一半导体结构还包括在第一衬底上的外围器件，并且NAND串中的一个NAND串电连接到一个或多个外围器件。
根据本发明的实施例，公开了一种半导体器件的制造方法，并且所述半导体器件的制造方法包括：提供暂时性半导体结构，其中，暂时性半导体结构包括暂时性衬底和导电层，暂时性衬底具有第一表面，导体层被设置在暂时性衬底的第一表面上，并且导电层包括一个或多个第一迹线；在暂时性半导体结构中形成凹陷，以形成第一半导体结构和第一衬底，其中，凹陷穿过第一衬底并且暴露出一个或多个第一迹线；以及在凹陷中并且在一个或多个第一迹线上形成输入/输出焊盘。
在一些实施例中，制造方法还包括将暂时性衬底的与第一表面相对的表面变薄，以在提供暂时性半导体结构和形成凹陷之间形成第二表面。
在一些实施例中，制造方法还包括在提供暂时性半导体结构和形成凹陷之间，在暂时性衬底上形成第一绝缘层，其中，第一绝缘层具有暴露出暂时性衬底的开口。
在一些实施例中，暂时性半导体结构还包括在暂时性衬底的第一表面和导电层之间的暂时性绝缘层，并且形成凹陷包括将暂时性绝缘层图案化为形成第二绝缘层。
在一些实施例中，形成输入/输出焊盘包括：在第一绝缘层、凹陷的侧壁以及一个或多个第一迹线上沉积导电材料层；以及去除导电材料层的在第一绝缘层和凹陷的侧壁上的部分。
在一些实施例中，输入/输出焊盘是直接形成于一个或多个第一迹线上的。
在一些实施例中，提供第一半导体结构包括提供暂时性半导体结构，提供暂时性半导体结构包括提供键合到暂时性半导体结构的第二半导体结构。
本领域技术人员根据所述描述、权利要求和本公开内容的附图能够理解本公开内容的其他方面。
对于本领域普通技术人员而言，在阅读了下文对在各附图和绘画中示出的优选实施例的详细描述之后，本发明的这些和其他目标将无疑将变得显而易见。
附图说明
被并入本文并且形成说明书的部分的附图示出了本发明的实施例并且与说明书一起进一步用以解释本发明的原理，并且使相关领域的技术人员能够做出和使用本发明。
图1示出了常规3D存储器件的输入/输出焊盘结构。
图2示意性地示出了根据本发明的第一实施例的示例性半导体器件的截面图。
图3示意性地示出了根据本发明的第一实施例的示例的半导体器件的截面图。
图4是根据本发明的第一实施例的半导体器件的示例性制造方法的流程图。
图5到图8示意性地示出了半导体器件的示例性制造步骤。
图9示意性地示出了根据本发明的第二实施例的示例性半导体器件。
具体实施方式
虽然讨论了特定的配置和布置，但应理解，这可以仅为了说明性目的而完成。相关领域中的技术人员将认识到：在不偏离本发明的精神和范围的情况下，其它配置和布置可以被使用。对相关领域中的技术人员将显而易见的是，本发明也可以在各种其它应用中被使用。
注意，在本说明书中对“一个实施例”、“实施例”、“示例实施例”、“一些实施例”等的提及指示所描述的实施例可以包括特定特征、结构或特性，但每个实施例可能不一定包括特定特征、结构或特性。此外，这样的短语不一定指相同的实施例。此外，当结合实施例描述特定特征、结构或特性时，不管是否被明确描述，在相关领域中的技术人员的知识内会结合其它实施例来影响这样的特征、结构或特性。
通常，可以至少部分地从在上下文中的用法来理解术语。例如，至少部分地根据上下文，如在本文使用的术语“一个或多个”可以用于在单数意义上描述任何特征、结构或特性或可以用于在复数意义上描述特征、结构或特性的组合。类似地，至少部分地根据上下文，术语例如“一(a)”、“一个(an)”和“该(the)”再次可以被理解为传达单数用法或传达复数用法。
应容易理解，在本发明中的“在……上(on)”、“在……上面(above)”和“在……之上(over)”的含义应以最广泛的方式被解释，使得“在……上”不仅意指“直接在某物上”，而且还包括“在某物上”，在其之间有中间特征或层的含义，以及“在……上面”或“在……之上”不仅意指“在某物上面”或“在某物之上”的含义，而且还可以包括其“在某物上面”或“在某物之上”，在其之间没有中间特征或层(即，直接在某物上)的含义。
除了在附图中描绘的定向以外，空间相对术语意欲还包括在使用或操作中的器件的不同定向。装置可以以另外方式被定向(旋转90度或在其它定向处)，并且在本文使用的空间相对描述符可以相应地同样被解释。
如在整个本申请中所用的那样，以允许的意义(例如，意味着具有可能性)而非强制的意义(例如，意味着必须)使用词语“可以”。词语“包括(include)”、“包含(including)”、以及“含有(includes)”指示开放的关系，并且因此意味着包括但不限于。类似地，词语“具有(have)”、“有(having)”、以及“带有(has)”也指示开放的关系，并且因此意味着具有但不限于。本文中采用的词语“第一”、“第二”、“第三”等是指区分不同要素的标签，并且可以不必具有根据其数值指示的排序含义。
在本发明当中，可以对下述说明中描述的不同实施例中的不同技术特征进行合并、替代以及相互混合，以构成另一实施例。
参考图2，其示意性地示出了根据本发明的第一实施例的示例性半导体器件的截面图。如图2中所示，在该实施例中提供的半导体器件1包括第一半导体结构102和输入/输出(I/O)焊盘104，其中，第一半导体结构102具有用于设置I/O焊盘104的凹陷102R，所述I/O焊盘104电连接到外部电路或器件，以在半导体器件1和外部电路或器件之间传递电信号。在图2中示出了一个I/O焊盘104，但是本发明的I/O焊盘104的数量不限于此，并且可以有复数个。在该实施例中，第一半导体结构102包括第一衬底110以及一个或多个导电层112，其中，第一衬底110具有彼此相对的第一表面110a和第二表面110b，并且导电层112设置在第一衬底110的第一表面110a上。导电层112可以包括被凹陷102R暴露出的一个或多个第一迹线112T1，并且I/O焊盘104设置在第一迹线112T1上并且与第一迹线112T1电连接。通过将I/O焊盘104设置到凹陷102R内，能够减小在I/O焊盘104和第一衬底110之间生成的寄生电容。第一半导体结构102可以例如是外围器件结构，所以第一半导体结构102可以包括第一衬底110和在第一衬底110的第一表面110a上的外围互连层108，并且导电层112被包括在外围互连层108中。第一半导体结构102可以进一步包括在第一衬底110的第一表面110a上并且在外围互连层108和第一衬底110之间的外围器件106。第一衬底110例如可以包括硅(例如，单晶硅)、硅锗(SiGe)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)或任何其他适当材料。导电层112可以例如包括导体材料，所述导体材料包括但不限于W、Co、Cu、Al、硅化物或其任何组合。
应当指出，在图2中增加了X轴和Y轴，以进一步示出半导体器件1中的部件的空间关系。第一衬底110包括沿X方向(横向或宽度方向)横向延伸的两个横向表面(例如，第一表面110a和第二表面110b)。如本文所用，一个部件(例如，层或器件)在半导体器件的另一部件(例如，层或器件)“上”、“以上”或“之下”是在另一方向Y(垂直方向或厚度方向)上相对于半导体器件的衬底(例如，第一衬底110)来确定的。贯穿本公开内容应用相同的概念来描述空间关系。
在该实施例中，第一衬底110可以具有器件区DR和焊盘区PR。器件区DR用于形成外围器件106，以及焊盘区PR用于形成凹陷102R和I/O焊盘104，使得外围器件106不因凹陷102R和I/O焊盘104的形成而受到影响或损害。因此，第一衬底110可以被蚀穿，以具有对应于凹陷102R的开口110P。
外围器件106可以包括一个或多个晶体管。在图2所示的实施例中，示出了一个晶体管作为示例，但不限于此。外围器件106可以例如包括掺杂区106a和栅极结构106b。掺杂区106a设置在第一衬底110中。栅极结构106b可以被设置在第一衬底110和外围互连层108之间。
外围互连层108包括导电层112以及一个或多个绝缘层，使得外围器件106可以电连接至I/O焊盘104或其他器件，例如，下文的存储阵列器件。在图2所示的实施例中，示出了一个导电层112和两个绝缘层114a、114b作为示例，但不限于此。绝缘层114a和绝缘层114b中的每个绝缘层可以包括电介质材料，诸如氧化硅、氮化硅、氮氧化硅、任何其他适当的电介质材料或者它们的任何组合。导电层112设置在第一衬底110的第一表面110a上并且在绝缘层114a和绝缘层114b之间，并且绝缘层114a设置在导电层112和第一衬底110之间，使得导电层112的一些部分可以通过绝缘层114a与第一衬底110电隔离。
在该实施例中，凹陷102R进一步穿过在第一衬底110和导电层112之间的绝缘层114a，并且暴露出第一迹线112T1，使得绝缘层114a具有对应于凹陷102R的开口114P。例如，开口110P、开口114P、被暴露的第一迹线112T1和绝缘层114b的部分可以形成凹陷102R。
此外，半导体器件1可以进一步包括设置在第一衬底110的第二表面110b上的另一绝缘层118，其中，绝缘层118具有对应于凹陷102R的开口118P。换言之，开口118P暴露出凹陷102R。因此，I/O焊盘104可以通过开口118P和凹陷102R形成在导体层112上，并且通过被设置在凹陷102R中来电连接到被暴露的第一迹线112T1。例如，I/O焊盘104可以直接接触第一迹线112T1。在图2所示的实施例中，相互隔开的被暴露的第一迹线112T1的数量是多个，并且I/O焊盘104电连接至多个第一迹线112T1，但不限于此。在一些实施例中，被暴露的第一迹线112T1的数量可以为一，并且第一迹线112T1的宽度可以与凹陷102R的底部的宽度相同或不同。优选地，第一迹线112T1的宽度可以大于凹陷102R的底部的宽度，使得第一迹线112T1可以在形成凹陷102R时起到蚀刻停止层的作用。在一些实施例中，导电层112可以是外围互连层108内的导电层中的最接近第一衬底110的一个导电层，但不限于此。在一些实施例中，导电层112可以进一步包括电连接到外围器件106至少两个第二迹线112T2。在一些实施例中，被凹陷102R穿过的绝缘层的数量可以是多个。在一些实施例中，导电层112的厚度T1可以小于绝缘层114a的厚度T2，使得在导电层112和第一衬底110之间的间隔可以被增大，以减小其间的寄生电容。
在一些实施例中，外围互连层108可以进一步包括至少一个触点层116，用于将外围器件106电连接到导电层112。例如，触点层116包括穿过绝缘层114a的触点插塞。在一些实施例中，外围互连层108可以进一步包括在导电层112之下的触点层，但不限于此。导电层116可以例如包括导体材料，所述导体材料包括但不限于W、Co、Cu、Al、硅化物或其任何组合。
在一些实施例中，半导体器件1可以进一步包括用于保护绝缘层118、第一半导体结构102和I/O焊盘104的钝化层120。钝化层120具有暴露出I/O焊盘104的开口120P，使得I/O焊盘104能够通过开口120P电连接至外部电路或器件。
半导体器件可以例如是存储器件或者任何其他适当器件。参考图3，其示意性地示出了根据本发明的第一实施例的示例的半导体器件的截面图。如图3所示，在该示例中提供的半导体器件1是NAND闪速存储器件，但不限于此。NAND闪速存储器件中的存储单元是以在第一衬底110之下垂直延伸的多个NAND串222的形式提供的。在该示例中，半导体器件1可以进一步包括第二半导体结构224，以及第二半导体结构224包括第二衬底226和存储阵列器件228。第二衬底226被设置为与第一衬底110的第一表面110a相对，并且存储阵列器件228形成在第二衬底226上并且在第一衬底110和第二衬底226之间。第二衬底226例如可以包括硅(例如，单晶硅)、硅锗(SiGe)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)或任何其他适当材料。
存储阵列器件228可以包括设置在导电层112和第二衬底226之间的NAND串222。NAND串222垂直地延伸穿过多个导体层230和多个电介质层232。每个导体层230与电介质层232中对应的一个电介质层可以形成一对。每个导体层230可以在两侧与两个电介质层232相邻，并且每一电介质层232可以在两侧与两个导体层230相邻。导体层230可以包括导体材料，诸如钨(W)、钴(Co)、铜(Cu)、铝(Al)、掺杂硅、硅化物、任何其他适当导体材料或者它们的任何组合。电介质层232可以包括电介质材料，诸如氧化硅、氮化硅、氮氧化硅、任何其他适当的电介质材料或者它们的任何组合。此外，存储阵列器件228还可以包括源极触点234、字线触点236和电介质层238，其中，源极触点234垂直地延伸穿过导体层230和电介质层232，字线触点236在电介质层238内垂直地延伸，并且每个字线触点236与对应的导体层230接触，以单独地寻址存储阵列器件228的对应字线。应当指出，图2中所示的存储阵列器件228是用作示例，并且本领域技术人员了解存储阵列器件228可以具有其他结构，所以在本文中将不再详述存储阵列器件228的结构或其变型。在一些实施例中，隔离区240和掺杂区242可以形成在第二衬底226中。
如图2中所示，半导体器件1可以进一步包括阵列互连层244，用于将存储阵列器件228电连接到外围器件106和/或I/O焊盘104。例如，NAND串222中的一个NAND串通过阵列互连层244和外围互连层108来电连接到外围器件106。阵列互连层244设置在存储阵列器件228上并且与外围互连层108接触。阵列互连层244可以包括一个或多个触点层(例如，触点层246a、246b)、一个或多个导电层(例如，导电层248a、248b)以及一个或多个电介质层(例如，电介质层250a、250b)。触点层246a、246b以及导电层248a、248b可以包括导体材料，所述导体材料包括但不限于W、Co、Cu、Al、硅化物或其任何组合。电介质层250a、250b可以包括电介质材料，所述电介质材料包括但不限于氧化硅、氮化硅、低k电介质或其任何组合。
在该示例中，外围互连层108可以包括多个导电层112(例如，导电层112a、112b)、多个触点层116(例如，触点层116a、116b)以及多个电介质层(例如，电介质层114a、114b、114c)。在一些实施例中，触点层116的数量和电介质层的数量不限于复数个，并且可以基于导电层112的数量来调整。键合界面252可以形成在外围互连层108的电介质层114c与阵列互连层244的电介质层250a之间。键合界面252还可以形成在阵列互连层244的导体层248a与外围互连层108的导体层112b之间。换言之，第一半导体结构102在键合界面252处键合到第二半导体结构224。在一些实施例中，第一半导体结构102还可以包括形成在第一衬底110中的用于将不同部件隔开的隔离区154。
如上文所提及的，与图1所示的常规存储器件相比，半导体器件1可以具有下述优点。第一，由于I/O焊盘104直接设置在凹陷102R中，所以I/O焊盘104不存在于第一衬底110的开口110P中。因此，能够减小在I/O焊盘104和第一衬底110之间生成的寄生电容，由此改善半导体器件1的操作速度或者用于存储或读取半导体器件1中的数据的速度。第二，不需要增加绝缘层118的厚度来减小寄生电容，使得能够降低用于形成绝缘层118的成本，并且不需要较高的高宽比。因而，对I/O焊盘104的形成不受穿过绝缘层和衬底的通孔的较高的高宽比限制，并且在增加NAND串22的密度时能够使用于形成I/O焊盘104的工艺难度变得容易。第三，由于凹陷102R形成在包括外围器件106的第一半导体结构108上，因此凹陷102R的宽度(例如，处于70μm到80μm的范围内)不限于与NAND串222或TSC的宽度类似或相同，而且在光刻工艺中使用的曝光光不限于具有非常小的波长。例如，用于形成凹陷102R的光刻工艺可以使用I线曝光(例如，365nm)。由于该原因，将不会发生由于工艺误差在贯穿阵列触点与I/O焊盘之间的开路或者在半导体器件中的电流泄漏。出于该原因，不需要更加先进的技术，诸如用于形成具有穿过衬底的更大高宽比的通孔的机器、用于将钨胶填充到具有更大高宽比的通孔中的机器、用于在具有更大高宽比的通孔中沉积衬层的机器等等。第四，在增加导体层230和电介质层232的数量以升级存储容量时，不同的技术代仍然能够容易地共享相同的半导体器件1。
图4是根据本发明的第一实施例的半导体器件的示例性制造方法的流程图。图5到图8以及图2示意性地示出了半导体器件的示例性制造步骤，其中为了清楚起见，图6到图8忽略了第一半导体结构和第二半导体结构的部分，但是本发明不限于此。应当指出，图4中所示的步骤不是穷举的，并且也可以在所例示的步骤中的任何步骤之前、之后或者之间执行其他步骤。在该实施例中提供的半导体器件1的制造方法包括以下步骤S12-S20。如图4和图5所示，执行步骤S12，以提供暂时性半导体结构302。暂时性半导体结构302包括暂时性衬底310、暂时性绝缘层314a以及一个或多个导电层112。暂时性半导体结构302与第一半导体结构102的不同之处在于：半导体结构302的暂时性衬底310在步骤S12中未被变薄和蚀穿，所以暂时性半导体结构302不具有凹陷102R，并且暂时性衬底310不具有开口110P。在一些实施例中，暂时性衬底310的厚度在步骤S12中可以大于第一衬底110的厚度。在该实施例中，暂时性衬底310具有彼此相对的第一表面110a和第三表面310b，暂时性外围互连层308和外围器件106形成于暂时性衬底310的第一表面110a上。在步骤S12中，暂时性外围互连层308与上文提及的外围互连层108的不同之处在于：暂时性绝缘层314a未被蚀穿，以致不具有开口114P。在该实施例中，外围器件106与上文提及的类似或相同，并且将不再对其做多余的描述。
在步骤S12中，还提供了第二半导体结构224，并且所述第二半导体结构224被键合到暂时性半导体结构302。由于第二半导体结构224与上文提及的相同，所以将不重复地对第二半导体结构224做详细描述。
如图4、图5和图6中所示，可选地执行步骤S14以将暂时性衬底310的第三表面310b变薄，以形成第二表面110b。例如，将第一衬底310变薄可以包括执行化学机械平坦化(CMP)工艺或者任何其他适当工艺。
在将暂时性衬底310变薄之后，执行步骤S16，以在经变薄的暂时性衬底310的第二表面110b上形成绝缘层118，其中，绝缘层118具有暴露出暂时性衬底310的第二表面110b的开口118P。例如，形成绝缘层118可以包括沉积绝缘材料并且将绝缘材料层图案化。对绝缘材料层的沉积可以例如采用化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、原子层沉积(ALD)工艺或者任何其他适当的沉积工艺。对绝缘材料层的图案化可以例如采用使用光掩模(例如I线掩模)的光刻工艺。在一些实施例中，可以在提供暂时性半导体结构302之后直接执行步骤S16。
在形成绝缘层118之后，可以执行步骤S18，以在暂时性半导体结构302的焊盘区PR中形成凹陷102R。具体而言，形成凹陷102R可以包括：将被暴露的暂时性衬底310图案化，以在暂时性衬底310中形成开口110P，由此形成前述的具有开口110P的第一衬底110。对暂时性衬底310的图案化可以例如采用蚀刻工艺，所述蚀刻工艺使用绝缘层118作为掩模。形成凹陷102R还可以包括将被开口110P暴露出的暂时性绝缘层314a的一部分图案化，以在形成开口110P之后形成开口114P并且暴露出第一迹线112T1，由此形成具有开口114P的前述绝缘层114a。相应地，能够形成上文提及的第一半导体结构102，并且能够形成上文提及的外围互连层108。对暂时性绝缘层314a的图案化可以例如采用相对于绝缘层118、第一衬底110和导电层112对暂时性绝缘层314a进行选择性蚀刻的蚀刻工艺。在一些实施例中，外围互连层308还可以包括在导电层112和暂时性绝缘层314a之间的蚀刻停止层，使得对暂时性绝缘层314a的蚀刻能够停止在蚀刻停止层处，并且能够保护在第一迹线112T1之间的绝缘层114b。在一些实施例中，蚀刻工艺可以相对于绝缘层114b具有对暂时性绝缘层314a的高蚀刻选择性。
如图4和图8所示，可以执行步骤S20，以在凹陷102R中并且在第一迹线112T1上形成I/O焊盘104。具体地，如图7所示，形成I/O焊盘104包括：在绝缘层118、凹陷102R的侧壁以及第一迹线112T1上沉积导电材料层104m。换言之，导电材料层104m从绝缘层118的顶表面延伸到开口118P的侧壁、开口110P的侧壁、开口114P的侧壁和I/O焊盘104上。对导电材料层104m的沉积可以使用CVD工艺、PVD工艺、ALD工艺或者任何其他适当沉积工艺。随后，如图8中所示，形成I/O焊盘104还包括将导电材料层104m图案化，以去除导电材料层104m的在绝缘层118上和凹陷102R的侧壁上的部分。
如图2所示，在形成I/O焊盘104之后，还可以将钝化层120形成到绝缘层118、开口110P的侧壁、开口114P的侧壁和I/O焊盘104上，并且然后，钝化层120被图案化为具有暴露出I/O焊盘104的开口120P。相应地，形成该实施例的半导体器件1。
下文的描述将详细阐述本公开内容的不同实施例。为了简化描述，采用等同的符号标记下述实施例中的每个实施例的相同部件。为了使在实施例之间的差异更易于理解，下文的描述将详细阐述在不同实施例之间的相异之处，并且将不重复地描述等同的特征。
参考图9，其示意性地示出了根据本发明的第二实施例的示例性半导体器件。如图9中所示，该实施例中提供的半导体器件2与先前实施例的不同之处在于：第一迹线112T1的宽度W1可以大于凹陷102R的底部的宽度W2，因此第一迹线112T1可以在形成凹陷102R时起到蚀刻停止层的作用。
通过使用所公开的半导体器件及其制造方法，能够减小在I/O焊盘和第一衬底之间生成的寄生电容，由此改善存储器件的操作速度或者用于存储或读取在存储器件中的数据的速度。此外，不需要增加第一衬底上的绝缘层的厚度来减小寄生电容，使得能够降低用于形成绝缘层的成本，并且不需要较高的高宽比。因而，对I/O焊盘的形成不受较高的高宽比的限制，并且能够在增加NAND串的密度时使用于形成I/O焊盘的工艺难度变得容易。由于凹陷形成在包括外围器件的第一半导体结构上，所以第一半导体结构的凹陷的宽度不限于与NAND串或TSC的宽度类似或相同，在光刻工艺中使用的曝光光能够具有较大波长。此外，将不会发生由于工艺误差在贯穿阵列触点与I/O焊盘之间的开路或者在半导体器件中的电流泄漏，并且不需要更加先进的技术。此外，在增加导体层和电介质层的数量以升级存储容量时，不同的技术代仍然能够容易地使用相同的架构。
特定实施例的前述描述将这样充分地揭露其他人可以通过将在本领域的技能范围内的知识应用于各种应用(例如特定的实施例)，来容易修改和/或适应的本发明的一般性质，而没有过度的实验并且不偏离本发明的一般概念。因此，基于本发明和在本文提出的指导，这样的适应和修改旨在在所公开的实施例的等效形式的含义和范围内。应理解，本文的短语或术语是为了描述而不是限制的目的，使得本说明书的术语或短语应由技术人员按照本发明和指导来解释。
上面借助于用于说明特定功能的实现方式及其关系的功能构建块，描述了本发明的实施例。在本文为了描述的方便，这些功能构建块的边界已经被任意限定。可以定义替代的边界，只要特定功能及其关系被适当地执行。
发明内容和摘要部分可以阐述如发明人所设想的本发明的一个或多个但不是全部示例性实施例，并且因此不旨在以任何方式限制本发明和所附权利要求。
本领域的技术人员将容易地发现在遵循本发明的教导的同时可以对所述器件和方法做出很多修改和变更。相应地，应当将上文的公开内容视为仅由所附权利要求的公认范围来限定。

Claims (20)

1.一种三维存储器件，包括：
第一半导体结构，其包括第一衬底和导电层，其中，所述第一衬底具有彼此相对的第一表面和第二表面，所述导电层设置在所述第一衬底的所述第一表面上，并且所述导电层包括一个或多个第一迹线；以及
设置在所述一个或多个第一迹线上的输入/输出焊盘；
其中，所述第一半导体结构具有穿过所述第一衬底并且暴露出所述一个或多个第一迹线的凹陷，并且所述输入/输出焊盘被设置在所述凹陷中。
2.根据权利要求1所述的三维存储器件，还包括键合到所述第一半导体结构的第二半导体结构。
3.根据权利要求2所述的三维存储器件，其中，所述第二半导体结构包括多个NAND串。
4.根据权利要求3所述的三维存储器件，其中，所述第一半导体结构还包括在所述第一衬底上的外围器件，并且NAND串中的一个NAND串电连接到所述外围器件。
5.根据权利要求1所述的三维存储器件，还包括设置在所述第一衬底的所述第二表面上的第一绝缘层，其中，所述第一绝缘层具有对应于所述凹陷的开口。
6.根据权利要求1所述的三维存储器件，其中，所述第一半导体结构还包括在所述第一衬底的所述第一表面和第一导电层之间的第二绝缘层，其中，所述凹陷穿过所述第二绝缘层。
7.根据权利要求6所述的三维存储器件，其中，所述输入/输出焊盘的厚度小于所述第二绝缘层的厚度。
8.根据权利要求1所述的三维存储器件，其中，所述第一半导体结构还包括在所述第一衬底上的外围器件。
9.根据权利要求8所述的三维存储器件，其中，所述导电层还包括电连接到所述外围器件的至少两个第二迹线。
10.根据权利要求1所述的三维存储器件，其中，所述输入/输出焊盘直接接触所述一个或多个第一迹线。
11.根据权利要求1所述的三维存储器件，其中，所述一个或多个迹线的宽度大于所述凹陷的底部的宽度。
12.一种三维存储器件的制造方法，包括：
提供暂时性半导体结构，其中，所述暂时性半导体结构包括暂时性衬底和导电层，所述暂时性衬底具有第一表面，所述导体层被设置在所述暂时性衬底的所述第一表面上，并且所述导电层包括一个或多个第一迹线；
在所述暂时性半导体结构中形成凹陷，以形成第一半导体结构和第一衬底，其中，所述凹陷穿过所述第一衬底并且暴露出所述一个或多个第一迹线；以及
在所述凹陷中并且在所述一个或多个第一迹线上形成输入/输出焊盘。
13.根据权利要求12所述的三维存储器件的制造方法，其中，提供所述暂时性半导体结构包括提供键合到所述暂时性半导体结构的第二半导体结构。
14.根据权利要求13所述的三维存储器件的制造方法，其中，所述第二半导体结构包括多个NAND串。
15.根据权利要求12所述的三维存储器件的制造方法，还包括将所述暂时性衬底的与所述第一表面相对的表面变薄，以在提供所述暂时性半导体结构和形成所述凹陷之间形成第二表面。
16.根据权利要求12所述的三维存储器件的制造方法，还包括在提供所述暂时性半导体结构和形成所述凹陷之间，在所述暂时性衬底上形成第一绝缘层，其中，所述第一绝缘层具有暴露出所述暂时性衬底的开口。
17.根据权利要求16所述的三维存储器件的制造方法，其中，所述暂时性半导体结构还包括在所述暂时性衬底的所述第一表面和所述导电层之间的暂时性绝缘层，并且形成所述凹陷包括将所述暂时性绝缘层图案化为形成第二绝缘层。
18.根据权利要求17所述的三维存储器件的制造方法，其中，所述输入/输出焊盘的厚度小于所述第二绝缘层的厚度。
19.根据权利要求16所述的三维存储器件的制造方法，其中，形成所述输入/输出焊盘包括：
在所述第一绝缘层、所述凹陷的侧壁以及所述一个或多个第一迹线上沉积导电材料层；以及
去除所述导电材料层的在所述第一绝缘层和所述凹陷的侧壁上的部分。
20.根据权利要求19所述的三维存储器件的制造方法，其中，所述输入/输出焊盘是直接形成于所述一个或多个第一迹线上的。
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CN110770896A (zh) 2020-02-07
US11710730B2 (en) 2023-07-25
EP3915145B1 (en) 2024-03-13
US20210066274A1 (en) 2021-03-04
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