TW202349645A - 3d堆疊半導體晶片架構及其製造方法 - Google Patents
3d堆疊半導體晶片架構及其製造方法 Download PDFInfo
- Publication number
- TW202349645A TW202349645A TW111149186A TW111149186A TW202349645A TW 202349645 A TW202349645 A TW 202349645A TW 111149186 A TW111149186 A TW 111149186A TW 111149186 A TW111149186 A TW 111149186A TW 202349645 A TW202349645 A TW 202349645A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- wafer
- semiconductor wafer
- power
- power rails
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 242
- 238000000034 method Methods 0.000 title claims description 21
- 235000012431 wafers Nutrition 0.000 claims description 259
- 239000010410 layer Substances 0.000 claims description 191
- 239000011229 interlayer Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 239000000758 substrate Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0756—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/215—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/245—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
本發明提供一種三維(3D)堆疊半導體晶片架構,包含:第一半導體晶片,其包含:第一晶圓;第一前段製程(FEOL)層,設置於第一晶圓的第一側上;第一中段製程(MOL)層,設置於第一FEOL層上;第一後段製程(BEOL)層,設置於第一MOL層上;第一電源軌層,設置於第一晶圓的第二側上;及第二半導體晶片,其包含:第二晶圓;第二FEOL層,設置於第二晶圓的第一側上;第二MOL層,設置於第二FEOL層上;第二BEOL層,設置於第二MOL層上;第二電源軌層,設置於第二晶圓的第二側上,其中第一電源軌層與第二電源軌層彼此接觸。
Description
本發明的實例實施例是關於一種共享背面電源分佈軌的三維(three-dimensionally;3D)堆疊半導體晶片架構及其製造方法。
相關申請案的交叉參考
研發包含半導體晶片的多個堆疊的3D堆疊半導體晶片架構以藉由緊密大小在有限面積內堆疊多個電晶體。然而,對於包含載體晶圓及堆疊於載體晶圓上的前段製程(front-end-of-line;FEOL)層、中段製程(middle-of-line;MOL)層以及後段製程(back-end-of-line;BEOL)層的半導體晶片,連接半導體晶片的不同堆疊的通孔的縱橫比的限制使得難以堆疊多個半導體晶片。
另外,當根據相關技術堆疊半導體晶片時,歸因於可接合在一起的BEOL層的複雜結構,堆疊半導體晶片之間可能出現未對準。
此背景章節中所揭露的資訊在達成本申請案的實施例之前已由發明者知曉,或為在達成實施例的過程中獲取的技術資訊。因此,其可含有未形成已由公眾知曉的相關技術的資訊。
一或多個實例實施例提供一種三維(3D)堆疊半導體晶片架構及其製造方法。
根據實例實施例的態樣,提供一種3D堆疊半導體晶片架構,包含:第一半導體晶片,其包含:第一晶圓;第一FEOL層,設置於第一晶圓的第一側上;第一MOL層,設置於第一FEOL層上;第一BEOL層,設置於第一MOL層上;第一電源軌層,設置於第一晶圓的第二側上;及第二半導體晶片,其包含:第二晶圓;第二FEOL層,設置於第二晶圓的第一側上;第二MOL層,設置於第二FEOL層上;第二BEOL層,設置於第二MOL層上;第二電源軌層,設置於第二晶圓的第二側上,其中第一電源軌層與第二電源軌層彼此接觸。
根據實例實施例的另一態樣,提供一種製造3D堆疊半導體晶片架構的方法,方法包含:設置第一半導體結構,包含:設置第一晶圓;在第一晶圓的第一側上設置第一前段製程(FEOL)層;在第一FEOL層上設置第一中段製程(MOL)層;在第一MOL層上設置第一後段製程(BEOL)層;翻轉第一晶圓;以及在第一晶圓的第二側上設置第一電源軌層;設置第二半導體晶片,包含:設置第二晶圓;在第二晶圓的第一側上設置第二前段製程(FEOL)層;在第二FEOL層上設置第二中段製程(MOL)層;在第二MOL層上設置後段製程(BEOL)層;翻轉第二晶圓;以及在第二晶圓的第二側上設置第二電源軌層;翻轉第二半導體晶片;以及將第二半導體晶片接合至第一半導體晶片,使得第二電源軌層與第一電源軌層接觸。
根據實例實施例的另一態樣,提供一種3D堆疊半導體晶片架構,包含:第一半導體晶片,其包含:第一晶圓;第一前段製程(FEOL)層,設置於第一晶圓的第一側上;第一中段製程(MOL)層,設置於第一FEOL層上;第一後段製程(BEOL)層,設置於第一MOL層上;多個第一電源軌,設置於第一晶圓的第二側上,所述多個第一電源軌經組態以分佈電源;第二半導體晶片,包含:第二晶圓;第二FEOL層,設置於第二晶圓的第一側上;第二MOL層,設置於第二FEOL層上;第二BEOL層,設置於第二MOL層上;多個第二電源軌,設置於第二晶圓的第二側上,所述多個第二電源軌經組態以分佈電源,其中第一電源軌層與第二電源軌層彼此接觸,其中第一電源軌在垂直方向上自第一晶圓的第二側突出,且其中第二電源軌包括在垂直方向上延伸穿過第二晶圓的一部分的開口。
本文中所描述的實例實施例為實例,且因此,本揭露不限於此,且可以各種其他形式實現。以下描述中所提供的實例實施例中的各者不排除與本文中亦提供或本文中未提供但與本揭露一致的另一實例或另一實例實施例的一或多個特徵相關聯。舉例而言,即使特定實例或實例實施例中所描述的物質未在另外的不同實例或實例實施例描述,除非在其描述中另外提及,否則所述物質仍可理解為與不同實例或實施例有關或與不同實例或實施例組合。
另外,應理解,對原理、態樣、實例以及實例實施例的所有描述均意欲涵蓋所述原理、態樣、實例以及實例實施例的結構及功能等效物。另外,這些等效物應理解為不僅包含當前眾所周知的等效物,且亦包含未來待開發的等效物,亦即,發明以進行相同功能的所有裝置,無論其結構如何。
應理解,當將半導體裝置的元件、組件、層、圖案、結構、區等(在下文中統稱為「元件」)稱為「在」半導體裝置的另一元件「之上」、「上方」、「上」、「下方」、「之下」、「底下」、「連接至」或「耦接至」所述另一元件時,其可直接在所述另一元件之上、上方、上、下方、之下、底下、連接至或耦接至所述另一元件,或可存在介入元件。相反,當將半導體裝置的元件稱為「直接在」半導體裝置的另一元件「之上」、「直接在」所述另一元件「上方」、「直接在」所述另一元件「上」、「直接在」所述另一元件「下方」、「直接在」所述另一元件「之下」、「直接在」所述另一元件「底下」、「直接連接至」或「直接耦接至」所述半導體裝置的另一元件時,不存在介入元件。相同附圖標號貫穿本揭露指相同元件。
為易於描述,本文中可使用諸如「在…之上」、「在…上方」、「在…上」、「上部」、「在…下方」、「在…之下」、「在…底下」、「下部」、「頂部」以及「底部」以及類似者的空間相對術語以描述如在諸圖中所示出的一個元件與另一(些)元件的關係。應理解,除了圖中所描繪的定向之外,此類空間相對術語意欲涵蓋半導體裝置在使用或操作中的不同定向。舉例而言,若翻轉圖式中的半導體裝置,則描述為「在」其他元件「下方」或「在」其他元件「底下」的元件將隨後定向「在」其他元件「上方」。因此,術語「在……下方」可涵蓋上方及下方的定向兩者。半導體裝置可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞可相應地進行解釋。
如本文中所使用,諸如「……中的至少一者」的表述在位於元件清單之前時修飾整個元件清單,而並不修飾清單中的個別元件。舉例而言,表述「a、b以及c中的至少一者」應理解為包含僅a、僅b、僅c、a及b兩者、a及c兩者、b及c兩者,或a、b以及c中的所有者。在本文中,當術語「相同」用於比較兩個或多於兩個元件的尺寸時,所述術語可覆蓋「實質上相同」的尺寸。
將理解,儘管本文中可使用術語「第一」、「第二」、「第三」、「第四」等來描述各種元件,但這些元件不應受這些術語限制。此等術語僅用以將一個元件與另一元件區分開來。因此,在不脫離本揭露的教示的情況下,下文所論述的第一元件可稱為第二元件。
亦應理解,即使製造設備或結構的某一步驟或操作比另一步驟或操作更晚描述,所述步驟或操作亦可比另一步驟或操作更晚進行,除非將所述另一步驟或操作描述為在所述步驟或操作之後進行。
本文中參考為實施例(及中間結構)的示意性圖示的橫截面圖示來描述實例實施例。因此,預期圖解說明的形狀可以因為例如製造技術及/或公差而有所變化。因此,實例實施例不應視為受限於本文中所示出的特定區形狀,而應包含由於例如製造造成的形狀偏差。舉例而言,示出為矩形的植入區將通常在其邊緣具有圓化或彎曲特徵及/或植入濃度梯度,而非自植入區至非植入區的二元變化。同樣,由植入形成的內埋區可在內埋區與進行植入的表面之間的區中產生某種植入。因此,諸圖中所示出的區在本質上為示意性的,且其形狀並不意欲示出裝置區的實際形狀,且並不意欲限制本揭露的範疇。此外,在圖式中,出於清楚起見,可放大層及區的大小及相對大小。
出於簡潔起見,在本文中可或可不詳細地描述半導體裝置的通用元件。
在下文中,將參考隨附圖式詳細地解釋實施例。本文所描述的實施例為實例實施例,且因此本揭露不限於此。
圖1示出根據實施例的根據相關技術的通用配電網(PDN)半導體晶片及背面配電網(BSPDN)半導體晶片的透視圖。
參考圖1,通用PDN半導體晶片1000'包含形成於晶圓1100的一側(前側)上的PDN/信號配線層1200a'。然而,通用PDN半導體晶片1000'的此組態可導致PDN/信號配線層1200a'中的路由擁塞且增大通用PDN半導體晶片1000'的大小。另外,通用PDN半導體晶片1000'的電阻可相對較高。
如圖1中所示出,在根據實施例的BSPDN半導體晶片1000中,信號配線層1200a可設置於晶圓1100的第一側(前側)上,且配電網(PDN)層1200b可設置於晶圓1100的與信號配線層1200a相對的第二側(背面)上。根據本實施例的BSPDN半導體晶片1000可藉由自晶圓1100的第一側移除PDN來減少路由擁塞及減小BSPDN半導體晶片1000的大小,且因此形成更簡化的PDN層1200b可設置於晶圓1100的第二側上。
應理解,儘管信號配線層1200a及PDN層1200b分別與晶圓1100分離以在圖1中在其間具有空間,此分離僅出於說明目的以展示在本實施例中將分離相關技術的PDN/信號配線層1200a'。因此,根據實施例,這兩個層中的至少一者可接合至晶圓1100或以其他方式與晶圓1100整合,或其間可設置一或多個介入層。
圖2A示出根據相關技術的三維(3D)半導體晶片架構。
參考圖2A,3D堆疊半導體晶片架構1110'可包含第一半導體晶片及堆疊在第一半導體晶片上的第二半導體晶片。第一半導體晶片可包含載體晶圓(處置器晶圓)111、包含FEOL層及MOL層的半導體層113以及包含金屬圖案112的BEOL層。
在本文中,FEOL層可指包含半導體裝置(例如,電晶體)的初級結構的層或元件,初級結構諸如磊晶層(例如,源極/汲極區)、鰭結構(通道)以及閘極電極,且MOL層可以指包含接觸結構的層或元件,接觸結構諸如半導體裝置的源極/汲極接觸插塞、閘極接觸插塞以及相應通孔。此外,BEOL層可指代包含以下各者的元件層:連接至電壓源或用於來自/去往另一電路元件的信號路由的金屬圖案或接觸結構;及將金屬圖案或接觸結構連接至MOL元件或結構的通孔。
第二半導體晶片可包含載體晶圓111'、包含FEOL層及MOL層的半導體層113',以及包含金屬圖案112'的BEOL層。
第二半導體晶片可經翻轉使得金屬圖案112'面向第一半導體晶片的金屬圖案112,且第二半導體晶片可接合至第一半導體晶片以形成3D半導體晶片架構1110'。
然而,在先前技術中,由於第一半導體晶片及第二半導體晶片的BEOL層包含形成具有小特徵大小的複雜結構的各種金屬線及金屬圖案,因此精確對準第一半導體晶片的金屬圖案112與第二半導體晶片的金屬圖案112'可為困難的。
第一半導體晶片與第二半導體晶片之間的此類未對準可最終降低根據相關技術的3D堆疊半導體晶片架構1110'的品質。
圖2B示出根據實施例的3D堆疊半導體晶片架構。
參考圖2B,3D堆疊半導體晶片架構1110可包含第一BSPDN半導體晶片及堆疊於第一BSPDN半導體晶片上的第二BSPDN半導體晶片。第一BSPDN半導體晶片可包含載體晶圓11、包含FEOL層及MOL層的半導體層13以及設置於半導體層13的頂側(前側)上的BEOL層的一部分。BEOL層可包含金屬圖案12。在圖2B中,包含於BEOL層中的金屬圖案12可設置於載體晶圓11上。
第一BSPDN半導體晶片亦可包含背面BEOL層的一部分,所述背面BEOL層包含PDN層,所述PDN層包含設置於半導體層13的與金屬圖案12相對的底側(背面)上的背面電源軌21。背面電源軌21可連接至電壓源。因此,在本實施例中,BEOL層可劃分成兩個BEOL層,其間具有FEOL層及MOL層。
第二BSPDN半導體晶片可包含半導體層13'(包含FEOL層及MOL層),及設置於半導體層13'的頂側上的BEOL層的一部分。BEOL層可包含金屬圖案12'。另外,第二BSPDN半導體晶片可包含背面BEOL層的一部分,所述背面BEOL層包含PDN層,所述PDN層包含設置於半導體層13'的與金屬圖案12'相對的底側上的背面電源軌21'。背面電源軌21'可連接至電壓源。
第二BSPDN半導體晶片可經翻轉,使得背面電源軌21'面向第一BSPDN半導體晶片的背面電源軌21。第二BSPDN半導體結構接合至第一BSPDN半導體晶片以形成3D堆疊半導體晶片架構1110。
在根據實施例的3D堆疊半導體晶片1110中,形成於第一BSPDN半導體晶片的背面上的背面電源軌21(其與第一BSPDN的信號配線層分離)及形成於第二BSPDN半導體晶片的背面上的背面電源軌21'(其與第二BSPDN的信號配線層分離)可直接彼此接合,其間無任何金屬圖案,且因此可共享。由於背面電源軌21及背面電源軌21'與包含於圖2A中的先前技術的BEOL層中的金屬線以及金屬圖案112及金屬圖案112'相比具有更簡化的結構及更大的特徵大小,相較於根據先前技術的3D堆疊半導體晶片架構1110',可簡化接合製程且可改良背面電源軌21與背面電源軌21'之間的對準。包含於第一BSPDN半導體晶片中的背面電源軌21與包含於第二BSPDN半導體晶片中的背面電源軌21'的對準的此改良可導致根據本實施例的3D堆疊半導體晶片架構1110的品質的改良。另外,由於堆疊於第一BSPDN半導體晶片上的第二BSPDN半導體晶片不需要額外載體晶圓,因此所需的多個載體晶圓的數目可減少,且半導體晶片經翻轉的次數可減少。
圖3示出根據實施例的3D堆疊半導體晶片架構。
參考圖3,3D堆疊半導體晶片架構1可包含第一BSPDN半導體晶片及堆疊於第一BSPDN半導體晶片上的第二BSPDN半導體晶片。
第一BSPDN半導體晶片可包含載體晶圓100'、可為金屬圖案的BEOL層190、BEOL接觸結構及通孔170,以及介電質間層180。BEOL通孔170可自BEOL層延伸至MOL層。介電質間層180可填充BEOL接觸結構與通孔170之間的空間。第一BSPDN半導體晶片可更包含MOL層中的MOL接觸結構150及自MOL層延伸至FEOL層中的MOL通孔160。另一介電質間層140可設置於MOL接觸結構150的側表面上以填充MOL接觸結構150與MOL通孔160之間的空間。MOL接觸結構150及MOL通孔160可包含導電材料。
第一BSPDN半導體晶片亦可包含FEOL層。FEOL層可包含半導體裝置130及淺溝槽隔離(shallow trench isolation;STI)結構120。此處,半導體裝置130可包含一或多個電晶體,所述電晶體包含磊晶層、鰭結構、閘極結構等。STI結構120可包含氧化矽(SiO)或氮化矽(SiN),不限於此。另一介電質間層140'可設置於STI結構120上。介電質間層140、介電質間層140'或介電質間層180亦可由SiO或SiN形成,所述SiO或SiN與形成STI結構120的材料相同或不同。
第一BSPDN半導體晶片可更包含PDN層,所述PDN層包含背面電源軌200。雖然BEOL層190設置於第一BSPDN半導體晶片的第一側上,但PDN層可設置於第一BSPDN半導體晶片的與第一側相對的第二側(背面)上。背面電源軌200可藉由用金屬材料填充形成於介電質間層140'中的溝槽來形成。背面電源軌200可包含例如銅(Cu)、鈷(Co)、鎢(W)、鉬(Mo)以及釕(Ru),不限於此。MOL通孔160可在垂直方向上延伸至STI結構120的頂部表面的水平面且與背面電源軌200接觸。
第二BSPDN半導體晶片可具有與上文所描述的第一BSPDN半導體晶片實質上相同的組態,且因此,省略其詳細描述。
第二BSPDN半導體晶片可翻轉且堆疊於第一BSPDN半導體晶片上,使得第二BSPDN半導體晶片的背面電源軌200接合至第一BSPDN半導體晶片的背面電源軌200。
在根據本實施例的3D堆疊半導體晶片架構1中,由於背面電源軌200相較於先前技術的BEOL層具有更簡化結構,因此第一BSPDN半導體晶片的背面電源軌200與第二BSPDN半導體晶片的背面電源軌200之間的對準可得以改良,此可導致3D堆疊半導體晶片架構1的效能及品質的改良。
圖4A至圖4I示出製造根據實施例的3D堆疊半導體晶片架構的方法。
參考圖4A,方法可包含設置裝置基底(晶圓)100。裝置基底100可由半導體材料(例如,矽(Si))形成,或可為絕緣層上矽(SOI)基底的部分,不限於此。STI結構120可形成於裝置基底100中。STI結構120可在水平方向上彼此間隔開,且可包含SiO或SiN,不限於此。半導體裝置130可由裝置基底100形成,且可藉由STI結構120彼此隔離。半導體裝置130可包含電晶體。電晶體中的各者可包含磊晶層,所述磊晶層可為源極/汲極區、鰭片形成通道結構以及閘極結構,不限於此。下文所描述的電晶體可為一或多個FinFET、奈米線電晶體、奈米薄片電晶體等。
參考圖4B,介電質間層140可形成於STI結構120及半導體裝置130上。介電質間層140可形成於半導體裝置130及STI結構120的頂部表面上。
參考圖4C,介電質間層140及STI結構120可經圖案化以形成溝槽。
參考圖4D,溝槽可由導電材料填充以形成MOL通孔160及MOL接觸結構150。MOL通孔160可延伸穿過介電質間層140及STI結構120。MOL通孔160的底部表面可與STI結構120的底部表面共面。MOL接觸結構150可接觸半導體裝置130。MOL接觸結構150及MOL通孔160可一體成型。
參考圖4E,可設置載體晶圓100'。載體晶圓100'可包含矽(Si)。BEOL層190可形成於載體晶圓100'上。BEOL接觸結構及通孔170可形成於BEOL層190上,且介電質間層180可形成於BEOL接觸結構及通孔170以及BEOL層190的頂側上。
圖4D中所展示的半導體晶片可經翻轉且附接至介電質間層180,藉此MOL接觸結構150可接觸介電質間層180。MOL接觸結構150亦可接觸BEOL通孔170。
參考圖4F,裝置基底100可經蝕刻以暴露STI結構120、MOL通孔160以及半導體裝置130。可暴露STI結構120的頂部表面及側表面、MOL通孔160的頂部表面及側表面以及半導體裝置130的頂部表面。此處,STI結構120的頂部表面指代圖4D中的其底部表面,且MOL通孔160的頂部表面指代圖4D中的其底部表面。
參考圖4G,介電質間層140'可設置於STI結構120、MOL通孔160以及半導體裝置130上。
在本操作中,介電質間層140'可經圖案化以形成溝槽,所述溝槽暴露MOL通孔160的頂部表面及STI結構120的頂部表面。溝槽可由導電材料填充以形成背面電源軌200。背面電源軌200可接觸MOL通孔160的頂部表面及STI結構120的頂部表面。背面電源軌200可為例如矽通孔(through-silicon via;TSV)或埋入電源軌(buried power rail;BPR)。另外,背面電源軌200可包含Cu、Co、W、Mo以及Ru,不限於此。圖4G中的半導體晶片可稱為第一BSPDN半導體晶片10。
參考圖4H,可形成另一半導體晶片。圖4H中的半導體晶片可稱為第二BSPDN半導體晶片10'。圖4H中的第二BSPDN半導體晶片10'可具有與圖4G中所示出的第一BSPDN半導體晶片10實質上相同的組態,且因此,省略其詳細描述。
參考圖4I,圖4H中的第二BSPDN半導體晶片10'可翻轉且接合至圖4G中的第一BSPDN半導體晶片10以形成根據實施例的3D堆疊半導體晶片架構1。在3D堆疊半導體晶片架構1中,包含於第一BSPDN半導體晶片10中的背面電源軌200可接合至包含於第二BSPDN半導體晶片10'中的背面電源軌200。由於第一BSPDN半導體晶片10及第二BSPDN半導體晶片10'的背面電源軌具有更簡化的結構,因此可改良背面電源軌200之間的對準。對準的此類改良可導致3D堆疊半導體晶片架構的改良效能。
圖5示出包含於根據實施例的3D堆疊半導體晶片架構中的背面電源軌結構。
參考圖5,包含於第一BSPDN半導體晶片中的背面電源軌200a可自晶圓140a的表面突出。包含於第二BSPDN半導體晶片中的背面電源軌200b可經形成使得背面電源軌200b的表面與晶圓140b的表面共面。另外,背面電源軌200b可包含在垂直方向上延伸至晶圓140b的一部分的開口。開口的形狀及位置可對應於包含於第一BSPDN半導體晶片中的突出背面電源軌200a的形狀及位置,以使得當第一BSPDN半導體晶片及第二BSPDN半導體晶片接合時,突出背面電源軌200a裝配於形成於背面電源軌200b中的開口中。
舉例而言,背面電源軌200a的側表面的斜率可經形成以對應於背面電源軌200b的側表面的斜率,以使得當背面電源軌200a裝配至形成於背面電源軌200b中的開口中時,背面電源軌200a經由滑動沈降至開口中。因此,背面電源軌200a及背面電源軌200b的側表面將彼此自對準且彼此完全接觸,此可改良第一BSPDN與第二BSPDN之間的對準。然而,背面電源軌200a的形狀及形成於背面電源軌200b中的開口的形狀不限於此。舉例而言,背面電源軌200a及形成於背面電源軌200b中的開口可具有鋸齒形形狀、多齒形狀等。背面電源軌200a及形成於背面電源軌200b中的開口的形狀可藉由選擇性消減製造製程(諸如視需要使用罩幕的選擇性蝕刻)而形成。
根據如圖5中所示出的背面電源軌200a及背面電源軌200b的組態,可進一步改良第一BSPDN半導體晶片與第二BSPDN半導體晶片之間的對準。
圖6A及圖6B示出包含於根據實施例的3D堆疊半導體晶片架構中的背面電源軌的平面視圖,所述平面視圖可對應於圖5中所展示的配置。
參考圖6A,包含於第一BSPDN半導體晶片中的背面電源軌200a可具有圓形形狀,且包含於第二BSPDN半導體晶片中的背面電源軌200b可具有包含圓形開口的環形形狀。圓形開口可在垂直方向上延伸至晶圓140b的一部分且對應於背面電源軌200a的圓形形狀。當第一BSPDN半導體晶片接合至第二BSPDN半導體晶片時,圓形背面電源軌200a可適配至形成於環形背面電源軌200b中的圓形開口中。
參考圖6B,包含於第一BSPDN半導體晶片中的背面電源軌200a可具有在水平方向上延伸的矩形形狀,且包含於第二BSPDN半導體晶片中的背面電源軌200b可具有在水平方向上延伸的矩形形狀。矩形開口可形成於相鄰背面電源軌200b之間。矩形開口可在垂直方向上延伸至晶圓140b的一部分且對應於背面電源軌200a的矩形形狀。當第一BSPDN半導體晶片接合至第二BSPDN半導體晶片時,矩形背面電源軌200a可適配至形成於相鄰背面電源軌200b之間的矩形開口中。
圖7示出圖3中的3D堆疊半導體晶片架構的透視圖。
如圖7中所示出,3D堆疊半導體晶片架構可包含:第一BSPDN半導體晶片,包含半導體層211a、晶圓111a以及背面PDN層211b;及第二BSPDN半導體晶片,包含半導體層211a'、晶圓111a'以及背面PDN層211b'。半導體層211a及半導體層211a'可分別包含FEOL層、MOL層以及BEOL層。
晶圓111a及晶圓111a'可包含例如矽(Si)基底,不限於此。如圖7中所示出,晶圓111a及晶圓111a'可為圓形面板,但晶圓111a及晶圓111a'的形狀可不限於此。舉例而言,晶圓111a及晶圓111a'可為四邊形面板。晶圓111a及晶圓111a'可分別包含單層或多層。圖3示出圖7中的I-I'的橫截面視圖。
圖8示出製造根據實施例的3D堆疊半導體晶片架構的方法的流程圖。
方法可包含設置第一BSPDN半導體晶片,所述第一BSPDN半導體晶片包含第一晶圓、在第一晶圓的第一側上的第一FEOL層、在第一FEOL層上的第一MOL層,以及在第一MOL層上的第一BEOL層(S100)。
可翻轉第一晶圓(S110)。第一電源軌層可設置於第一晶圓的第二側上(S120)。
方法可更包含設置第二BSPDN半導體晶片,所述第二BSPDN半導體晶片包含第二晶圓、在第二晶圓的第一側上的第二FEOL層、在第二FEOL層上的第二MOL層,以及在第二MOL層上的第二BEO層(S130)。
可翻轉第二晶圓(S140)。第二電源軌層可設置於第二晶圓的第二側上(S150)。
所述方法可更包含翻轉第二BSPDN半導體晶片(S160)及將第二BSPDN半導體晶片接合至第一BSPDN半導體晶片,使得第二電源軌層接觸第一電源軌層(S170)。
圖9示出可併入有根據實施例的3D堆疊半導體晶片架構的半導體晶片。
參考圖9,根據實施例的半導體封裝2000可包含安裝於基底2100上的處理器2200及半導體裝置2300。處理器2200及/或半導體裝置2300可包含以上實施例中所描述的3D堆疊半導體晶片架構中的一或多者。
圖10示出根據實施例的電子系統的示意性方塊圖。
參考圖10,根據實施例的電子系統3000可包含使用匯流排3400來執行資料通信的微處理器3100、記憶體3200以及使用者介面3300。微處理器3100可包含中央處理單元(central processing unit;CPU)或應用程式處理器(application processor;AP)。電子系統3000可更包含與微處理器3100直接通信的隨機存取記憶體(random access memory;RAM)3500。微處理器3100及/或RAM 3500可實施於單一模組或封裝中。使用者介面3300可用於將資料輸入至電子系統3000,或自電子系統3000輸出資料。舉例而言,使用者介面3300可包含但不限於鍵盤、觸控板、觸控螢幕、滑鼠、掃描器、語音偵測器、液晶顯示器(liquid crystal display;LCD)、微發光裝置(light-emitting device;LED)、有機發光二極體(organic light-emitting diode;OLED)裝置、主動矩陣發光二極體(active-matrix light-emitting diode;AMOLED)裝置、印表機、照明系統或各種其他輸入/輸出裝置。記憶體3200可儲存微處理器3100的操作碼、由微處理器3100處理的資料或自外部裝置接收的資料。記憶體3200可包含記憶體控制器、硬碟或固態硬碟(solid state drive;SSD)。
電子系統3000中的至少微處理器3100、記憶體3200及/或RAM 3500可包含如上述實施例中所描述的3D堆疊半導體晶片架構。
應理解,本文中所描述的實施例應僅按描述性意義來考慮,而非出於限制目的。通常應將各實施例內的特徵或態樣的描述視為可用於其他實施例中的其他類似特徵或態樣。
雖然已參考圖式描述實施例,但所屬領域中具有通常知識者應理解,可在不脫離如由所附申請專利範圍界定的精神及範疇的情況下在其中進行形式及細節的各種變化。
1、1100、1110':3D堆疊半導體晶片架構
10:第一BSPDN半導體晶片
10':第二BSPDN半導體晶片
11、100'、111、111':載體晶圓
12、12'、112、112':金屬圖案
13、13'、113、113'、211a、211a':半導體層
21、21'、200、200a、200b:電源軌
100:裝置基底
120、120'STI:結構
130、2300:半導體裝置
140、140'、180:介電質間層
111a、111a'、140a、140b:晶圓
150:MOL接觸結構
160、160a、160b:MOL通孔
170:BEOL通孔
190:BEOL層
211b、211b':背面PDN層
1000:BSPDN半導體晶片
1000':通用PDN半導體晶片
1200a、1200a':配線層
1200b:配電網層
2000:半導體封裝
2100:基底
2200:處理器
3000:電子系統
3100:微處理器
3200:記憶體
3300:使用者介面
3400:匯流排
3500:RAM
I-I':線
S100、S110、S120、S130、S140、S150、S160、S170:步驟
根據結合隨附圖式進行的以下描述,本揭露內容的實例實施例的上述及/或其他態樣、特徵以及優勢將更顯而易見,在隨附圖式中:
圖1示出根據實例實施例的根據相關技術的通用配電網(power distribution network;PDN)半導體架構及背面配電網(back side power distribution network;BSPDN)半導體架構的透視圖。
圖2A示出根據先前技術的三維(3D)堆疊半導體晶片架構。
圖2B示出根據實例實施例的3D堆疊半導體晶片架構。
圖3示出根據實例實施例的3D堆疊半導體晶片架構。
圖4A、圖4B、圖4C、圖4D、圖4E、圖4F、圖4G、圖4H以及圖4I示出製造根據實例實施例的3D堆疊半導體晶片架構的方法。
圖5示出包含於根據實例實施例的3D堆疊半導體晶片架構中的背面電源軌結構。
圖6A及圖6B示出包含於根據實例實施例的3D堆疊半導體晶片架構中的背面電源軌結構的平面視圖。
圖7示出根據實例實施例的圖3中的3D堆疊半導體晶片架構的透視圖。
圖8示出製造根據實例實施例的3D堆疊半導體晶片架構的方法的流程圖。
圖9示出可併入有根據實例實施例的3D堆疊半導體晶片架構的半導體架構。
圖10示出根據實例實施例的電子系統的示意性方塊圖。
11:載體晶圓
12、12':金屬圖案
13、13':半導體層
21、21':電源軌
Claims (20)
- 一種三維(3D)堆疊的半導體晶片架構,包括: 第一半導體晶片,包括: 第一晶圓; 第一前段製程(FEOL)層,設置於所述第一晶圓的第一側上; 第一中段製程(MOL)層,設置於所述第一FEOL層上; 第一後段製程(BEOL)層,設置於所述第一MOL層上; 第一電源軌層,設置於所述第一晶圓的第二側上; 第二半導體晶片,包括: 第二晶圓; 第二FEOL層,設置於所述第二晶圓的第一側上; 第二MOL層,設置於所述第二FEOL層上; 第二BEOL層,設置於所述第二MOL層上; 第二電源軌層,設置於所述第二晶圓的第二側上, 其中所述第一電源軌層與所述第二電源軌層彼此接觸。
- 如請求項1所述的3D堆疊半導體晶片架構,其中所述第一電源軌層包括經組態以分佈電源的至少一個第一電源軌,以及 其中所述第二電源軌層包括經組態以分佈電源的至少一個第二電源軌。
- 如請求項2所述的3D堆疊半導體晶片架構,其中所述第一電源軌與所述第二電源軌接觸。
- 如請求項2所述的3D堆疊半導體晶片架構,其中所述第一電源軌在垂直方向上自所述第一晶圓的所述第二側上的表面突出,以及 其中所述多個第二電源軌包括在該垂直方向上延伸穿過所述第二晶圓的一部分的多個開口。
- 如請求項4所述的3D堆疊式半導體晶片架構,其中所述多個第一電源軌中的各者的形狀對應於所述開口的形狀,以及 其中所述多個第一電源軌分別插入至所述多個開口中且接觸所述多個第二電源軌。
- 如請求項5所述的3D堆疊半導體晶片架構,其中所述多個第一電源軌中的各者具有圓形形狀,以及 其中所述多個第二電源軌中的各者具有環形形狀且包括分別具有圓形形狀的所述開口,所述開口的所述圓形形狀對應於所述第一電源軌的所述圓形形狀。
- 如請求項5所述的3D堆疊半導體晶片架構,其中所述多個第一電源軌中的各者具有矩形形狀, 其中所述多個第二電源軌中的各者具有矩形形狀,以及 其中分別具有矩形形狀的所述多個開口設置於所述多個第二電源軌當中的相鄰第二電源軌之間,所述開口的所述矩形形狀對應於所述第一電源軌的所述矩形形狀。
- 如請求項2所述的3D層疊堆疊半導體晶片架構,其中所述第一晶圓及所述第二晶圓包括介電質間層。
- 如請求項2所述的3D堆疊半導體晶片架構,其中所述第一電源軌及所述第二電源軌包括銅(Cu)、鈷(Co)、鎢(W)以及釕(Ru)中的一者。
- 如請求項1所述的3D堆疊半導體晶片架構,其中所述第一半導體晶片及所述第二半導體晶片為背面配電網(BSPDN)半導體晶片。
- 一種製造三維(3D)堆疊半導體晶片架構的方法,所述方法包括: 設置第一半導體晶片,包括: 設置第一晶圓; 在所述第一晶圓的第一側上設置第一前段製程(FEOL)層; 在所述第一FEOL層上設置第一中段製程(MOL)層; 在所述第一MOL層上設置第一後段製程(BEOL)層; 翻轉所述第一晶圓;以及 在所述第一晶圓的第二側上設置第一電源軌層; 設置第二半導體晶片,包括: 設置第二晶圓; 在所述第二晶圓的第一側上設置第二前段製程(FEOL)層; 在所述第二FEOL層上設置第二中段製程(MOL)層; 在所述第二MOL層上設置第二後段製程(BEOL)層; 翻轉所述第二晶圓;以及 在所述第二晶圓的第二側上設置第二電源軌層; 翻轉所述第二半導體晶片;以及 將所述第二半導體晶片接合至所述第一半導體晶片,使得所述第二電源軌層與所述第一電源軌層接觸。
- 如請求項11所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述設置所述第一電源軌層包括設置經組態以分佈電源的多個第一電源軌,以及 其中設置所述第二電源軌層包括設置經組態以分佈電源的多個第二電源軌。
- 如請求項12所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述接合包括將所述多個第一電源軌分別接合至所述多個第二電源軌。
- 如請求項12所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述多個第一電源軌經形成以在垂直方向上自所述第一晶圓的所述第二側面的表面突出,以及 其中在所述垂直方向上延伸穿過所述第二晶圓的一部分的開口形成於所述第二電源軌中的各者中。
- 如請求項14所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述多個第一電源軌中的各者的形狀經形成以對應於所述開口的形狀;以及 所述多個第一電源軌插入至包含於所述多個第二電源軌中的所述多個開口中以分別與所述多個第二電源軌接觸。
- 如請求項15所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述多個第一電源軌中的各者以圓形形狀形成,以及 其中所述多個第二電源軌中的各者以環形形狀形成,包括分別具有對應於所述第一電源軌的所述圓形形狀的圓形形狀的所述開口。
- 如請求項15所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述多個第一電源軌中的各者以矩形形狀形成, 其中所述多個第二電源軌中的各者以矩形形狀形成, 其中分別具有矩形形狀的所述多個開口設置於所述多個第二電源軌當中的相鄰第二電源軌之間,所述開口的所述矩形形狀對應於所述第一電源軌的所述矩形形狀。
- 如請求項10所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述設置所述第一晶圓與所述第二晶圓包括設置介電質間層。
- 如請求項10所述的製造三維(3D)堆疊半導體晶片架構的方法,其中所述第一半導體晶片及所述第二半導體晶片為背面配電網(BSPDN)半導體晶片。
- 一種三維(3D)堆疊的半導體晶片架構,包括: 第一半導體晶片,包括: 第一晶圓; 第一前段製程(FEOL)層,設置於所述第一晶圓的第一側上; 第一中段製程(MOL)層,設置於所述第一FEOL層上; 第一後段製程(BEOL)層,設置於所述第一MOL層上; 多個第一電源軌,設置於所述第一晶圓的第二側上,所述多個第一電源軌經組態以分佈電源;以及 第二半導體晶片,設置於所述第一半導體晶片上,所述第二半導體晶片包括: 第二晶圓; 第二FEOL層,設置於所述第二晶圓的第一側上; 第二MOL層,設置於所述第二FEOL層上; 第二BEOL層,設置於所述第二MOL層上; 多個第二電源軌,設置於所述第二晶圓的第二側上,所述多個第二電源軌經組態以分佈電源, 其中所述多個第一電源軌及所述多個第二電源軌彼此接觸, 其中所述多個第一電源軌在垂直方向上自所述第一晶圓的所述第二側上的表面突出,以及 其中所述多個第二電源軌包括在所述垂直方向上延伸穿過所述第二晶圓的一部分的多個開口。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202263308692P | 2022-02-10 | 2022-02-10 | |
US63/308,692 | 2022-02-10 | ||
US17/720,642 | 2022-04-14 | ||
US17/720,642 US20230253324A1 (en) | 2022-02-10 | 2022-04-14 | 3d stacked chip that shares power rails |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202349645A true TW202349645A (zh) | 2023-12-16 |
Family
ID=84799870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111149186A TW202349645A (zh) | 2022-02-10 | 2022-12-21 | 3d堆疊半導體晶片架構及其製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20230253324A1 (zh) |
EP (1) | EP4227994A1 (zh) |
KR (1) | KR20230121548A (zh) |
TW (1) | TW202349645A (zh) |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7354798B2 (en) * | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
US9343369B2 (en) * | 2014-05-19 | 2016-05-17 | Qualcomm Incorporated | Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems |
US11037817B2 (en) * | 2017-03-30 | 2021-06-15 | Intel Corporation | Apparatus with multi-wafer based device and method for forming such |
US10727205B2 (en) * | 2018-08-15 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding technology for stacking integrated circuits |
US10811415B2 (en) * | 2018-10-25 | 2020-10-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method for making the same |
US20210343650A1 (en) * | 2020-04-30 | 2021-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power distribution structure and method |
US11239208B2 (en) * | 2020-05-12 | 2022-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packaged semiconductor devices including backside power rails and methods of forming the same |
TW202236569A (zh) * | 2020-12-04 | 2022-09-16 | 日商東京威力科創股份有限公司 | 密集閘極上閘極3d邏輯積體的層間電力輸送網路(pdn) |
WO2023272623A1 (en) * | 2021-06-30 | 2023-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
JPWO2023276125A1 (zh) * | 2021-07-01 | 2023-01-05 | ||
US20240063183A1 (en) * | 2022-08-19 | 2024-02-22 | Intel Corporation | Modular package architecture for voltage regulator-compute-memory circuits with quasi-monolithic chip layers |
-
2022
- 2022-04-14 US US17/720,642 patent/US20230253324A1/en active Pending
- 2022-12-06 KR KR1020220168971A patent/KR20230121548A/ko unknown
- 2022-12-21 TW TW111149186A patent/TW202349645A/zh unknown
-
2023
- 2023-01-03 EP EP23150135.4A patent/EP4227994A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
KR20230121548A (ko) | 2023-08-18 |
US20230253324A1 (en) | 2023-08-10 |
EP4227994A1 (en) | 2023-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10964692B2 (en) | Through silicon via design for stacking integrated circuits | |
US11758732B2 (en) | Hybrid bonding contact structure of three-dimensional memory device | |
JP7486058B2 (ja) | 後面電力供給における交換用埋設電力レール | |
US9379042B2 (en) | Integrated circuit devices having through silicon via structures and methods of manufacturing the same | |
CN112582375B (zh) | 带侧壁互连结构的半导体装置及其制造方法及电子设备 | |
CN112582374B (zh) | 带侧壁互连结构的半导体装置及其制造方法及电子设备 | |
CN112020774B (zh) | 半导体器件及用于形成半导体器件的方法 | |
US11961787B2 (en) | Semiconductor device with sidewall interconnection structure and method for manufacturing the same, and electronic apparatus | |
US20220101906A1 (en) | Novel capacitor structure and method of forming the same | |
TW202220152A (zh) | 半導體架構及其製造方法 | |
KR20220157301A (ko) | 후면 배전망 반도체 구조를 통해 구현된 쓰루-실리콘 매립 파워 레일 및 이의 제조 방법 | |
KR20220104617A (ko) | 에피택시얼층 직접 연결을 사용하는 후면 배전 네트워크 반도체 아키텍처 및 그의 제조 방법 | |
TW202422879A (zh) | 具有閘極接點之自對準閘極端蓋(sage)架構 | |
TW202349645A (zh) | 3d堆疊半導體晶片架構及其製造方法 | |
EP4261882A1 (en) | Reversed high aspect ratio contact (harc) structure and process | |
US20230326858A1 (en) | Reversed high aspect ratio contact (harc) structure and process | |
CN116581103A (zh) | 三维堆叠半导体芯片架构和制造其的方法 | |
EP4287246A1 (en) | A method for producing an interconnect rail for contacting a semiconductor device from the back side | |
US20240079294A1 (en) | Alignment mark for back side power connections | |
TWI773086B (zh) | 用於形成立體(3d)記憶體元件的方法 | |
CN116895634A (zh) | 半导体芯片架构及其制造方法 | |
US20240203882A1 (en) | Semiconductor device and method of forming thereof | |
TW202109852A (zh) | 半導體元件及其製造方法 |