TWI493659B - 匹配裝置中之奈米線電路 - Google Patents

匹配裝置中之奈米線電路 Download PDF

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TWI493659B
TWI493659B TW100111963A TW100111963A TWI493659B TW I493659 B TWI493659 B TW I493659B TW 100111963 A TW100111963 A TW 100111963A TW 100111963 A TW100111963 A TW 100111963A TW I493659 B TWI493659 B TW I493659B
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Sarunya Bangsaruntip
Guy Cohen
Amlan Majumdar
Jeffrey W Sleight
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Description

匹配裝置中之奈米線電路
本發明係關於半導體奈米線場效電晶體。
奈米線場效電晶體(field effect transistor，FET)包括奈米線的摻雜部分，其接觸裝置的通道區(channel region)並當成源極區(source region)與汲極區(drain region)。FET可用互補金屬氧化物半導體方法製造，以形成多種積體電路。
根據本發明的一個具體實施例，反向器裝置(inverter device)包括連接至一電壓源節點(voltage source node)與一接地節點(ground node)的一第一奈米線；具有一配置在該第一奈米線上的閘極(gate)的一第一p型(p-type)場效電晶體(pFET)裝置；以及具有一配置在該第一奈米線上的閘極的一第一n型場效電晶體(nFET)裝置。
根據本發明的替代具體實施例，形成反向器裝置的方法包括形成一第一奈米線；形成具有一配置在該第一奈米線上的閘極的一第一p型場效電晶體(pFET)裝置；形成具有一配置在該第一奈米線上的閘極的一第一n型場效電晶體(nFET)裝置；以及電連接該第一pFET裝置的該閘極至該第一nFET裝置的該閘極。
根據本發明的另一替代具體實施例，記憶體裝置(memory device)包括連接至一第一位元線節點(bit line node)與一接地節點的一第一奈米線；具有一配置在該第一奈米線上的閘極的一第一場效電晶體(FET)；具有一配置在該第一奈米線上的閘極的一第二FET；連接至一電壓源節點與一第一輸入節點(input node)的一第二奈米線；具有一配置在該第二奈米線上的閘極的一第三FET；連接至該電壓源節點與一第二輸入節點的一第三奈米線；具有一配置在該第三奈米線上的閘極的一第四FET；連接至一第二位元線節點與該接地節點的一第四奈米線；具有一配置在該第四奈米線上的閘極的一第五FET；以及具有一配置在該第四奈米線上的閘極的一第六FET。
根據本發明又另一替代具體實施例，形成記憶體裝置的方法包括形成連接至一第一位元線節點與一接地節點的一第一奈米線；形成具有一配置在該第一奈米線上的閘極的一第一場效電晶體(FET)；形成具有一配置在該第一奈米線上的閘極的一第二FET；形成連接至一電壓源節點與一第一儲存節點(storage node)的一第二奈米線；形成具有一配置在該第二奈米線上的閘極的一第三FET；形成連接至該電壓源節點與一第二儲存節點的一第三奈米線；形成具有一配置在該第三奈米線上的閘極的一第四FET；形成連接至一第二位元線節點與該接地節點的一第四奈米線；形成具有一配置在該第四奈米線上的閘極的一第五FET；以及形成具有一配置在該第四奈米線上的閘極的一第六FET。
透過本發明的技術可實現其他特徵與優點。本說明書內詳細描述本發明的其他具體實施例與態樣，且這些具體實施例與態樣視為所主張發明的一部分。為了更加了解本發明的優點與特徵，請參閱說明與附圖。
積體電路可包括由奈米線通道場效電晶體(FET)形成的許多不同類型FET裝置，奈米線通道FET包括連接至源極區與汲極區的矽奈米線，以及完全(或部分)包圍奈米線的閘極。通道形成於奈米線之閘極底下的表面上(或在直徑小於大約5 nm的奈米線之奈米線塊體內)。閘極完全包圍奈米線時，該裝置稱之為環繞閘極(gate-all-around，GAA)FET。閘極部分包圍奈米線時，如同奈米線固定至絕緣體之情況，該裝置稱之為omega閘極(omega-gate)FET。奈米線FET可製造來形成例如nFET和pFET裝置。nFET和pFET裝置可相連，以形成多種積體電路裝置，例如反向器以及靜態隨機存取記憶體(static random access memory，SRAM)。在電路裝置中，多個FET一般需要藉由例如相似的臨界電壓與驅動電流而作匹配。
晶圓上形成的奈米線FET裝置可包括任意數量的奈米線。該製程可包括例如使用等向性蝕刻製程(isotropic etching process)在嵌埋氧化物基板(buried oxide substrate，BOX substrate)上形成矽奈米線。該蝕刻製程產生橢圓(包括圓柱)形狀的奈米線，其可懸浮在基板上方或可部分置於基板上。該奈米線上形成金屬或多晶矽閘極結構，該閘極結構旁邊形成源極與汲極區，並且可形成接點，以將源極、汲極和閘極結構連接至其他裝置。
該製程特別可產生具有不同性質的奈米線，像是例如由於晶圓上特定奈米線之位置，晶圓上一奈米線的直徑可能與另一奈米線的直徑不同。雖然在晶圓上的兩條不同奈米線的直徑會改變，不過每一特定奈米線的直徑通常維持不變，並且在所需的公差範圍內。
像是例如SRAM和反向器這類積體電路裝置都包含許多pFET和nFET裝置，其置於配置於晶圓上的奈米線上。由於這些奈米線的性質(例如奈米線直徑)實現裝置的操作，因此需要配置該等裝置，使得奈米線性質差異的影響能降低。
圖1例示反向器的先前技術範例之圖式，該反向器包括連接至nFET裝置103之pFET裝置101。裝置101連接至電壓源節點(Vdd)106、輸入節點(A)102和輸出節點(Q)104。裝置102連接至接地節點(Vss)108、A和Q。
圖2例示靜態隨機存取記憶體(SRAM)電路的先前技術範例之圖式。SRAM包括連接至第一位元線節點(BL)202的第一nFET裝置(M6 )201、第一輸出節點(Q)204和字線節點(WL)206。第二nFET裝置(M3 )203連接至Q節點204、接地節點(Vss)208和第二輸出節點()210。第一pFET裝置(M4 )205連接至Q節點204、節點210和電壓源節點(Vdd)212。第二pFET裝置(M2 )207連接至Vdd節點212、Q節點204和節點210。第三nFET裝置(M1)209連接至Vss節點208、Q節點204和節點210。第四nFET裝置(M5)211連接至第二位元線節點()213、WL節點206和節點210。
如上討論，晶圓上的奈米線可具有不同直徑，影響置於奈米線上之閘極的效能特性(performance characteristic)。當裝置內特定FET具有類似特性時，包括例如圖1和圖2先前技術範例的積體電路之效能可獲得改善。因此，透過在共線(common wire)內使用更好的匹配裝置(matched device)，設計積體電路使得特定FET分享共用奈米線(common nanowire)可改善電路之效能。
圖3例示奈米線反向電路300的示範具體實施例，其如上述用基板上形成的矽奈米線裝置所製造。電路300包括連接至電壓源節點(Vdd)306與接地節點(Vss)308的第一奈米線320。pFET裝置301和nFET裝置303具有置於第一奈米線320上的閘極區(G)。裝置301和303的汲極區(D)連接至輸出節點(Q)304。裝置301的源極區(S)連接至Vdd節點306，且裝置303的源極區(S)連接至Vss節點308。裝置301和303的閘極都連接至輸入節點(A)302。例示的具體實施例包括類似於反向電路300的第二反向電路350。反向電路350形成於第二奈米線321上。第二反向電路350的A節點302藉由矽構件(silicon member)352連接至Q節點304。藉由將FET裝置301和303置於相同奈米線上，第一奈米線320上反向電路300的配置改善電路300的效能，導致具有類似效能特性的FET裝置301和303。利用配置第二反向電路350，可獲得類似的優點。
圖4例示奈米線SRAM電路400的示範具體實施例，其以上述類似方式用矽奈米線裝置所製造。電路400包括連接至位元線節點(BL)402與第一接地節點(Vss)408a的第一奈米線420。第一nFET裝置(M6 )401形成於第一奈米線420上，並連接至BL節點402、第一輸出節點(Q)404和第一字線節點(WL)406a。第二nFET裝置(M3 )403形成於第一奈米線420上，並且連接至Q節點404、第一Vss節點408a和第二輸出節點()410。第二奈米線421連接至Q節點404和第一電壓源節點(Vdd)412a。第一pFET裝置(M4 )405形成於第二奈米線421上，並且連接至Q節點404、節點410和Vdd節點412a。第三奈米線422連接至第二Vdd節點412b和節點410。第二pFET裝置(M2 )407形成於第三奈米線422上，並且連接至Vdd節點412b、Q節點404和節點410。第四奈米線423連接至第二Vss節點408b和位元線節點()412。第三nFET裝置(M1)409連接至第二Vss節點408b、Q節點404和節點410。第四nFET裝置(M5)411連接至位元線節點()412、第二WL節點406b和節點410。可形成矽構件452，將第一奈米線420連接至Q節點404，並且可形成矽構件453，將第四奈米線423連接至節點410。
雖然所例示的具體實施例包括在積體電路內實施匹配FET的兩個範例，但是，藉由將特定FET裝置排列在特定奈米線上，上述方法可施加於任何一種積體電路，以改善電路效能，使得相同奈米線上的FET裝置具有類似效能特性。
此處所使用的術語僅為說明特定具體實施例之用，並非用於限制本發明。如此處所使用，除非上下文有明確指示，否則該等單數形式「一」(a,an)和「該」(the)也包含該等複數形式。吾人將更瞭解，說明書中使用的術語「包含」(comprises及/或comprising)指明所陳述的特徵、整體、步驟、操作、元件及/或組件的存在，但是不排除還有一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組的存在或添加。
對應的結構、材料、動作以及或以下申請專利範圍內所有裝置或步驟附加功能之元件的同等物，都欲包含任何結構、材料或動作，以結合特別主張的其他主張元件來執行該功能。本發明的描述已經為了例示與描述的目的而呈現，但非要將本發明毫無遺漏地限制在所揭之形式中。在不脫離本發明之範疇與精神的前提下，本領與之一般技術者將瞭解許多修正以及變化。具體實施例經過選擇與說明來最佳闡述本發明原理及實際應用，並且使其他本領域之一般技術者瞭解用於各種具體實施例的本發明，這些實施例具有適合於所考量之特定用途的各種修改。
本說明書內說明的圖式只是一個範例，在不悖離本發明精神之下，本說明書內說明的圖式或步驟(或操作)可有許多變化。例如：該等步驟可用不同順序執行，或可增加、刪減或修改步驟。所有這些變化都視為所主張發明的一部分。
雖然已經說明過本發明的較佳具體實施例，但精通此技術的人士可了解，目前與未來可在後附申請專利範圍的範疇內進行各種修改與增強。這些申請專利範圍應被視為對主要描述之本發明維持適當保護。
101．．．pFET裝置
102．．．輸入節點(A)
103．．．nFET裝置
104．．．輸出節點(Q)
106．．．源電壓節點(Vdd)
108．．．接地節點(Vss)
201．．．第一nFET裝置(M6 )
202．．．第一位元線節點(BL)
203．．．第二nFET裝置(M3 )
204．．．第一輸出節點(Q)
205．．．第一pFET裝置(M4 )
206．．．字線節點(WL)
207．．．第二pFET裝置(M2 )
208．．．接地節點(Vss)
209．．．第三nFET裝置(M1)
210．．．第二輸出節點()
211．．．第四nFET裝置(M5)
212．．．電壓源節點(Vdd)
213．．．第二位元線節點()
300．．．奈米線反向電路
301．．．pFET裝置
302．．．輸入節點(A)
303．．．nFET裝置
304．．．輸出節點(Q)
306．．．源電壓節點(Vdd)
308．．．接地節點(Vss)
320．．．第一奈米線
321．．．第二奈米線
350．．．第二反向電路
352．．．矽構件
400．．．奈米線SRAM電路
401．．．第一nFET裝置(M6 )
402．．．位元線節點(BL)
403．．．第二nFET裝置(M3 )
404．．．第一輸出節點(Q)
405．．．第一pFET裝置(M4 )
406a．．．第一字線節點(WL)
406b．．．第二WL節點
407．．．第二pFET裝置(M2 )
408a．．．第一接地節點(Vss)
408b．．．第二Vss節點
409．．．第三nFET裝置(M1)
410．．．第二輸出節點()
411．．．第四nFET裝置(M5)
412．．．位元線節點()
412a．．．第一電壓源節點(Vdd)
412b．．．第二Vdd節點
420．．．第一奈米線
421．．．第二奈米線
422．．．第三奈米線
423．．．第四奈米線
452．．．矽構件
453．．．矽構件
在本說明書總結處特別指出與本發明有關的標的，並在申請專利範圍內清楚提出。從下列搭配附圖的詳細說明中，可瞭解本發明的上述與其他特徵和優點，其中：
圖1例示反向器電路的先前技術範例的圖式。
圖2例示靜態隨機存取記憶體(SRAM)電路的先前技術範例的圖式。
圖3例示奈米線反向電路的示範具體實施例。
圖4例示奈米線SRAM電路的示範具體實施例。
300．．．奈米線反向電路
301．．．pFET裝置
302．．．輸入節點(A)
303．．．nFET裝置
304．．．輸出節點(Q)
306．．．源電壓節點(Vdd)
308．．．接地節點(Vss)
320．．．第一奈米線
321．．．第二奈米線
350．．．第二反向電路
352．．．矽構件

Claims (15)

  1. 一種反向器裝置，包括：一第一奈米線，其連接至一電壓源節點與一接地節點；一第一p型場效電晶體(pFET)裝置，其具有一配置在該第一奈米線上的閘極；以及一第一n型場效電晶體(nFET)裝置，其具有一配置在該第一奈米線上的閘極。
  2. 如申請專利範圍第1項之裝置，其中該裝置另包括：一第二奈米線，其連接至該電壓源節點與該接地節點；一第二p型場效電晶體(pFET)裝置，其具有一配置在該第二奈米線上的閘極；以及一第二n型場效電晶體(nFET)裝置，其具有一配置在該第二奈米線上的閘極。
  3. 如申請專利範圍第2項之裝置，其中該裝置另包括連接至該第一pFET裝置的該閘極與該第一nFET裝置的該閘極的一第三節點，及/或連接至該第二pFET裝置的該閘極與該第二nFET裝置的該閘極的一第四節點。
  4. 如申請專利範圍第3項之裝置，其中該裝置包括該第四節點與該第一pFET裝置的一汲極區和該第一nFET裝置的一汲極區之間的一連接。
  5. 如申請專利範圍第1項之裝置，其中該第一奈米線為一矽奈米線，或懸浮在一基板上方。
  6. 一種形成一反向器裝置的方法，該方法包括：形成一第一奈米線；形成一第一p型場效電晶體(pFET)裝置，其具有一配置在該第一奈米線上的閘極；形成一第一n型場效電晶體(nFET)裝置，其具有一配置在該第一奈米線上的閘極；以及電連接該第一pFET裝置的該閘極至該第一nFET裝置的該閘極。
  7. 如申請專利範圍第6項之方法，其中該方法另包括：形成一第二奈米線；形成一第二p型場效電晶體(pFET)裝置，其具有一配置在該第二奈米線上的閘極；形成一第二n型場效電晶體(nFET)裝置，其具有一配置在該第二奈米線上的閘極；以及電連接該第二pFET裝置的該閘極至該第二nFET裝置的該閘極、該第一pFET裝置的一汲極區以及該第一nFET裝置的一汲極區。
  8. 如申請專利範圍第6項之方法，其中該方法另包括連接該第一pFET裝置的一源極區至一電壓源節點，或連接該第一nFET裝置的一源極區至一接地節點。
  9. 一種記憶體裝置，包括：一第一奈米線，其連接至一第一位元線節點與一接地節點；一第一場效電晶體(FET)，其具有一配置在該第一奈米線上的閘極；一第二FET，其具有一配置在該第一奈米線上的閘極；一第二奈米線，其連接至一電壓源節點與一第一輸入節點；一第三FET，其具有一配置在該第二奈米線上的閘極；一第三奈米線，其連接至一電壓源節點與一第二輸入節點；一第四FET，其具有一配置在該第三奈米線上的閘極；一第四奈米線，其連接至一第二位元線節點與該接地節點；一第五FET，其具有一配置在該第四奈米線上的閘極；以及一第六FET，其具有一配置在該第四奈米線上的閘極。
  10. 如申請專利範圍第9項之裝置，其中該第一FET的一閘極端子(terminal)連接至一字線節點，該第二FET的一閘極端子連接至該第二輸入節點，該第三FET的一閘極端子連接至該第二輸入節點，該第四FET的一閘極端子連接至該第一輸入節點，該第五FET的一閘極端子連接至該第一輸入節點，且該第六FET的一閘極端子連接至該字線節點。
  11. 如申請專利範圍第9項之裝置，其中該第一FET為一n型FET(nFET)，該第二FET為一nFET，該第三FET為一p型FET(pFET)，該第四FET為一pFET，該第五FET為一nFET，且該第六FET為一nFET。
  12. 如申請專利範圍第9項之裝置，其中該第一奈米線為一矽奈米線，或懸浮在一基板上方。
  13. 如申請專利範圍第9項之裝置，其中該第一奈米線的一部分連接至該第一輸入節點，並且該第四奈米線的一部分連接至該第二輸入節點。
  14. 一種形成一記憶體裝置的方法，該方法包括：形成連接至一第一位元線節點與一接地節點的一第一奈米線；形成一第一場效電晶體(FET)，其具有一配置在該第一奈米線上的閘極；形成一第二FET，其具有一配置在該第一奈米線上的閘極；形成連接至一電壓源節點與一第一儲存節點的一第二奈米線；形成一第三FET，其具有一配置在該第二奈米線上的閘極；形成連接至該電壓源節點與一第二儲存節點的一第三奈米線；形成一第四FET，其具有一配置在該第三奈米線上的閘極；形成連接至一第二位元線節點與該接地節點的一第四奈米線；形成一第五FET，其具有一配置在該第四奈米線上的閘極；以及形成一第六FET，其具有一配置在該第四奈米線上的閘極。
  15. 如申請專利範圍第14項之方法，其中該第一奈米線為用一等向性蝕刻製程形成的一矽奈米線，或懸浮在一基板上方。
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