TWI456758B - 具有低導通電阻之金氧半元件的幾何結構 - Google Patents

具有低導通電阻之金氧半元件的幾何結構 Download PDF

Info

Publication number
TWI456758B
TWI456758B TW096150732A TW96150732A TWI456758B TW I456758 B TWI456758 B TW I456758B TW 096150732 A TW096150732 A TW 096150732A TW 96150732 A TW96150732 A TW 96150732A TW I456758 B TWI456758 B TW I456758B
Authority
TW
Taiwan
Prior art keywords
region
drain region
substrate
gate
forming
Prior art date
Application number
TW096150732A
Other languages
English (en)
Other versions
TW200849591A (en
Inventor
Sehat Sutardja
Ravishanker Krishnamoorthy
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200849591A publication Critical patent/TW200849591A/zh
Application granted granted Critical
Publication of TWI456758B publication Critical patent/TWI456758B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Claims (17)

  1. 一種形成於一基材上的金氧半導體Metal Oxide Semiconductor,MOS)元件,該金氧半導體元件包含:一汲極區域,具有一正方形的形狀;一閘極區域,(i)其係圍繞該汲極區域並且(ii)圍繞該汲極區域形成一封閉迴圈,其中該封閉迴圈具有對應至該汲極區域的形狀之形狀;複數個源極區域,(i)其係排列成圍繞該閘極區域並(ii)與該汲極區域相對;以及複數個基板區域,(i)其係排列成圍繞該閘極區域並(ii)分隔該等源極區域,其中該汲極區域的每一邊都與該等源極區域中之一對準,且該源極區域的寬度與該汲極區域的寬度相等或較該汲極區域的寬度更寬。
  2. 如申請專利範圍第1項所述之金氧半導體元件,其中該基材具有對應至該汲極區域的形狀之形狀,並且該基板區域係排列在該基材的角落。
  3. 如申請專利範圍第1項所述之金氧半導體元件,其中一通道區域形成於該閘極區域之下。
  4. 如申請專利範圍第3項所述之金氧半導體元件,其中該通道區域配置成讓電流從每一源極區域流至該汲極區域。
  5. 如申請專利範圍第1項所述之金氧半導體元件,其中該金氧半導體元件為一電晶體。
  6. 如申請專利範圍第1項所述之金氧半導體元件,其中該基材為一矽基材,並且該閘極區域包含多晶矽。
  7. 如申請專利範圍第6項所述之金氧半導體元件,其中 該金氧半導體元件為一正方形雙擴散金氧半導體(SQDMOS)。
  8. 如申請專利範圍第1項所述之金氧半導體元件,其中:該汲極區域包含複數個汲極區域接點;該複數個源極區域中之至少一個具有複數個源極區域接點;以及該等汲極區域接點與該閘極區域間之一距離大於該等源極區域接點與該閘極區域間之一距離。
  9. 一種金氧半導體(MOS)元件,其具有在一基材上以一陣列方式形成的複數個金氧半導體電晶體單元,其中每一金氧半導體電晶體單元包含:一汲極區域,具有一正方形的形狀;一閘極區域,(i)其係圍繞該汲極區域並且(ii)圍繞該汲極區域形成一封閉迴圈,其中該封閉迴圈具有對應至該汲極區域的形狀之形狀;複數個源極區域,(i)其係排列成圍繞該閘極區域並(ii)與該汲極區域相對;以及複數個基板區域,(i)其排列成圍繞該閘極區域並(ii)分隔該等源極區域,其中該等源極區域與一相鄰金氧半導體電晶體單元的該對應源極區域重疊,且其中該汲極區域的每一邊都與該等源極區域中之一對準,且該源極區域的寬度與該汲極區域的寬度相等或較該汲極區域的寬度更寬。
  10. 一種用於在一基材上形成一金氧半導體(MOS)元件之方法,該方法包含:形成一汲極區域,具有一正方形的形狀;形成一閘極區域,其係以一封閉迴圈方式圍繞該 汲極區域,其中該封閉迴圈具有對應至該汲極區域的形狀之形狀;形成複數個源極區域,(i)其係排列成圍繞該閘極區域並(ii)與該汲極區域相對;以及形成複數個基板區域,(i)其係排列成圍繞該閘極區域並(ii)分隔該等源極區域,其中該汲極區域的每一邊都與該等源極區域中之一對準,且該源極區域的寬度與該汲極區域的寬度相等或較該汲極區域的寬度更寬。
  11. 如申請專利範圍第10項所述之方法,其中該基材具有對應至該汲極區域的形狀之形狀,並且該基板區域係排列在該基材的角落。
  12. 如申請專利範圍第10項所述之方法,其進一步包含在該閘極區域之下形成一通道區域。
  13. 如申請專利範圍第12項所述之方法,其中該通道區域配置成讓電流從每一源極區域流至該汲極區域。
  14. 如申請專利範圍第10項所述之方法,其中該基材為一矽基材,並且該閘極區域包含多晶矽。
  15. 如申請專利範圍第14項所述之方法,其中該金氧半導體元件為一正方形DMOS(SQDMOS)。
  16. 如申請專利範圍第10項所述之方法,其進一步包含在該汲極區域及該等源極區域內形成個別接點,其中該等汲極區域接點與該閘極區域間之距離大於該等源極區域接點與該閘極區域間之距離。
  17. 一種用於在一基材上形成一金氧半導體(MOS)電晶體單元之方法,其包含:在該基材上形成金氧半導體電晶體單元,其中每 一金氧半電晶體單元係由下列形成:形成一汲極區域,具有一正方形的形狀;形成一閘極區域,其係以一封閉迴圈方式圍繞該汲極區域,其中該封閉迴圈具有對應至該汲極區域的形狀之形狀;形成複數個源極區域,(i)其係排列成圍繞該閘極區域並(ii)與該汲極區域相對;以及形成複數個基板區域,(i)其係排列成圍繞該閘極區域並(ii)分隔該等源極區域,其中相鄰金氧半導體電晶體單元的該個別源極區域重疊,且其中該汲極區域的每一邊都與該等源極區域中之一對準,且該源極區域的寬度與該汲極區域的寬度相等或較該汲極區域的寬度更寬。
TW096150732A 2006-12-28 2007-12-28 具有低導通電阻之金氧半元件的幾何結構 TWI456758B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88225006P 2006-12-28 2006-12-28
US11/964,696 US9466596B2 (en) 2006-12-28 2007-12-26 Geometry of MOS device with low on-resistance

Publications (2)

Publication Number Publication Date
TW200849591A TW200849591A (en) 2008-12-16
TWI456758B true TWI456758B (zh) 2014-10-11

Family

ID=39582614

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096150732A TWI456758B (zh) 2006-12-28 2007-12-28 具有低導通電阻之金氧半元件的幾何結構

Country Status (6)

Country Link
US (1) US9466596B2 (zh)
EP (1) EP2100334B1 (zh)
JP (2) JP5360829B2 (zh)
CN (2) CN101657901B (zh)
TW (1) TWI456758B (zh)
WO (1) WO2008083180A2 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932577B2 (en) * 2007-12-31 2011-04-26 Silicon Laboratories, Inc. Circuit device and method of forming a circuit device having a reduced peak current density
US8076724B2 (en) * 2008-10-09 2011-12-13 Hvvi Semiconductors, Inc. Transistor structure having an active region and a dielectric platform region
EP2400552A1 (en) 2010-06-24 2011-12-28 Dialog Semiconductor GmbH Mos transistor structure with easy access to all nodes
CN102403310A (zh) 2010-09-13 2012-04-04 登丰微电子股份有限公司 金属氧化物半导体场效晶体管布局及结构
CN102142462B (zh) * 2011-02-25 2012-08-29 北京大学 一种非对称结构的功率mos晶体管及其阵列
WO2012158174A1 (en) * 2011-05-19 2012-11-22 Hewlett-Packard Development Company, L.P. Device active channel length/width greater than channel length/width
KR20150092828A (ko) * 2014-02-06 2015-08-17 정덕영 배터리의 충방전 제어회로를 위한 4-단자 fet
CN105097916A (zh) 2014-05-05 2015-11-25 中芯国际集成电路制造(上海)有限公司 Mos晶体管器件及其制作方法
CN104409503B (zh) * 2014-11-21 2017-05-17 中国科学院上海微系统与信息技术研究所 多叉指栅极结构mosfet的版图设计
US9356105B1 (en) * 2014-12-29 2016-05-31 Macronix International Co., Ltd. Ring gate transistor design for flash memory
EP3062349B1 (en) 2015-02-25 2019-10-09 Nxp B.V. Semiconductor device comprising a switch
CN106328508B (zh) * 2016-08-22 2019-02-01 上海华力微电子有限公司 改善有源区边界处的栅极拐角的方法
EP3352224B1 (en) * 2017-01-24 2020-03-11 Nxp B.V. Semiconductor device comprising a switch
US10811497B2 (en) 2018-04-17 2020-10-20 Silanna Asia Pte Ltd Tiled lateral BJT
US11309353B2 (en) * 2020-04-30 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer-defined back-end transistor as memory selector
CN111599807B (zh) * 2020-05-22 2023-09-01 赛卓电子科技(上海)股份有限公司 一种标准mos工艺下提升性能的差分输入对管及提升方法
CN116344530A (zh) * 2021-12-24 2023-06-27 长鑫存储技术有限公司 晶体管单元及其阵列、集成电路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW274150B (en) * 1995-10-17 1996-04-11 Winbond Electronics Corp Ring-packaged electric device

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3783349A (en) * 1971-05-25 1974-01-01 Harris Intertype Corp Field effect transistor
JPS5737875A (en) 1980-08-20 1982-03-02 Hitachi Ltd Mos semiconductor device
JPS6173481A (ja) 1984-09-19 1986-04-15 Canon Inc 画像処理装置
JPS61290767A (ja) 1985-06-19 1986-12-20 Hitachi Ltd Mos電界効果トランジスタ
US5192989A (en) * 1989-11-28 1993-03-09 Nissan Motor Co., Ltd. Lateral dmos fet device with reduced on resistance
JP2626139B2 (ja) 1990-03-08 1997-07-02 日産自動車株式会社 パワーmosfet
JPH0582782A (ja) * 1991-09-20 1993-04-02 Nippon Telegr & Teleph Corp <Ntt> Mosfet
JP2720783B2 (ja) * 1993-12-29 1998-03-04 日本電気株式会社 半導体集積回路
JP3136885B2 (ja) * 1994-02-02 2001-02-19 日産自動車株式会社 パワーmosfet
DE19581809B4 (de) * 1995-04-06 2008-12-24 Transpacific Ip, Ltd. MOS-Zelle, Mehrfachzellentransistor und IC-Chip
US5714784A (en) * 1995-10-19 1998-02-03 Winbond Electronics Corporation Electrostatic discharge protection device
TW281798B (en) 1996-03-16 1996-07-21 Winbond Electronics Corp Hexagon transistor element
JP3276325B2 (ja) 1996-11-28 2002-04-22 松下電器産業株式会社 半導体装置
JP3257969B2 (ja) 1997-07-22 2002-02-18 花王株式会社 液体柔軟仕上げ剤組成物
JPH1174505A (ja) 1997-08-27 1999-03-16 Fujitsu Ltd 半導体装置
JPH1174517A (ja) * 1997-08-29 1999-03-16 Matsushita Electric Works Ltd 半導体装置
US5965925A (en) 1997-10-22 1999-10-12 Artisan Components, Inc. Integrated circuit layout methods and layout structures
JP2002503034A (ja) 1998-02-07 2002-01-29 ゼモッド・インコーポレイテッド ソース領域を裏面に接続するプラグを含む、ラテラルrfmosデバイスのための擬似メッシュゲート構造
JPH11251445A (ja) 1998-02-27 1999-09-17 Rohm Co Ltd 半導体素子
US6064088A (en) 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
JP2000208759A (ja) 1999-01-12 2000-07-28 Rohm Co Ltd 半導体装置
EP1115158A1 (en) 2000-01-05 2001-07-11 Mitsubishi Denki Kabushiki Kaisha Soi-misfet
JP2001257360A (ja) * 2000-01-05 2001-09-21 Mitsubishi Electric Corp 半導体装置
US7115946B2 (en) 2000-09-28 2006-10-03 Kabushiki Kaisha Toshiba MOS transistor having an offset region
JP2002110970A (ja) 2000-09-28 2002-04-12 Toshiba Corp 半導体装置
JP2002246600A (ja) * 2001-02-13 2002-08-30 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6724044B2 (en) * 2002-05-10 2004-04-20 General Semiconductor, Inc. MOSFET device having geometry that permits frequent body contact
JP4158453B2 (ja) * 2002-08-22 2008-10-01 株式会社デンソー 半導体装置及びその製造方法
JP2004186511A (ja) 2002-12-04 2004-07-02 Nec Electronics Corp 静電気放電保護素子
US6798022B1 (en) * 2003-03-11 2004-09-28 Oki Electric Industry Co., Ltd. Semiconductor device with improved protection from electrostatic discharge
JP2006120952A (ja) 2004-10-22 2006-05-11 Fuji Electric Holdings Co Ltd Mis型半導体装置
JP4892847B2 (ja) 2005-03-17 2012-03-07 Dic株式会社 高分子分散型液晶表示素子用組成物及び高分子分散型液晶表示素子
JP4890793B2 (ja) * 2005-06-09 2012-03-07 トヨタ自動車株式会社 半導体装置の製造方法
EP2030237B1 (en) 2006-05-08 2011-02-09 Marvell World Trade Ltd. Efficient transistor structure
US20090072314A1 (en) 2007-09-19 2009-03-19 Texas Instruments Incorporated Depletion Mode Field Effect Transistor for ESD Protection
JP2008078469A (ja) * 2006-09-22 2008-04-03 Texas Instr Japan Ltd 電界効果トランジスタ
JP5082782B2 (ja) 2007-11-09 2012-11-28 大日本印刷株式会社 データ処理方法、icカードおよびicカードプログラム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW274150B (en) * 1995-10-17 1996-04-11 Winbond Electronics Corp Ring-packaged electric device

Also Published As

Publication number Publication date
CN102709285A (zh) 2012-10-03
CN101657901A (zh) 2010-02-24
JP5360829B2 (ja) 2013-12-04
JP2013179336A (ja) 2013-09-09
WO2008083180A3 (en) 2008-08-28
US9466596B2 (en) 2016-10-11
EP2100334A4 (en) 2011-03-23
JP5726230B2 (ja) 2015-05-27
EP2100334B1 (en) 2016-04-13
WO2008083180A2 (en) 2008-07-10
US20080157195A1 (en) 2008-07-03
EP2100334A2 (en) 2009-09-16
TW200849591A (en) 2008-12-16
JP2010515274A (ja) 2010-05-06
CN102709285B (zh) 2015-09-16
CN101657901B (zh) 2012-07-04

Similar Documents

Publication Publication Date Title
TWI456758B (zh) 具有低導通電阻之金氧半元件的幾何結構
US7528449B2 (en) Semiconductor device including ESD protective element
US8653583B2 (en) Sensing FET integrated with a high-voltage transistor
TW200616225A (en) Structure and method for making strained channel field effect transistor using sacrificial spacer
TW200629544A (en) Field effect transistor (FET) having wire channels and method of fabricating the same
EP1555688A3 (en) A multi-sided-channel finfet transistor and manufacturing method
WO2007143130A3 (en) Planar split-gate high-performance mosfet structure and manufacturing method
TW200607092A (en) Wide bandgap transistors Wide bandgap transistors with multiple field plates
TW200802802A (en) Closed cell configuration to increase channel density for sub-micron planar semiconductor power device
JP2014522114A5 (zh)
TW200746425A (en) Semiconductor transistors with expanded top portions of gates
EP1691419A3 (en) Field-effect transistor and method of manufacturing a field-effect transistor
US8901648B2 (en) MOS device with low on-resistance
TW200735357A (en) MOS device and method of fabricating a MOS device
TW200629427A (en) Transistor structure and method of manufacturing thereof
JP2009188223A5 (zh)
DE602005022561D1 (de) Verfahren zum herstellen eines halbleiterbauelements
US20170018461A1 (en) Semiconductor Device Including at Least One Lateral IGFET and at Least One Vertical IGFET and Corresponding Manufacturing Method
WO2011151681A3 (ja) 半導体装置およびこれを用いた半導体リレー
US8564062B2 (en) High voltage MOS array with gate contact on extended drain region
EP2461351A3 (fr) Cellule memoire electronique a double grille et dispositif a cellules memoires electroniques a double grille
TW200505030A (en) MOS type semi conductor device
TW200746421A (en) Semiconductor device including a channel with a non-semiconductor monolayer and associated methods
TWI602297B (zh) 垂直擴散金氧半場效電晶體
TW200703666A (en) Thin film transistor

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees