TWI602297B - 垂直擴散金氧半場效電晶體 - Google Patents

垂直擴散金氧半場效電晶體 Download PDF

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TWI602297B
TWI602297B TW100142571A TW100142571A TWI602297B TW I602297 B TWI602297 B TW I602297B TW 100142571 A TW100142571 A TW 100142571A TW 100142571 A TW100142571 A TW 100142571A TW I602297 B TWI602297 B TW I602297B
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羅翰Ｓ 布萊斯維特
藍迪Ｌ 葉奇
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微晶片科技公司
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Description

垂直擴散金氧半場效電晶體
本申請案係關於一種垂直擴散金屬氧化物半導體(DMOS)場效電晶體(FET)。
本申請案主張2010年11月23日申請之題為「LOW CAPACITANCE VERTICAL GATE-FIELD EFFECT TRANSISTOR」的美國臨時申請案第61/416,638號之權利，該申請案之全文併入本文中。
與積體電路中之橫向電晶體相比，功率金屬氧化物半導體場效電晶體(MOSFET)一般用以處置高功率位準。圖6展示使用垂直擴散MOSFET結構(亦稱為雙擴散MOSFET結構(DMOS或VDMOS))之典型MOSFET。
如所展示，例如，在圖6中，在N+基板415上形成有N-磊晶層，該N-磊晶層之厚度及摻雜一般判定裝置之電壓額定值。自頂部至磊晶層410中，形成有N+摻雜之左方源極區430及右方源極區430，該等源極區430由形成P基極之P摻雜區420圍繞。P基極可具有圍繞P基極420之向外擴散區域425。源極接點460一般在晶粒之表面上接觸區430及420兩者且一般由連接左方源極區及右方源極區兩者之金屬層形成。絕緣層450(通常為二氧化矽或任何其他合適材料)使覆蓋P基極區420及向外擴散區域425之部分的多晶矽閘極440絕緣。閘極440連接至通常由另一金屬層形成之閘極接點470。此垂直電晶體之底側具有形成汲極接點480之另一金屬層405。總之，圖6展示可為極小的且包含共同汲極、共同閘極以及兩個源極區及兩個通道的MOSFET之典型基本單元。其他類似單元可用於垂直功率MOS-FET中。複數個此等單元可一般並聯地連接以形成功率MOSFET。
在接通狀態中，通道形成於區420及區425之由閘極覆蓋之區域內，自表面分別到達至區420及區425中。因此，如由水平箭頭所指示，電流可流動。單元結構需要提供閘極440之足夠寬度d以允許此電流變成流動至汲極側的垂直電流，如由垂直箭頭所指示。
歸因於特定地在高頻率切換應用(諸如，切換模式電源供應器)中不合需要之閘極的必要寬度，此等結構具有相對較高之閘極源極電容。
根據一實施例，一種具有一單元結構之垂直擴散金屬氧化物半導體(DMOS)場效電晶體(FET)可包含：一第一導電類型之一基板，其形成一汲極區；在該基板上之該第一導電類型之一磊晶層；在該磊晶層內之該第二導電類型之第一基極區及第二基極區，該等基極區間隔開一預定義距離；一第一導電類型之第一源極區及第二源極區，其分別配置於該第一基極區及該第二基極區中，其中該第一基極區及該第二基極區可操作以在該源極區與該磊晶層之間形成第一橫向通道及第二橫向通道；一閘極結構，其藉由一絕緣層而與該磊晶層絕緣且配置於該第一基極區與該第二基極區之間的區上方，且其中該閘極結構包含第一閘極區及第二閘極區，每一閘極區僅覆蓋分別在該第一基極區及該第二基極區內之該第一通道及該第二通道。
根據另一實施例，該絕緣層可包含一閘極氧化物層，在該閘極氧化物層之上沈積及圖案化一厚氧化物層。根據另一實施例，該厚氧化物層可經圖案化以在該第一源極區與該第二源極區之間形成一台座(pedestal)。根據另一實施例，該垂直DMOS-FET可進一步包含在該第一基極區與該第二基極區之間的該第二導電類型之一輕微摻雜區域，該輕微摻雜區域自表面延伸至該磊晶層中。根據另一實施例，該垂直DMOS-FET可進一步包含在該第一基極區與該第二基極區之間的一沈降區，該沈降區自表面延伸至該磊晶層中。根據另一實施例，該垂直DMOS-FET可進一步包含一源極金屬層，該源極金屬層連接該第一源極區及該第二源極區與該第一基極區及該第二基極區。根據另一實施例，該垂直DMOS-FET可進一步包含該第二導電類型之第一擴散區域及第二擴散區域，該第一擴散區域及該第二擴散區域分別圍繞該第一基極區及該第二基極區。根據另一實施例，該閘極結構可包含一橋接區段，該橋接區段連接該第一閘極與該第二閘極且相比該第一閘極及該第二閘極而與該磊晶層間隔開更遠。根據另一實施例，該橋接區域可配置於該單元結構之外部。根據另一實施例，該第一閘極及該第二閘極可藉由導線接合來連接。根據另一實施例，該垂直DMOS-FET可進一步包含在該基板之背面上的一汲極金屬層。根據另一實施例，該單元結構或複數個單元結構可形成於一積體電路裝置中。根據另一實施例，該積體電路裝置可提供用於一切換模式電源供應器之控制功能。根據另一實施例，該第一導電類型可為P型且該第二導電類型為N型。根據另一實施例，該第一導電類型可為N型且該第二導電類型為P型。
根據另一實施例，一種用於製造一垂直擴散金屬氧化物半導體(DMOS)場效電晶體(FET)之一單元結構的方法可包含：在配置於一第一導電類型之一基板上的一第一導電類型之一磊晶層中的一第二導電類型之一第一基極區及第二基極區內形成一單元結構，該單元結構包含一第一導電類型之第一源極區及第二源極區，其中該第一基極區及該第二基極區間隔開一預定義距離，且其中該第一基極區及該第二基極區可操作以在該源極區與該磊晶層之間形成第一橫向通道及第二橫向通道；在該第一基極區與該第二基極區之間在該磊晶層之上形成具有一台座之一閘極絕緣層；在該台座之側壁上形成覆蓋該第一通道及該第二通道之第一閘極及第二閘極。
根據該方法之另一實施例，該形成一閘極絕緣層之步驟可包含：沈積一薄閘極氧化物層；在該薄閘極氧化物層之上沈積一厚氧化物層；及蝕刻該厚氧化物層以形成該台座。根據該方法之另一實施例，該方法可進一步包含在該第一基極區與該第二基極區之間形成自該磊晶層之表面延伸至該磊晶層中的一輕微摻雜區。根據該方法之另一實施例，該形成該第一閘極及該第二閘極之步驟可提供一閘極結構之連接該第一閘極與該第二閘極的一橋接區域。根據該方法之另一實施例，該橋接區域可位於該單元結構之外部。根據該方法之另一實施例，該方法可進一步包含藉由一金屬層連接該第一閘極與該第二閘極。根據該方法之另一實施例，該方法可進一步包含藉由導線接合來連接該第一閘極與該第二閘極。根據該方法之另一實施例，該方法可進一步包含在該第一基極區與該第二基極區之間的中心區域中形成自該磊晶層之表面延伸至該基板的一沈降結構。
圖1展示根據各種實施例之垂直DMOS-FET之橫截面圖。提供高度摻雜之N+基板115，在高度摻雜之N+基板115之上已成長有N-磊晶層110。自頂部至磊晶層110中，形成有N+摻雜之左方源極區130及右方源極區130，該等源極區130各自由形成P基極之P摻雜區120圍繞。可在P基極120內植入較重摻雜之P+區135以用於連接至源極端子。如由點線所指示，每一P基極120可另外由相關聯之向外擴散區域125圍繞。可使用用於左方源極區130及右方源極區130之其他結構。與圖6中所展示之電晶體類似，源極接點160一般在晶粒之表面上接觸區130及區120兩者且一般由連接左方源極區及右方源極區兩者之金屬層形成。絕緣結構140用以使左方閘極152及右方閘極154絕緣。根據一實施例，此結構140包含在電晶體之多晶矽閘極152、154下方的閘極氧化物層142，如由點劃線所指示。可使用沈積之氧化物，後續接著密化沈積之氧化物142使得其更穩固的熱氧化來形成此閘極氧化物層142。
與習知垂直DMOS-FET相反，絕緣結構140包含沈積及遮罩於此閘極氧化物層140上之另一厚絕緣層145，該厚絕緣層145覆蓋右方P基極120與左方P基極120之間的中間空間。根據一實施例，在切割至源極130/135之接點之前沈積此厚氧化物145。此另一絕緣層145可為亦幫助分離金屬接點與閘極電極之金屬間介電質(IMD)。此處，厚絕緣層145經遮罩及蝕刻以在層142上形成左方及右方階部，且因此在中心形成台座區域，如下文將更詳細解釋。接著在絕緣層142之右方及左方薄部分上沿著絕緣結構140之台座區段145之側壁藉由多晶矽形成右方閘極152及左方閘極154。右方閘極152及左方閘極154各自覆蓋各別左方及右方P基極區120之部分。因此，在將適當電壓施加至閘極接點及源極接點之情況下，左方通道及右方通道可形成於P基極區120內。在台座145之上藉由橋接區域156使閘極152與閘極154互連。台座145足夠厚以避免橋接區域顯著影響閘極電容。因此，根據各種實施例，所提議之單元結構不僅建立兩個源極區120、130、135及兩個通道，而且建立兩個多晶矽閘極152及154。根據其他實施例，如由圖1中之虛線所展示，可在左方P基極區與右方P基極區之間的中心區段中提供輕微摻雜區域190，該區域190自頂表面延伸至磊晶層110中。此垂直電晶體之底側再次具有形成汲極接點180之另一金屬層105。
窄閘極152、154之小的佔據面積提供極小閘極電容。因此，所得個別閘極-源極電容及閘極-汲極電容總體上有效地比如(例如)圖6中所展示之習知垂直DMOS-FET之各別閘極電容小得多。因此，各種實施例有效地提供兩個渠溝閘極152、154，其中橋接區域156與磊晶層110間隔開以僅就閘極電容而言不具有顯著影響。如下文將更詳細解釋，亦可完全省略橋接區域156或將其配置於單元區域之外部。
圖2展示另一實施例。功率電晶體單元之一般結構可與圖1中所展示之實施例相同。另外，沈降結構210(例如，多晶矽沈降區)可形成於左方P基極區120與右方P基極區120之間的區之中心中，自磊晶層110之頂表面延伸至基板115。沈降植入物210用以在裝置處於完全操作中時提供低電阻路徑以用於電流流動。沈降植入物210亦幫助減少裝置之Rdson(汲極源極導通電阻)，此係因為沈降植入物210將有效地在局部減少N-磊晶膜110之電阻。
圖3展示在已形成金屬層310之後的圖2之單元。金屬層310提供源極區130與相鄰接觸分區140之電連接，從而有效地連接P基極120與源極。金屬層310亦連接左方及右方源極區130、140以及其他單元之源極區。
圖4A展示由厚絕緣層145圍繞且擱置在閘極氧化物層142之上的窄渠溝閘極154。根據如圖4B中所展示之另一實施例，沈積單一閘極氧化物層140且渠溝158形成於此層140內。
圖5A至圖5E展示用於製造如圖1中所展示之裝置的例示性程序步驟。然而，根據所應用之技術，其他步驟可適合於產生類似裝置。如圖5A中所展示，在重摻雜之N+基板115上成長N-摻雜之磊晶層110。在磊晶層110之上沈積氧化物層142，諸如二氧化矽或任何其他適當的閘極氧化物層。可使用沈積之氧化物，後續接著密化沈積之氧化物142使得其更穩固的熱氧化來形成此閘極氧化物層142。如圖5B中所展示，接著在閘極氧化物142上沈積厚絕緣氧化物層145(諸如，金屬間介電層)。可如圖5B中所展示圖案化厚絕緣層145且可藉由熟知擴散技術在磊晶層110中形成P摻雜之基極區120。如圖5C中所展示，接著再次藉由厚氧化物層145覆蓋P基極區且在厚氧化物層145內形成窄渠溝510。如圖5D中所展示，可接著在該層之上沈積多晶矽層且可藉由適當遮罩及蝕刻技術圖案化多晶矽層以形成具有反轉U形之閘極結構。此閘極結構150可接著用作遮罩以切斷連接左方源極區130、135與右方源極區130、135之金屬層131的金屬連接通孔。因此，單元結構可自對準。此外，圖5E展示在已沈積接觸源極之金屬層131及接觸汲極區115之背面金屬層105之後的單元。
根據一實施例，亦可在一單一步驟中執行圖案化閘極絕緣結構140以形成閘極結構150之步驟。因此，不需要額外程序步驟。然而，根據其他實施例，例如，在提供圖4A中所展示之渠溝閘極結構時或在部分地移除橋接區域156以在單元結構區域之外部連接閘極152與閘極154的情況下，可使用一個以上步驟。
該單元結構可為如圖1至圖3中所展示之條帶結構。然而，根據其他實施例可使用正方形單元、六邊形形狀或可應用各種實施例之原理的任何其他合適之單元形狀。該單元結構或複數個單元可用以在積體電路內或在離散電晶體裝置中形成功率DMOS-FET。此積體電路可提供用於切換模式電源供應器中之控制電路。因此，外部功率電晶體可為不必要的。
此外，例示性實施例展示具有適當導電類型之不同區的P通道裝置。熟習此項技術者應瞭解，本申請案之實施例不限於P通道裝置，而是亦可應用於N通道裝置。
105．．．金屬層/背面金屬層
110．．．N-磊晶層/N-磊晶膜/N-摻雜之磊晶層
115．．．N+基板/汲極區
120．．．左方P基極區/右方P基極區/P摻雜區/P摻雜之基極區
125．．．向外擴散區域
130．．．左方源極區/右方源極區
135．．．左方源極區/右方源極區/較重摻雜之P+區
140．．．相鄰接觸分區/閘極絕緣結構
142．．．閘極氧化物層/沈積之氧化物/絕緣層
145．．．厚絕緣層/厚絕緣氧化物層/台座區段/台座
150．．．閘極結構
152．．．多晶矽閘極/窄閘極/渠溝閘極/右方閘極
154．．．多晶矽閘極/窄閘極/渠溝閘極/左方閘極
156．．．橋接區域
158．．．渠溝
160．．．源極接點
180．．．汲極接點
190．．．輕微摻雜區域
210．．．沈降結構/沈降植入物
310．．．金屬層
405．．．金屬層
410．．．磊晶層
415．．．N+基板
420．．．P摻雜區/P基極區/P基極
425．．．向外擴散區域
430．．．N+摻雜之左方源極區/N+摻雜之右方源極區
440．．．多晶矽閘極
450．．．絕緣層
460．．．源極接點
470．．．閘極接點
480．．．汲極接點
510．．．窄渠溝
圖1展示經改良之垂直DMOS-FET的第一實施例；
圖2展示經改良之垂直DMOS-FET的第二實施例；
圖3展示經改良之垂直DMOS-FET的第三實施例；
圖4A、圖4B展示根據各種實施例之閘極的更詳細視圖；
圖5A至圖5E展示根據各種實施例之用於製造裝置的若干例示性程序步驟；及
圖6展示習知垂直DMOS-FET。
105．．．金屬層/背面金屬層
110．．．N-磊晶層/N-磊晶膜/N-摻雜之磊晶層
115．．．N+基板/汲極區
120．．．左方P基極區/右方P基極區/P摻雜區/P摻雜之基極區
125．．．向外擴散區域
130．．．左方源極區/右方源極區
135．．．左方源極區/右方源極區/較重摻雜之P+區
140．．．相鄰接觸分區/閘極絕緣結構
142．．．閘極氧化物層/沈積之氧化物/絕緣層
145．．．厚絕緣層/厚絕緣氧化物層/台座區段/台座
150．．．閘極結構
152．．．多晶矽閘極/窄閘極/渠溝閘極/右方閘極
154．．．多晶矽閘極/窄閘極/渠溝閘極/左方閘極
156．．．橋接區域
160．．．源極接點
180．．．汲極接點
190．．．輕微摻雜區域

Claims (11)

  1. 一種具有一單元結構之垂直擴散金屬氧化物半導體(DMOS)場效電晶體，其包含如下單元結構：一第一導電類型之一基板，其形成一汲極區；在該基板上之該第一導電類型之一磊晶層；在該磊晶層內之一第二導電類型之第一基極區及第二基極區，該等第一及第二基極區間隔開一距離；一第一導電類型之第一源極區及第二源極區，其分別配置於該第一基極區及該第二基極區中，其中該第一基極區及該第二基極區可操作以在該源極區與該磊晶層之間形成第一橫向通道及第二橫向通道；一金屬層，其與該第一源極區及該第二源極區連接；及一閘極結構，其藉由一絕緣層而與該磊晶層絕緣且配置於該第一基極區與該第二基極區之間的區上方，且其中該閘極結構包含第一閘極區及第二閘極區，該第一閘極區及該第二閘極區每一者形成一第一閘極及一第二閘極，每一閘極區僅覆蓋分別在該第一基極區及該第二基極區內之該第一橫向通道及該第二橫向通道，其中該絕緣層包含一閘極氧化物層，在該閘極氧化物層之上配置及圖案化一厚氧化物層以在該第一源極區與該第二源極區之間形成一台座(pedestal)，且其中該閘極結構係U形且圍繞該台座藉此減少一閘極源極電容，其中僅由該U形閘極結構之一第一垂直側壁及一第二 垂直側壁形成該第一閘極及該第二閘極，且其中該第一垂直側壁及該第二垂直側壁具有由一渠溝所界定之一厚度，且具有該渠溝之該厚度的水平底端面分別形成該第一閘極及該第二閘極且分別覆蓋該第一橫向通道及該第二橫向通道且其中藉由一厚絕緣層而將該閘極結構與該金屬層絶緣以使得該閘極源極電容不增加，其中該U形閘極結構包含一橋接區段，該橋接區段連接該第一閘極區與該第二閘極區且相比該第一閘極及該第二閘極與該磊晶層間隔開更遠，使得該橋接區段配置在該單元結構之外。
  2. 如請求項1之垂直DMOS場效電晶體，其進一步包含在該第一基極區與該第二基極區之間的該第二導電類型之一輕微摻雜區域，該輕微摻雜區域自表面延伸至該磊晶層中。
  3. 如請求項1之垂直DMOS場效電晶體，其進一步包含在該第一基極區與該第二基極區之間的一沈降區，該沈降區自表面延伸至該磊晶層中。
  4. 如請求項1之垂直DMOS場效電晶體，其中該金屬層連接該第一源極區及該第二源極區與該第一基極區及該第二基極區。
  5. 如請求項1之垂直DMOS場效電晶體，其進一步包含該第二導電類型之第一擴散區域及第二擴散區域，該第一擴散區域及該第二擴散區域分別圍繞該第一基極區及該第二基極區。
  6. 一種積體電路裝置，其包含如請求項1至5中任一項之該單元結構或複數個單元結構。
  7. 如請求項6之積體電路裝置，其中該積體電路裝置提供用於一切換模式電源供應器之控制功能。
  8. 一種用於製造一DMOS場效電晶體之一單元結構之方法，其包含：形成一單元結構，該單元結構包含第一源極區及第二源極區，該第一及第二源極區配置於一第一導電類型之一基板上的一第一導電類型之一磊晶層中的一第二導電類型之一第一基極區及第二基極區內，其中該第一基極區及該第二基極區間隔開一距離，且其中該第一基極區及該第二基極區可操作以在該源極區與該磊晶層之間形成第一橫向通道及第二橫向通道；藉由下列步驟在該第一基極區與該第二基極區之間在該磊晶層之上形成具有一台座之一閘極絕緣層：沈積一薄閘極氧化物層，在該薄閘極氧化物層之上沈積一厚氧化物層，及蝕刻該厚氧化物層以形成該台座及第一渠溝及第二渠溝；在該第一渠溝及該第二渠溝中形成第一閘極及第二閘極，其中該等渠溝之終端部分係經配置以覆蓋該第一基極區及該第二基極區之通道部分，其中該閘極結構係U形且圍繞該台座，且其中僅由該U形閘極結構之一第一垂直側壁及一第二垂直側壁形成該第一閘極及該第二閘極，且其中該第一垂直側壁及該第二垂直側壁具有由一 渠溝所界定之一厚度，且具有該渠溝之該厚度的水平底端面分別形成該第一閘極及該第二閘極且分別覆蓋該第一橫向通道及該第二橫向通道；及將一金屬層與該第一源極區及該第二源極區連接，其中提供在該閘極結構與該金屬層之間之一厚絕緣層藉此不增加一閘極源極電容，其中該U形閘極結構包含一橋接區段，該橋接區段連接該第一閘極區與該第二閘極區且相比該第一閘極及該第二閘極與該磊晶層間隔開更遠，使得該橋接區段配置在該單元結構之外。
  9. 如請求項8之方法，其中該形成該第一閘極及該第二閘極之步驟進一步包含形成連接該第一閘極與該第二閘極的一橋接區域。
  10. 如請求項9之方法，其中藉由將多晶矽沈積於該厚氧化物層上並將多晶矽沈積至該第一渠溝及該第二渠溝中來形成該第一閘極及該第二閘極與該橋接區域。
  11. 如請求項8至10中任一項之方法，其進一步包含在該第一基極區與該第二基極區之間的中心區域中形成自該磊晶層之表面延伸至該基板的一沈降結構。
TW100142571A 2010-11-23 2011-11-21 垂直擴散金氧半場效電晶體 TWI602297B (zh)

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US9087920B2 (en) 2012-06-01 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical power MOSFET and methods of forming the same
CN106920837B (zh) * 2015-12-25 2020-02-07 无锡华润华晶微电子有限公司 一种垂直双扩散金属氧化物半导体器件及其制作方法
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US6870221B2 (en) * 2002-12-09 2005-03-22 Semiconductor Components Industries, Llc Power switching transistor with low drain to gate capacitance

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