TWI518911B - 垂直dmos電晶體 - Google Patents

垂直dmos電晶體 Download PDF

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Publication number
TWI518911B
TWI518911B TW102146870A TW102146870A TWI518911B TW I518911 B TWI518911 B TW I518911B TW 102146870 A TW102146870 A TW 102146870A TW 102146870 A TW102146870 A TW 102146870A TW I518911 B TWI518911 B TW I518911B
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Taiwan
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trench
region
transistor
layer
sidewall
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TW102146870A
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TW201427024A (zh
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秀明土子
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萬國半導體股份有限公司
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Description

垂直DMOS電晶體
本發明是有關於半導體元件，特別是垂直DMOS電晶體。
由於橫向雙擴散金屬-氧化物-半導體(LDMOS)電晶體的高擊穿電壓性能，以及對於低壓元件的CMOS技術相容，因此通常用於高壓元件(<10V至>1000V)。第1圖表示傳統的低端N-型LDMOS電晶體的剖面圖。眾所周知，增大漂流區的長度(用距離“d”表示)，LDMOS電晶體的擊穿電壓也可以相應地增大。
第2圖表示傳統的溝槽MOSFET元件的剖面圖。在溝槽MOSFET元件中，閘極電極形成在溝槽中，通道形成在沿溝槽側壁的垂直區中。因此，溝槽MOSFET元件是垂直電晶體元件，源極區在元件的頂部，汲極端在元件的背部。Williams等人發明的美國專利7,576,391也提出了一種橫向溝槽MOSFET元件，用於控制通道電流的溝槽閘極在刻蝕後溝槽的側邊垂直向下。
本發明提供一種垂直DMOS電晶體，增強了電晶體元件的強度和可靠性，電晶體元件可以擁有很寬的安全操作區，可以調節溝槽深 度和側壁汲極延伸物的摻雜水準，優化汲極節點和漏源導通電阻RdsON所載入的最高電壓，而不會使元件間距明顯增大，准垂直DMOS電晶體可以整合或作為單獨的元件。
依據本發明的原理，准垂直雙擴散MOS(DMOS)電晶體包含沿溝槽側壁的垂直汲極電流通路。該溝槽可以引入導電場效電板，或者配置成溝槽汲極電極。在一些實施例中，垂直汲極電流通路連接到掩埋摻雜區，掩埋摻雜區將汲極電流水準引至溝槽汲極電極，構成頂端汲極電極。憑藉頂端汲極電極，可以作為積體電路的一部分，整合准垂直DMOS電晶體。准垂直DMOS電晶體也可以作為帶有背部汲極電極的單獨元件。
依據本發明的另一方面，製備NMOS電晶體，汲極延伸物在沿溝槽側壁的垂直汲極電流通路中。汲極延伸物具有降低閘極電極邊緣處的汲極電壓的作用，藉以使低壓NMOS電晶體可以接通或斷開汲極節點上所載入的高壓，而不會影響元件的可靠性。
在本發明的實施例中，准垂直DMOS電晶體包含橫向通道，形成在閘極電極下方的半導體本體中，藉由閘極電介質層，與閘極電極絕緣。溝槽形成在閘極電極的汲極端，並在此處形成輕摻雜的側壁區，藉以沿溝槽側壁提供高電阻率的汲極延伸物通路。來自於橫向通道的汲極電流在溝槽側壁處拐彎，汲極電流沿輕摻雜側壁區傳導，構成垂直汲極電流通路。在這種情況下，延伸後的汲極漂流區形成在摻雜汲極電流通路中，以提高准垂直DMOS電晶體的擊穿電壓。
在一些實施例中，垂直電流通路連接到掩埋摻雜區，例如掩埋層，將汲極電流水準引至溝槽汲極電極。溝槽汲極電極作為導電填充溝槽，可以位於每個准垂直DMOS電晶體結構或並聯准垂直DMOS電晶體結構陣列的預定義間隔處。
准垂直DMOS電晶體結構與傳統的橫向或垂直DMOS電晶體元件相比，具有很多優勢。首先，本發明所述之准垂直DMOS電晶體具有很深的結，在溝槽底部而不是在閘極邊緣處擊穿。因此，閘極電極的汲極邊緣無法承受過高的電壓。高電場位於P-阱本體的底部。在這種情況下，熱載流子注入被提升。藉以增強了電晶體元件的強度和可靠性，電晶體元件可以擁有很寬的安全操作區。此外，可以調節溝槽深度和側壁汲極延伸物的摻雜水準，優化汲極節點和漏源導通電阻RdsON所載入的最高電壓，而不會使元件間距明顯增大。例如，較深的溝槽和較輕摻雜的側壁區可以增大汲極節點的擊穿電壓。同時，准垂直DMOS電晶體的RdsON*面積比傳統的橫向DMOS或LDMOS電晶體的RdsON*面積更小。此外，准垂直DMOS電晶體可以整合或作為單獨的元件。例如，准垂直DMOS電晶體可以整合在功率積體電路中，用作片上功率FET。在這種情況下，可以利用頂部溝槽汲極電極連接到掩埋層，掩埋層連接到垂直汲極電流通路，用於並聯電晶體陣列。更可選擇，准垂直DMOS電晶體可以作為單獨的元件，更可以作為N-型或P-型元件。對於N-通道DMOS電晶體來說，單獨的元件可以形成在帶有N-型外延層的N+基板上。
100、100A、200、250、50、50A‧‧‧qVDMOS電晶體
110、270、370、470、70、80‧‧‧溝槽
117、276、376、476、76‧‧‧側壁氧化層
122：82‧‧‧摻雜區
128、284、484、84‧‧‧溝槽汲極電極
152‧‧‧節點
154‧‧‧共同節點
156‧‧‧輸出節點
158‧‧‧負載
257、58‧‧‧P-阱
272、372、472、72‧‧‧摻雜側壁區
274‧‧‧底部氧化層
278、378、78‧‧‧多晶矽層
282‧‧‧底部摻雜區
300、300A、400、400A‧‧‧NMOS電晶體
367、467‧‧‧汲極擴散區
374、74‧‧‧氧化層
482‧‧‧溝槽底部擴散區
52‧‧‧基板
54‧‧‧掩埋層
56‧‧‧外延層
60‧‧‧閘極電介質層
62‧‧‧閘極電極
64‧‧‧墊片
65‧‧‧輕摻雜擴散區
66‧‧‧N+源極區
68‧‧‧P+本體接觸區
以下的詳細說明及圖式提出了本發明的各個實施例。
第1圖表示一種傳統的低端N-型LDMOS電晶體的剖面圖。
第2圖表示一種傳統的溝槽MOSFET元件的剖面圖。
第3圖表示依據本發明的一個實施例，一種引入溝槽導電場效電板的准垂直DMOS電晶體元件的剖面圖。
第4圖表示依據本發明的一個實施例，一種引入溝槽汲極電極的准垂直DMOS電晶體元件的剖面圖。
第5圖表示一個在同步降壓變換器中的開關電路的電路圖。
第6圖表示依據本發明的一個實施例，引入不帶有掩埋層的qVDMOS電晶體以及帶有掩埋層的qVDMOS電晶體的積體電路剖面圖。
第7圖表示依據本發明的一個實施例，在中間製程步驟中，一種帶有汲極延伸物的NMOS電晶體的剖面圖。
第8圖表示依據本發明的一個實施例，一種帶有汲極延伸物的NMOS電晶體的剖面圖。
第9圖表示依據本發明的一個可選實施例，一種帶有汲極延伸物的NMOS電晶體的剖面圖。
本發明可以以各種方式實現，包含作為一個製程；一種裝置；一個系統；和/或一種物質合成物。在本說明書中，這些實現方式或本發明可能採用的任意一種其他方式，都可以稱為技術。一般來說，可以在本發明的範圍內變換製程步驟的順序。
本發明的一個或多個實施例的詳細說明以及圖式解釋了本發明的原理。雖然，本發明與這些實施例一起提出，但是本發明的範圍並不局限於任何實施例。本發明的範圍僅由申請專利範圍限定，本發明包含多種可選手段、修正以及等效手段。在以下說明中，所提出的各種具體細節用於全面理解本發明。這些細節用於解釋說明，無需這些詳細細節中的部分細節或全部細節，依據申請專利範圍，就可以實現本發明。為了簡便， 本發明相關技術領域中眾所周知的技術材料並沒有詳細說明，以免對本發明產生不必要的混淆。
第3圖表示依據本發明的一個實施例，一種引入溝槽導電場效電板的准垂直DMOS電晶體元件的剖面圖。參見第3圖，准垂直DMOS(qVDMOS)電晶體50形成在P-型基板52上，N-型掩埋層(N-BL)54也形成在上面，作為掩埋摻雜區。外延層56形成在P-基板52上。外延層56可以是N-型外延層或P-型外延層。當使用P-型外延層時，可以藉由離子注入或擴散和退火，將外延層轉換成輕摻雜N-型區。構成qVDMOS電晶體本體區的P-阱58，形成在外延層56上，例如藉由離子注入。然後，P-阱58本體退火。在外延層56上方形成閘極電介質層60，在閘極電介質層上方形成閘極電極62。閘極電極62與P-阱58本體部分重疊，並且延伸到P-阱58本體上方。輕摻雜擴散(LDD)區65自對準到閘極電極62之後，在閘極電極的旁邊，形成側壁墊片64。重摻雜N+源極區66和重摻雜P+本體接觸區68形成在qVDMOS電晶體50的源極端。在大多數的應用中，N+源極區66和P+本體接觸區68通常短接在一起。
然後，在qVDMOS電晶體50的汲極端形成溝槽70。溝槽70內襯很薄的側壁氧化層76，可以藉由沉積或熱生長製備側壁氧化層76。在溝槽70中，進行N-型注入，包含側壁和帶角度的注入，以便在N-外延層56中形成N-型摻雜側壁區72，並且在溝槽底部形成N-型摻雜區。在本發明的實施例中，N-型摻雜側壁區72為輕摻雜側壁區。在一個實施例中，摻雜側壁區72的摻雜濃度低於P-阱58本體的摻雜水準。在一些實施例中，摻雜側壁區72的摻雜濃度在1015/cm3至1017/cm3的範圍內。在一個實施例中，摻雜側壁區72的摻雜濃度大約為1016/cm3。
然後，在溝槽底部，用厚氧化層74填充溝槽70。選取厚氧 化層74的厚度，以增大擊穿電壓，同時降低柵漏電容。在本實施例中，用多晶矽層78填充溝槽70。多晶矽層78起溝槽導電場效電板的作用，這將在下文中詳細介紹。因此，所製成的輕摻雜側壁區72構成汲極延伸區或汲極漂流區，以提高qVDMOS電晶體的擊穿電壓。
在本發明的可選實施例中，溝槽70以及之後的注入和沉積，可以在製備多晶矽閘極電極之前進行。
在本發明的實施例中，可以複製基本的qVDMOS電晶體50結構，以構成並聯qVDMOS電晶體的陣列，以提高電晶體元件的電流載流能力。在第3圖中，在溝槽70的另一邊，製備qVDMOS電晶體50結構的鏡像qVDMOS電晶體50A。可以複製相同的基本qVDMOS電晶體50、50A結構，以製備並聯qVDMOS電晶體的陣列，每一對電晶體都具有共同的溝槽。
在本實施例中，沿溝槽70的側壁形成的輕摻雜側壁區72,電連接到掩埋層54。因此，掩埋層54將所有的qVDMOS電晶體的垂直汲極電流通路電連接起來，藉以形成在N-外延層56中。在一個實施例中，利用連接到掩埋層54上的溝槽汲極電極84，製備頂端汲極電極，例如在遠離qVDMOS電晶體陣列的位置處。如第3圖所示，藉由溝槽80製備溝槽汲極電極84，其中內襯側壁絕緣層(例如側壁氧化層)的溝槽80，並用導電層(例如鎢或鋁)填充溝槽80。一般來說，(例如藉由離子注入形成的)摻雜區82形成在溝槽80的底部，以增強溝槽中導電層和掩埋層54之間的歐姆接觸。
在本實施例中，用多晶矽填充qVDMOS電晶體50的溝槽70，構成溝槽多晶矽場效電板，作為溝槽導電場效電板。在本發明的實施例中，溝槽多晶矽層78導電連接到qVDMOS電晶體的閘極電極或源極電 極。可以藉由不同的方式完成導電連接，例如藉由金屬互連或多晶矽互連。
將溝槽導電場效電板連接到閘極電極的特殊優勢在於，降低了qVDMOS電晶體的漏源導通電阻RdsON。更確切地說，當qVDMOS電晶體50接通時，閘極電壓處於邏輯上的高級別(例如5V)，而汲極電壓處於低級別(例如0V左右)。當溝槽多晶矽層78連接到閘極電極時，溝槽多晶矽層78也偏置到邏輯上的高級別(例如5V)。因此，當偏置時，摻雜側壁區72積聚電子，藉以降低汲極延伸區的電阻。因此，將溝槽導電場效電板連接到閘極電勢，可以降低qVDMOS電晶體的導通電阻RdsON。
當溝槽導電場效電板電連接到閘極電極時，柵漏重疊電容會增大。當用於高速開關元件時，增大後的電容可以提高qVDMOS電晶體的開關速度。然而，當qVDMOS晶體管用於低速開關元件時，例如2MHz以下時，柵漏重疊電容不會明顯增大。
當需要很高的開關速度而且可以承受較高的RdsON導通電阻時，溝槽導電場效電板可以電連接到源極端。當場效電板電連接到源極端時，場效電板摻雜區並不處於累加態。導通電阻RdsON沒有降低，而柵漏重疊電容達到最小值，因此所形成的qVDMOS電晶體可以在很高的開關速度下工作。
在第3圖所示的qVDMOS電晶體中，每個電晶體晶胞的垂直汲極電流通路都連接到N-掩埋層54，N-掩埋層54將汲極電流水準傳輸到溝槽汲極電極84。在本發明的實施例中，可以藉由改變N-掩埋層54的摻雜等級，以及改變溝槽汲極電極84的位置，來調節汲極延伸通路的電阻。例如根據N-掩埋層54的摻雜等級和電阻，對於指定數量的qVDMOS 電晶體，可以包含溝槽汲極電極84。根據N-掩埋層54的電阻和並聯元件陣列的導通電阻RdsON，可以增大或減小溝槽汲極電極84的數量或間距。
第4圖表示依據本發明的一個實施例，一種引入溝槽汲極電極的准垂直DMOS電晶體元件的剖面圖。參見第4圖，qVDMOS電晶體100的製備方式與第3圖所示的qVDMOS電晶體50的製備方式相同，垂直汲極電流通路形成在溝槽110的N-型輕摻雜側壁區72中。然而，在qVDMOS電晶體100中，並沒有將導電場效電板製備在溝槽110中，而是利用溝槽110製備溝槽汲極電極128。在這種情況下，qVDMOS電晶體100的每個電晶體結構處都有汲極電極。
更確切地說，製備溝槽110之後，藉由離子注入，在溝槽110底部製備摻雜區122。摻雜區122降低了掩埋層54和後來形成的汲極導電層之間的接觸電阻，在它們之間形成歐姆接觸。然後，用側壁氧化層117內襯溝槽110。側壁氧化層117比導電場效電板所用的側壁氧化層76更厚。側壁氧化層117必須足夠厚，才能使汲極電極與形成在摻雜側壁區72中的汲極延伸區電絕緣。然後，用鋁或鎢等導電材料填充溝槽110，形成溝槽汲極電極128。
可以鏡像基本的qVDMOS電晶體100結構，以製備qVDMOS電晶體100的鏡像qVDMOS電晶體100A，它們共用同溝槽汲極電極128。可以重複qVDMOS電晶體100結構及鏡像qVDMOS電晶體100A，形成VDMOS電晶體的陣列，qVDMOS電晶體的每個部分或每個帶都製備汲極電極。
這樣一來，汲極電流流經輕摻雜側壁區72中的垂直汲極電流通路，流至N-掩埋層54，然後藉由溝槽汲極電極128起動汲極電流。 由於汲極電流起動非常靠近垂直汲極電流通路，因此N-掩埋層54在汲極電流通路中引起的電阻降低。
在第3圖和第4圖所示的實施例中，qVDMOS電晶體形成在N-掩埋層上。利用N-型掩埋層將汲極電流從垂直汲極電流通路水準傳輸出來。在本發明的實施例中，N-型掩埋層作為一片N-掩埋層。當導電場效電板形成在電晶體結構的溝槽中時，溝槽汲極電極形成在週期性的間隔處，以起動汲極電流，如第3圖所示。更可選擇，利用電晶體結構的溝槽製備溝槽汲極電極，使每一對qVDMOS電晶體都有汲極電極，如第4圖所示。在其他實施例中，由於，在每一對電晶體處都起動了汲極電流，因此如第4圖所示的qVDMOS電晶體沒有掩埋層。具有第3圖和第4圖所示掩埋層的qVDMOS電晶體結構，特別適用於降壓變換器中的高端開關元件，而不具有掩埋層的qVDMOS電晶體結構可以用作低端開關元件，這將在下文中詳細介紹。
第5圖表示同步降壓轉換器中開關電路的電路圖。參見第5圖，同步降壓轉換器150含有兩個功率MOSFET作為開關元件，一個作為高端(HS)開關元件，另一個作為低端(LS)開關元件。高端(HS)電晶體和低端(LS)電晶體交替接通和斷開，使電流流經電感器L1，在輸出節點156處，提供輸出電壓VOUT。電感器L1和電容器C1構成LC網路，過濾輸出電壓VOUT，產生振幅基本恒定的輸出電壓。利用輸出電壓VOUT驅動負載158。當開關電路用於非同步降壓轉換器時，開關電路可能只含有高端電晶體，低端可以使用一個二極體。
在同步降壓轉換器150中，高端電晶體和低端電晶體串聯在輸入電壓VIN(節點152)和接地端之間。高端電晶體和低端電晶體之間的共同節點154為開關電壓VSW，它可以在地電壓和輸入電壓VIN之間 擺動。例如，當輸入電壓VIN為6V時，開關電壓VSW可以在0V至16V之間擺動。低端電晶體的汲極端連接到開關電壓，源極和本體端連接到地電壓。因此，低端電晶體的汲極節點從地電壓和輸入電壓VIN之間擺動。同時，高端電晶體的汲極端連接到輸入電壓VIN，而源極和本體端連接到開關電壓VSW。因此，高端電晶體的源極和本體的電壓在地電壓和輸入電壓VIN之間擺動。
對於低端電晶體來說，電晶體的本體與P-基板合併在一起。對於高端電晶體來說，電晶體的本體必須藉由N-掩埋層，與P-基板絕緣。
在本發明的實施例中，無需N-掩埋層，就能製備准VDMOS電晶體，因此准VDMOS電晶體可以用作降壓轉換器中的低端電晶體。此外，在本發明的實施例中，形成在掩埋層上的准VDMOS電晶體，以及無需掩埋層就能製備的准VDMOS形成在同一個積體電路中，因此該積體電路可以用作降壓轉換器的功率開關電晶體。
第6圖表示依據本發明的一個實施例，含有無需掩埋層就能製備的qVDMOS電晶體以及帶有掩埋層的qVDMOS電晶體的積體電路剖面圖。參見第6圖，積體電路包含無需掩埋層就能製備的qVDMOS電晶體200以及形成在掩埋層上的qVDMOS電晶體250。積體電路形成在P-型基板52和外延層56上。qVDMOS電晶體200形成在外延層中的P-阱257中。P-阱257可以是高壓P-阱，比標準的P-阱摻雜濃度更輕而且更深。
qVDMOS電晶體200的製備方式與上述N-型輕摻雜側壁區272的製備方式基本相同，N-型輕摻雜側壁區272沿溝槽270的側壁形成，作為垂直汲極電流通路。在沒有N-掩埋層的情況下，溝槽270也作為溝槽汲極電極，接收來自輕摻雜側壁區272的汲極電流。在本實施例中，所 形成的溝槽帶有底部摻雜區282。在本發明的實施例中，利用兩步注入工藝，製備底部摻雜區282，以形成一個分級的結。然後，溝槽內襯薄側壁氧化層276。沉積底部氧化層274之後，再沉積多晶矽層278，以構成導電場效電板。多晶矽層可以依據與上述相同的方式，連接到閘極電極62，利用多晶矽層278作為場效電板，以降低汲極電流通路的電阻。更可選擇，將多晶矽層278連接到N+源極區/P+本體接觸區66/68，使柵漏重疊電容達到最小。
為了在同一個溝槽270中形成汲極電極，利用第二溝槽刻蝕工藝，穿過多晶矽層278刻蝕。沉積氧化層，使多晶矽層絕緣。然後，利用另一個溝槽刻蝕工藝，形成溝槽開口，穿過底部氧化層274，一直到底部摻雜區282。用導電層(例如鋁或鎢)填充溝槽開口，以形成溝槽汲極電極284。在這種情況下，汲極電流沿輕摻雜側壁區272的垂直汲極電流通路，流至底部摻雜區282，然後藉由溝槽汲極電極284起動。
可以鏡像qVDMOS電晶體200，無需N-型掩埋層，就可製備並聯qVDMOS電晶體的一個陣列，每一對電晶體結構共用一個溝槽270結構。
qVDMOS電晶體250形成在P-基板52上，N-型掩埋層54形成在上面。qVDMOS電晶體200根據與上述相同的方式形成在外延層56中，輕摻雜側壁區272沿溝槽270的側壁，用作垂直汲極電流通路。垂直汲極電流通路連接在N-掩埋層54中，N-掩埋層54可以是一片連接到qVDMOS電晶體陣列上的N-掩埋層。溝槽270也作為溝槽汲極電極，接收來自輕摻雜側壁區272的汲極電流，汲極電流傳輸至N-掩埋層54，底部摻雜區282，溝槽汲極電極284。
可以鏡像qVDMOS電晶體250，在N-型掩埋層上，形成並 聯qVDMOS電晶體的陣列，每一對電晶體結構共用一個溝槽270結構。
因此，qVDMOS電晶體200可以用作降壓轉換器的低端電晶體，而qVDMOS電晶體250可以用作降壓轉換器的高端電晶體。依據本發明的一個實施例，利用准垂直DMOS電晶體結構，積體電路的低端電晶體和高端電晶體都可以整合在同一個基板上。更重要的是，無需N-掩埋層就能製備低端電晶體。藉以降低了汲極節點和P-基板之間的結電容。由於低端開關元件的汲極在地電壓和輸入電壓VIN之間擺動，因此降低汲極節點和P-基板之間的結電容對於低端開關元件來說尤其重要。N-掩埋層在兩個電壓極值之間擺動是不良的。
在上述實施例中，qVDMOS電晶體形成在帶有N-型外延層56的P-型基板52上。當使用N-型掩埋層時，qVDMOS電晶體250形成在N-外延層56中，本體形成在P-阱58中。當沒有使用掩埋層時，qVDMOS電晶體200形成在高壓P-阱257中，本體形成在低壓P-阱58中，高壓P-阱比低壓P-阱摻雜濃度更小而且更深。在本發明的實施例中，qVDMOS電晶體形成在帶有P-型外延層的P-型基板52上。在這種情況下，輕摻雜側壁區272構成N-型汲極延伸區，用於汲極電流。
带有汲極延伸物的NMOS電晶體。
在上述DMOS電晶體結構中，構成本體區的P-阱對準到主動擴散區，也就是源極擴散。閘極電極也對準到主動擴散區。因此，P-阱和閘極電極不會相互自對準，而是具有各自的對準過程。當這兩個層都對準到主動擴散區時，可以有單獨的不對準誤差。當在溝槽附近如上所述地鏡像電晶體結構製備DMOS電晶體陣列時，不對準誤差會使溝槽一側電晶體的導通電阻RdsON較大，溝槽另一側電晶體的RdsON較小。導通電阻的這種不對稱性是不良的。
依據本發明的另一方面，製備NMOS電晶體，其汲極延伸物在沿溝槽側壁的垂直汲極電流通路中。更重要的是，NMOS電晶體可以對稱形成在溝槽附近，藉以避免任何不對準誤差可能引起鏡像元件中的元件失配。汲極延伸物的作用是降低閘極電極邊緣處的汲極電壓，可以縮短NMOS電晶體的通道長度，而不會影響元件的可靠性。
第7圖表示依據本發明的一個實施例，在中間工藝步驟中帶有汲極延伸物的NMOS電晶體剖面圖。第8圖表示依據本發明的一個實施例，一種帶有汲極延伸物的NMOS電晶體剖面圖。參見第7圖，NMOS電晶體300、300A形成在P-型基板52上，N-型掩埋層54形成在上面。外延層形成在基板52上，基板52可以為N-型或P-型。NMOS電晶體300、300A形成在P-阱58中，P-阱58可以是一片外延層中的P-阱。NMOS電晶體300、300A為傳統的NMOS電晶體，閘極電極62形成在閘極電介質層60上方。沿閘極電極62的側壁製備墊片64之前，先製備輕摻雜擴散區65。然後，製備N+源極區66、汲極擴散區367以及P+本體接觸區68。橫向通道形成在閘極電極和閘極電介質層60以下，通道長度用“LCH”表示。
在本實施例中，製備NMOS電晶體300、300A，作為並聯NMOS電晶體的一個陣列。製備汲極擴散區367，作為細長的擴散區，連接兩個相鄰的NMOS電晶體。在本發明的實施例中，在汲極擴散區367中製備溝槽370，如第7圖中虛線所示。安排溝槽370的位置，使汲極擴散區367位於溝槽的任意一側。
參見第8圖，溝槽370細長在汲極擴散區367和P-阱58中，並且觸及N-掩埋層54。利用N-型側壁注入，沿溝槽側壁形成輕摻雜側壁區372。製備薄側壁氧化層376，內襯溝槽370的側壁，然後在溝槽底部 沉積很厚的氧化層374。用導電層(例如多晶矽層378)填充溝槽，形成導電場效電板。多晶矽層378可以電連接到閘極電極或源極電極。導電場效電板的工作方式與上述第3圖相同，在累加態下導電場效電板可以偏置，以降低垂直汲極電流通路的導通電阻，或者藉由偏置降低柵漏重疊電容。
因此，NMOS電晶體300、300A在閘極電極62下方具有傳統的橫向通道，以源極和汲極擴散區為界，電晶體在汲極擴散區367中具有汲極端。汲極端接收的汲極電流流向輕摻雜側壁區372中形成的垂直汲極電流通路。在本實施例中，N-掩埋層54收集汲極電流，汲極粘損電極(例如溝槽汲極電極)可以形成在積體電路中的任何地方，以便用第3圖所示相同的方式連接到N-掩埋層54。
NMOS電晶體具有許多優勢。首先，在溝槽的兩側都有汲極擴散區，使電晶體的通道成為對稱的，元件性能不會受到不對準誤差的影響。此外，由於汲極擴散區是重摻雜的，汲極擴散區電阻率很低。因此汲極擴散區中溝槽370的絕對位置並不重要。仍然位於溝槽370任意一側的汲極擴散區可以更長或更短，而不會影響電晶體元件的性能。
帶有汲極延伸物的NMOS電晶體的一個重要特點是，只要輕摻雜側壁區具有足夠高的電阻率，閘極電極邊緣處的汲極擴散區就不會受到高電壓。因此，可以減小電晶體的通道長度LCH或者電晶體的源極/本體間距，在不犧牲元件性能的前提下，製備更小的元件。實際上，憑藉汲極延伸物，NMOS電晶體在汲極擴散區處將最多只有幾伏的電壓。排除了穿通或熱載流子注入等問題。
在本發明的可選實施例中，無需掩埋層，就能製備帶有上述汲極延伸物的NMOS電晶體。第9圖表示依據本發明的一個可選實施例，帶有汲極延伸物的NMOS電晶體剖面圖。參見第9圖，NMOS電晶體400、 400A的製備方式除了在P-基板52上沒有製備N-型掩埋層之外，其他都與NMOS電晶體300、300A的製備方式基本相同。在這種情況下，溝槽汲極電極形成在溝槽470中，以便與垂直汲極電流通路形成電接觸，垂直汲極電流通路形成在輕摻雜側壁區472中。溝槽結構含有側壁氧化層476和溝槽汲極電極484，其製備方式與上述第6圖所示的製備方式相同。因此，來自通道的汲極電流流經汲極擴散區467，向下穿過輕摻雜側壁區472中的垂直汲極電流通路，流經溝槽底部擴散區482，由溝槽汲極電極484起動汲極電流。
第8圖所示的NMOS電晶體300、300A以及第9圖所示的NMOS電晶體400、400A可以製備在同一個積體電路上，用作降壓轉換器的功率開關元件。帶有掩埋層的NMOS電晶體300、300A可以用作高端開關元件，而不帶有掩埋層的NMOS電晶體400、400A可以用作低端開關元件。
雖然為了解釋說明，上述實施例給出了許多具體細節，但是本發明不應局限於上述細節。實施本發明更有許多可選方式。上述實施例僅用於解釋說明，不具有侷限性。
儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。
50、50A‧‧‧qVDMOS電晶體
52‧‧‧基板
54‧‧‧掩埋層
56‧‧‧外延層
58‧‧‧P-阱
60‧‧‧閘極電介質層
62‧‧‧閘極電極
64‧‧‧墊片
65‧‧‧輕摻雜擴散區
66‧‧‧N+源極區
68‧‧‧P+本體接觸區
70、80‧‧‧溝槽
72‧‧‧摻雜側壁區
74‧‧‧氧化層
76‧‧‧側壁氧化層
78‧‧‧多晶矽層
82‧‧‧摻雜區
84‧‧‧溝槽汲極電極

Claims (29)

  1. 一種電晶體，其包含：一半導體本體；一第一導電類型的本體區，形成在該半導體本體中；一閘極電極，與該本體區部分重疊，並且藉由閘極電介質層，與該半導體本體絕緣；一第二導電類型的源極擴散區，形成在該閘極電極第一側的該本體區中；一溝槽，形成在該閘極電極第二側的該半導體本體中，該閘極電極的第二側與第一側相對，該溝槽內襯一側壁電介質層；以及一第二導電類型的摻雜側壁區，沿該溝槽側壁形成在該半導體本體中，該摻雜側壁區構成電晶體的垂直汲極電流通路；其中，該溝槽內襯一薄電介質層，作為該側壁電介質層，一底部電介質層填充在該溝槽底部，一導電層填充在該底部電介質層上方，該導電層電連接到該閘極電極或源極電極；其中，該半導體本體包含：一第一導電類型的基板；一第二導電類型的掩埋層，形成在該基板上；以及一第二導電類型的外延層，形成在該基板上；其中該溝槽至少觸及該掩埋層，電晶體的汲極電流穿過該摻雜側壁區，流至該掩埋層。
  2. 如申請專利範圍第1項所述之電晶體，其中該導電層電連接到該閘極電極，構成垂直汲極電流通路的溝槽導電場效電板，當電晶體接通時，場效電板偏置到累加態，以降低垂直汲極電流通路的電阻率。
  3. 如申請專利範圍第1項所述之電晶體，其中該薄電介質層包含一薄氧化層，該溝槽中的該導電層包含一多晶矽層。
  4. 如申請專利範圍第1項所述之電晶體，其更包含：一第二溝槽，形成在該半導體本體中，遠離該溝槽，至少觸及該掩埋層，該第二溝槽內襯側壁電介質層，並用該導電層填充；以及一第二導電類型的溝槽底部摻雜區，形成在該第二溝槽以下的該半導體本體中；其中該第二溝槽的該導電層與該溝槽底部摻雜區和該掩埋層電接觸，構成溝槽汲極電極的該導電層傳導電晶體的汲極電流。
  5. 如申請專利範圍第4項所述之電晶體，其中該導電層係由鋁或鎢的其中一種構成的。
  6. 如申請專利範圍第1項所述之電晶體，其更包含一第二導電類型的溝槽底部摻雜區，形成在該溝槽以下的該半導體本體中，並且與該摻雜側壁區電接觸，該摻雜側壁區沿該溝槽側壁，形成在該半導體本體中；其中該溝槽的該側壁電介質層足夠厚，使得該導電層與該摻雜側壁區電絕緣，用該導電層填充該溝槽，該導電層與該溝槽底部摻雜區電接觸，該導電層構成溝槽汲極電極； 其中垂直汲極電流通路中的電晶體汲極電流，直接流至該溝槽底部摻雜區和溝槽汲極電極。
  7. 如申請專利範圍第6項所述之電晶體，其中該導電層包含鋁或鎢的其中一種。
  8. 如申請專利範圍第6項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一第二導電類型的掩埋層，形成在該基板上；以及一第二導電類型的外延層，形成在該基板上；其中該本體區作為第一導電類型的阱區，該溝槽至少觸及該掩埋層，電晶體的汲極電流流經該摻雜側壁區，流至該掩埋層或該溝槽底部摻雜區，然後流至溝槽汲極電極。
  9. 如申請專利範圍第6項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一形成在該基板上的外延層；以及一第一導電類型的阱區，形成在該外延層中；其中該本體區和該溝槽都形成在該阱區中。
  10. 如申請專利範圍第1項所述之電晶體，其更包含一第二導電類型的溝槽底部摻雜區，形成在該溝槽以下的該半導體本體中，並且與該摻雜側壁區電接觸，該摻雜側壁區沿該溝槽的側壁形成在該半導體本體中； 其中該溝槽內襯薄電介質層，作為側壁電介質層，在該溝槽的底部，用底部電介質層填充在該溝槽的周邊部分，第一導電層在該底部電介質層上方，導電層電連接到該閘極電極或源極電極；其中該溝槽的剩餘部分用第二導電層填充，該第二導電層與該溝槽底部摻雜區電接觸，該第二導電層藉由電介質層，與該第一導電層電絕緣，該第二導電層構成溝槽汲極電極；其中垂直汲極電流通路中的電晶體汲極電流，直接流至該溝槽底部摻雜區和溝槽汲極電極。
  11. 如申請專利範圍第10項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一第二導電類型的掩埋層，形成在該基板上；以及一第二導電類型的外延層，形成在該基板上；其中該本體區作為第一導電類型的阱區，該溝槽至少觸及該掩埋層，電晶體的汲極電流流經該摻雜側壁區，流至該掩埋層或該溝槽底部摻雜區，然後流至溝槽汲極電極。
  12. 如申請專利範圍第10項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一形成在該基板上的外延層；以及一第一導電類型的阱區，形成在該外延層中；其中該本體區和該溝槽都形成在該阱區中。
  13. 如申請專利範圍第10項所述之電晶體，其中該第一導電層包含多晶矽層，該第二導電層包含鋁或鎢的其中一種。
  14. 如申請專利範圍第1項所述之電晶體，其更包含一雙擴散MOS電晶體，其中一橫向通道在該閘極電極下方，垂直汲極電流通路沿該溝槽的側壁，在該摻雜側壁區中。
  15. 如申請專利範圍第1項所述之電晶體，其更包含一MOS電晶體，該本體區包含一第一導電類型的阱區，該阱區形成在該半導體本體中，該MOS電晶體更包含一第二導電類型的汲極擴散區，形成在該閘極電極和該溝槽之間的該閘極電極第二側上的該本體區中，其中該MOS電晶體在該閘極電極下方具有一橫向通道，汲極電流從該汲極擴散區，沿該溝槽側壁，流至該摻雜側壁區中的垂直汲極電流通路。
  16. 一種製備電晶體的方法，其包含：製備一半導體本體；在該半導體本體中，製備一第一導電類型的本體區；製備一閘極電極，與該本體區部分重疊，該閘極電極藉由閘極電介質層，與該半導體本體絕緣；在該閘極電極第一側的該本體區中，製備一第二導電類型的源極擴散區；在該閘極電極第二側的該半導體本體中，製備一溝槽，該閘極電極第二側與該閘極電極第一側相對；製備一側壁電介質層，內襯該溝槽的側壁；以及 沿該溝槽的側壁，在該半導體本體中注入第二導電類型的摻雜物，以構成摻雜側壁區，摻雜側壁區構成電晶體的垂直汲極電流通路。
  17. 如申請專利範圍第16項所述之方法，其更包含：在該溝槽底部，製備一底部電介質層；在該底部電介質層上方的該溝槽中，製備一導電層；以及將該導電層電連接到該閘極電極或源極電極。
  18. 如申請專利範圍第16項所述之方法，其中製備該半導體本體包含：製備一第一導電類型的基板；在該基板上製備一第二導電類型的掩埋層；並且在該基板上製備一第二導電類型的外延層；其中該溝槽至少觸及該掩埋層，電晶體的汲極電流流經摻雜側壁區，流至該掩埋層。
  19. 如申請專利範圍第18項所述之方法，其更包含：在該半導體本體中，製備一第二溝槽，遠離該溝槽，至少觸及該掩埋層；在該第二溝槽中，製備該側壁電介質層；在該第二溝槽以下的該半導體本體中，製備一第二導電類型的溝槽底部摻雜區；以及在該第二溝槽中，製備一導電層； 其中該第二溝槽的該導電層與該溝槽底部摻雜區和該掩埋層電接觸，該導電層構成一溝槽汲極電極，傳輸電晶體的汲極電流。
  20. 如申請專利範圍第16項所述之方法，其更包含：在該溝槽以下的該半導體本體中，製備一第二導電類型的溝槽底部摻雜區，並且沿該溝槽的側壁，與該半導體本體中的摻雜側壁區電接觸；製備一厚電介質層，作為該側壁電介質層，內襯該溝槽的側壁；以及在該溝槽中製備一導電層，與該溝槽底部摻雜區電接觸，該導電層構成一溝槽汲極電極；其中在垂直汲極電流通路中流動的電晶體汲極電流，直接流至該溝槽底部摻雜區和該溝槽汲極電極。
  21. 如申請專利範圍第16項所述之方法，其更包含：在該溝槽以下的該半導體本體中，製備一第二導電類型的溝槽底部摻雜區，並且沿該溝槽的側壁，與該半導體本體中的摻雜側壁區電接觸；在該溝槽底部，製備一底部電介質層；在該底部電介質層上方的該溝槽中，製備一第一導電層；刻蝕該第一導電層和該底部電介質層中形成第一內部溝槽；在第一內部溝槽中，製備一電介質層；在該電介質層中，刻蝕第二內部溝槽，刻蝕到該溝槽底部； 在第二內部溝槽中，製備一第二導電層，與該溝槽底部摻雜區電接觸，剩餘的該電介質層使該第一導電層與該第二導電層絕緣，該第二導電層構成一溝槽閘極電極；以及將該第一導電層電連接到該閘極電極或源極電極；其中在垂直汲極電流通路中流動的電晶體汲極電流，直接流至該溝槽底部摻雜區和溝槽汲極電極。
  22. 一種電晶體，其包含：一半導體本體；一第一導電類型的本體區，形成在該半導體本體中；一閘極電極，與該本體區部分重疊，並且藉由閘極電介質層，與該半導體本體絕緣；一第二導電類型的源極擴散區，形成在該閘極電極第一側的該本體區中；一溝槽，形成在該閘極電極第二側的該半導體本體中，該閘極電極的第二側與第一側相對，該溝槽內襯一側壁電介質層；一第二導電類型的摻雜側壁區，沿該溝槽側壁形成在該半導體本體中，該摻雜側壁區構成電晶體的垂直汲極電流通路；以及一第二導電類型的溝槽底部摻雜區，形成在該溝槽以下的該半導體本體中，並且與該摻雜側壁區電接觸，該摻雜側壁區沿該溝槽側壁，形成在該半導體本體中； 其中，該溝槽的該側壁電介質層足夠厚，使得一導電層與該摻雜側壁區電絕緣，用該導電層填充該溝槽，該導電層與該溝槽底部摻雜區電接觸，該導電層構成溝槽汲極電極；其中，垂直汲極電流通路中的電晶體汲極電流，直接流至該溝槽底部摻雜區和溝槽汲極電極。
  23. 如申請專利範圍第22項所述之電晶體，其中該導電層包含鋁或鎢的其中一種。
  24. 如申請專利範圍第22項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一第二導電類型的掩埋層，形成在該基板上；以及一第二導電類型的外延層，形成在該基板上；其中該本體區作為第一導電類型的阱區，該溝槽至少觸及該掩埋層，電晶體的汲極電流流經該摻雜側壁區，流至該掩埋層或該溝槽底部摻雜區，然後流至溝槽汲極電極。
  25. 如申請專利範圍第22項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一形成在該基板上的外延層；以及一第一導電類型的阱區，形成在該外延層中；其中該本體區和該溝槽都形成在該阱區中。
  26. 一種電晶體，其包含： 一半導體本體；一第一導電類型的本體區，形成在該半導體本體中；一閘極電極，與該本體區部分重疊，並且藉由閘極電介質層，與該半導體本體絕緣；一第二導電類型的源極擴散區，形成在該閘極電極第一側的該本體區中；一溝槽，形成在該閘極電極第二側的該半導體本體中，該閘極電極的第二側與第一側相對，該溝槽內襯一側壁電介質層；一第二導電類型的摻雜側壁區，沿該溝槽側壁形成在該半導體本體中，該摻雜側壁區構成電晶體的垂直汲極電流通路；以及一第二導電類型的溝槽底部摻雜區，形成在該溝槽以下的該半導體本體中，並且與該摻雜側壁區電接觸，該摻雜側壁區沿該溝槽的側壁形成在該半導體本體中；其中，該溝槽內襯一薄電介質層，作為該側壁電介質層，在該溝槽的底部，用底部電介質層填充在該溝槽的周邊部分，一第一導電層在該底部電介質層上方，導電層電連接到該閘極電極或源極電極；其中，該溝槽的剩餘部分用一第二導電層填充，該第二導電層與該溝槽底部摻雜區電接觸，該第二導電層藉由電介質層，與該第一導電層電絕緣，該第二導電層構成溝槽汲極電極； 其中，垂直汲極電流通路中的電晶體汲極電流，直接流至該溝槽底部摻雜區和溝槽汲極電極。
  27. 如申請專利範圍第26項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一第二導電類型的掩埋層，形成在該基板上；以及一第二導電類型的外延層，形成在該基板上；其中該本體區作為第一導電類型的阱區，該溝槽至少觸及該掩埋層，電晶體的汲極電流流經該摻雜側壁區，流至該掩埋層或該溝槽底部摻雜區，然後流至溝槽汲極電極。
  28. 如申請專利範圍第26項所述之電晶體，其中該半導體本體包含：一第一導電類型的基板；一形成在該基板上的外延層；以及一第一導電類型的阱區，形成在該外延層中；其中該本體區和該溝槽都形成在該阱區中。
  29. 如申請專利範圍第26項所述之電晶體，其中該第一導電層包含多晶矽層，該第二導電層包含鋁或鎢的其中一種。
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US20150214335A1 (en) 2015-07-30
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US10032900B2 (en) 2018-07-24
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