CN104051534A - 垂直dmos晶体管 - Google Patents

垂直dmos晶体管 Download PDF

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Publication number
CN104051534A
CN104051534A CN201310671827.0A CN201310671827A CN104051534A CN 104051534 A CN104051534 A CN 104051534A CN 201310671827 A CN201310671827 A CN 201310671827A CN 104051534 A CN104051534 A CN 104051534A
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groove
transistor
conductive layer
conduction type
semiconductor body
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CN201310671827.0A
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CN104051534B (zh
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秀明土子
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种晶体管，包含一个半导体本体；一个形成在半导体本体中的第一导电类型的本体区；一个与本体区部分重叠的栅极电极，并且通过栅极电介质层，与半导体本体绝缘；一个第二导电类型的源极扩散区，形成在栅极电极第一侧的本体区中；一个形成在栅极电极第二侧半导体本体中的沟槽，第二侧与第一侧相对，沟槽内衬侧壁电介质层，第二导电类型的掺杂侧壁区沿沟槽的侧壁，形成在半导体本体中，掺杂侧壁区在沟槽侧壁构成晶体管的垂直漏极电流通路。

Description

垂直DMOS晶体管
技术领域
本发明涉及半导体器件，尤其是垂直DMOS晶体管。
背景技术
由于横向双扩散金属-氧化物-半导体（LDMOS）晶体管的高击穿电压性能，以及对于低压器件的CMOS技术兼容，因此通常用于高压器件（＜10V至＞1000V）。图1表示传统的低端N-型LDMOS晶体管的剖面图。众所周知，增大漂流区的长度（用距离“d”表示），LDMOS晶体管的击穿电压也可以相应地增大。
图2表示传统的沟槽MOSFET器件的剖面图。在沟槽MOSFET器件中，栅极电极形成在沟槽中，通道形成在沿沟槽侧壁的垂直区中。因此，沟槽MOSFET器件是一个垂直晶体管器件，源极区在器件的顶部，漏极端在器件的背部。Williams等人发明的美国专利7,576,391也提出了一种横向沟槽MOSFET器件，用于控制通道电流的沟槽栅极在刻蚀后沟槽的侧边垂直向下。
发明内容
本发明提供一种垂直DMOS晶体管，增强了晶体管器件的强度和可靠性，晶体管器件可以拥有一个很宽的安全操作区，可以调节沟槽深度和侧壁漏极延伸物的掺杂水平，优化漏极节点和漏源导通电阻RdsON所加载的最高电压，而不会使器件间距明显增大，准垂直DMOS晶体管可以集成或作为一个单独的器件。
依据本发明的原理，准垂直双扩散MOS（DMOS）晶体管包含一个沿沟槽侧壁的垂直漏极电流通路。该沟槽可以引入一个导电场板，或者配置成一个沟槽漏极电极。在一些实施例中，垂直漏极电流通路连接到掩埋掺杂区，掩埋掺杂区将漏极电流水平引至沟槽漏极电极，构成一个顶端漏极电极。凭借顶端漏极电极，可以作为集成电路的一部分，集成准垂直DMOS晶体管。准垂直DMOS晶体管也可以作为一个带有背部漏极电极的单独器件。
依据本发明的另一方面，制备一个NMOS晶体管，漏极延伸物在沿沟槽侧壁的垂直漏极电流通路中。漏极延伸物具有降低栅极电极边缘处的漏极电压的作用，从而使低压NMOS晶体管可以接通或断开漏极节点上所加载的高压，而不会影响器件的可靠性。
在本发明的实施例中，准垂直DMOS晶体管包含一个横向通道，形成在栅极电极下方的半导体本体中，通过一个栅极电介质层，与栅极电极绝缘。沟槽形成在栅极电极的漏极端，并在此处形成轻掺杂的侧壁区，从而沿沟槽侧壁提供一个高电阻率的漏极延伸物通路。来自于横向通道的漏极电流在沟槽侧壁处拐弯，漏极电流沿轻掺杂侧壁区传导，构成垂直漏极电流通路。在这种情况下，延伸后的漏极漂流区形成在掺杂漏极电流通路中，以提高准垂直DMOS晶体管的击穿电压。
在一些实施例中，垂直电流通路连接到掩埋掺杂区，例如掩埋层，将漏极电流水平引至沟槽漏极电极。沟槽漏极电极作为导电填充沟槽，可以位于每个准垂直DMOS晶体管结构或并联准垂直DMOS晶体管结构阵列的预定义间隔处。
准垂直DMOS晶体管结构与传统的横向或垂直DMOS晶体管器件相比，具有很多优势。首先，本发明所述的准垂直DMOS晶体管具有一个很深的结，在沟槽底部而不是在栅极边缘处击穿。因此，栅极电极的漏极边缘无法承受过高的电压。高电场位于P-阱本体的底部。在这种情况下，热载流子注入被提升。从而增强了晶体管器件的强度和可靠性，晶体管器件可以拥有一个很宽的安全操作区。此外，可以调节沟槽深度和侧壁漏极延伸物的掺杂水平，优化漏极节点和漏源导通电阻RdsON所加载的最高电压，而不会使器件间距明显增大。例如，较深的沟槽和较轻掺杂的侧壁区可以增大漏极节点的击穿电压。同时，准垂直DMOS晶体管的RdsON*面积比传统的横向DMOS或LDMOS晶体管的RdsON*面积更小。此外，准垂直DMOS晶体管可以集成或作为一个单独的器件。例如，准垂直DMOS晶体管可以集成在功率集成电路中，用作片上功率FET。在这种情况下，可以利用顶部沟槽漏极电极连接到掩埋层，掩埋层连接到垂直漏极电流通路，用于并联晶体管阵列。还可选择，准垂直DMOS晶体管可以作为一个单独的器件，还可以作为一个N-型或P-型器件。对于N-通道DMOS晶体管来说，单独的器件可以形成在带有N-型外延层的N+衬底上。
附图说明
以下的详细说明及附图提出了本发明的各个实施例。
图1表示一种传统的低端N-型LDMOS晶体管的剖面图。
图2表示一种传统的沟槽MOSFET器件的剖面图。
图3表示依据本发明的一个实施例，一种引入沟槽导电场板的准垂直DMOS晶体管器件的剖面图。
图4表示依据本发明的一个实施例，一种引入沟槽漏极电极的准垂直DMOS晶体管器件的剖面图。
图5表示一个在同步降压变换器中的开关电路的电路图。
图6表示依据本发明的一个实施例，引入一个不带有掩埋层的qVDMOS晶体管以及一个带有掩埋层的qVDMOS晶体管的集成电路剖面图。
图7表示依据本发明的一个实施例，在中间工艺步骤中，一种带有漏极延伸物的NMOS晶体管的剖面图。
图8表示依据本发明的一个实施例，一种带有漏极延伸物的NMOS晶体管的剖面图。
图9表示依据本发明的一个可选实施例，一种带有漏极延伸物的NMOS晶体管的剖面图。
具体实施方式
本发明可以以各种方式实现，包含作为一个工艺；一种装置；一个系统；和/或一种物质合成物。在本说明书中，这些实现方式或本发明可能采用的任意一种其他方式，都可以称为技术。一般来说，可以在本发明的范围内变换所述工艺步骤的顺序。
本发明的一个或多个实施例的详细说明以及附图解释了本发明的原理。虽然，本发明与这些实施例一起提出，但是本发明的范围并不局限于任何实施例。本发明的范围仅由权利要求书限定，本发明包含多种可选方案、修正以及等效方案。在以下说明中，所提出的各种具体细节用于全面理解本发明。这些细节用于解释说明，无需这些详细细节中的部分细节或全部细节，依据权利要求书，就可以实现本发明。为了简便，本发明相关技术领域中众所周知的技术材料并没有详细说明，以免对本发明产生不必要的混淆。
图3表示依据本发明的一个实施例，一种引入沟槽导电场板的准垂直DMOS晶体管器件的剖面图。参见图3，准垂直DMOS（qVDMOS）晶体管50形成在P-型衬底52上，N-型掩埋层（N-BL）54也形成在上面，作为掩埋掺杂区。外延层56形成在P-衬底52上。掩埋层56可以是一个N-型外延层或一个P-型外延层。当使用P-型外延层时，可以通过离子注入或扩散和退火，将外延层转换成轻掺杂N-型区。构成qVDMOS晶体管本体区的P-阱58，形成在外延层56上，例如通过离子注入。然后，P-阱本体58退火。在外延层56上方形成一个栅极电介质层60，在栅极电介质层上方形成一个栅极电极62。栅极电极62与P-阱本体58部分重叠，并且延伸到P-阱本体58上方。轻掺杂扩散（LDD）区65自对准到栅极电极62之后，在栅极电极的旁边，形成侧壁垫片64。重掺杂N+源极区66和重掺杂P+本体接触区68形成在qVDMOS晶体管50的源极端。在大多数的应用中，N+源极区66和P+本体接触区68通常短接在一起。
然后，在qVDMOS晶体管50的漏极端形成一个沟槽70。沟槽70内衬很薄的侧壁氧化物76，可以通过沉积或热生长制备侧壁氧化物76。在沟槽70中，进行N-型注入，包含侧壁和带角度的注入，以便在N-外延层56中形成N-型掺杂侧壁区72，并且在沟槽底部形成N-型掺杂区。在本发明的实施例中，N-型掺杂侧壁区72为轻掺杂侧壁区。在一个实施例中，掺杂侧壁区72的掺杂浓度低于P-阱本体58的掺杂水平。在一些实施例中，掺杂侧壁区72的掺杂浓度在1015/cm3至1017/cm3的范围内。在一个实施例中，掺杂侧壁区72的掺杂浓度大约为1016/cm3。
然后，在沟槽底部，用厚氧化层74填充沟槽70。选取厚氧化层74的厚度，以增大击穿电压，同时降低栅漏电容。在本实施例中，用多晶硅层78填充沟槽70。多晶硅层78起沟槽导电场板的作用，这将在下文中详细介绍。因此，所制成的轻掺杂侧壁区72构成漏极延伸区或漏极漂流区，以提高qVDMOS晶体管的击穿电压。
在本发明的可选实施例中，沟槽70以及之后的注入和沉积，可以在制备多晶硅栅极电极之前进行。
在本发明的实施例中，可以复制基本的qVDMOS晶体管结构50，以构成一个并联qVDMOS晶体管的阵列，以提高晶体管器件的电流载流能力。在图3中，在沟槽70的另一边，制备qVDMOS晶体管结构50的镜像50A。可以复制相同的基本qVDMOS晶体管结构50/50A，以制备一个并联qVDMOS晶体管的阵列，每一对晶体管都具有一个公共的沟槽。
在本实施例中，沿沟槽70的侧壁形成的轻掺杂侧壁区72，电连接到掩埋层54。因此，掩埋层54将所有的qVDMOS晶体管的垂直漏极电流通路电连接起来，从而形成在N-外延层56中。在一个实施例中，利用连接到掩埋层54上的沟槽漏极电极84，制备顶端漏极电极，例如在远离qVDMOS晶体管阵列的位置处。如图3所示，通过沟槽80制备沟槽漏极电极84，其中内衬侧壁绝缘层（例如侧壁氧化层）沟槽80，并用导电层（例如钨或铝）填充沟槽80。一般来说，（例如通过离子注入形成的）掺杂区82形成在沟槽80的底部，以增强沟槽中导电层和掩埋层54之间的欧姆接触。
在本实施例中，用多晶硅填充qVDMOS晶体管50的沟槽70，构成一个沟槽多晶硅场板，作为沟槽导电场板。在本发明的实施例中，沟槽多晶硅场板78导电连接到qVDMOS晶体管的栅极电极或源极电极。可以通过不同的方式完成导电连接，例如通过金属互连或多晶硅互连。
将沟槽导电场板连接到栅极电极的特殊优势在于，降低了qVDMOS晶体管的漏源导通电阻RdsON。更确切地说，当qVDMOS晶体管50接通时，栅极电压处于逻辑上的高级别（例如5V），而漏极电压处于低级别（例如0V左右）。当沟槽多晶硅层78连接到栅极电极时，沟槽多晶硅层78也偏置到逻辑上的高级别（例如5V）。因此，当偏置时，侧壁掺杂区72积聚电子，从而降低漏极延伸区的电阻。因此，将沟槽导电场板连接到栅极电势，可以降低qVDMOS晶体管的导通电阻RdsON。
当沟槽导电场板电连接到栅极电极时，栅漏重叠电容会增大。当用于高速开关器件时，增大后的电容可以提高qVDMOS晶体管的开关速度。然而，当qVDMOS晶体管用于低速开关器件时，例如2MHz以下时，栅漏重叠电容不会明显增大。
当需要很高的开关速度而且可以承受较高的RdsON导通电阻时，沟槽导电场板可以电连接到源极端。当场板电连接到源极端时，场板掺杂区并不处于累加态。导通电阻RdsON没有降低，而栅漏重叠电容达到最小值，因此所形成的qVDMOS晶体管可以在很高的开关速度下工作。
在图3所示的qVDMOS晶体管中，每个晶体管晶胞的垂直漏极电流通路都连接到N-掩埋层54，N-掩埋层54将漏极电流水平传输到漏极电极84。在本发明的实施例中，可以通过改变N-掩埋层54的掺杂等级，以及改变沟槽漏极电极84的位置，来调节漏极延伸通路的电阻。例如根据N-掩埋层54的掺杂等级和电阻，对于指定数量的qVDMOS晶体管，可以包含沟槽漏极电极84。根据N-掩埋层54的电阻和并联器件阵列的导通电阻RdsON，可以增大或减小沟槽漏极电极84的数量或间距。
图4表示依据本发明的一个实施例，一种引入沟槽漏极电极的准垂直DMOS晶体管器件的剖面图。参见图4，qVDMOS晶体管100的制备方式与图3所示的qVDMOS晶体管50的制备方式相同，垂直漏极电流通路形成在沟槽110的N-型轻掺杂侧壁区72中。然而，在qVDMOS晶体管100中，并没有将导电场板制备在沟槽110中，而是利用沟槽110制备沟槽漏极电极128。在这种情况下，qVDMOS晶体管100的每个晶体管结构处都有一个漏极电极。
更确切地说，制备沟槽110之后，通过离子注入，在沟槽110底部制备一个掺杂区122。掺杂区122降低了掩埋层54和后来形成的漏极导电层之间的接触电阻，在它们之间形成欧姆接触。然后，用侧壁氧化层117内衬沟槽110。侧壁氧化层117比导电场板所用的侧壁氧化层76更厚。侧壁氧化层117必须足够厚，才能使漏极电极与形成在侧壁掺杂区72中的漏极延伸区电绝缘。然后，用铝或钨等导电材料填充沟槽110，形成沟槽漏极电极128。
可以镜像基本的qVDMOS晶体管结构100，以制备qVDMOS晶体管100A，它们共享同一个沟槽漏极电极128。可以重复qVDMOS晶体管结构100/100A，形成一个VDMOS晶体管的阵列，qVDMOS晶体管的每个部分或每个带都制备一个漏极电极。
这样一来，漏极电流流经轻掺杂侧壁区72中的垂直漏极电流通路，流至N-掩埋层54，然后通过沟槽漏极电极128起动漏极电流。由于漏极电流起动非常靠近垂直漏极电流通路，因此N-掩埋层54在漏极电流通路中引起的电阻降低。
在图3和图4所示的实施例中，qVDMOS晶体管形成在N-掩埋层上。利用N-型掩埋层将漏极电流从垂直漏极电流通路水平传输出来。在本发明的实施例中，N-型掩埋层作为一片N-掩埋层。当导电场板形成在晶体管结构的沟槽中时，沟槽漏极电极形成在周期性的间隔处，以起动漏极电流，如图3所示。还可选择，利用晶体管结构的沟槽制备沟槽漏极电极，使每一对qVDMOS晶体管都有漏极电极，如图4所示。在其他实施例中，由于，在每一对晶体管处都起动了漏极电流，因此如图4所示的qVDMOS晶体管没有掩埋层。具有图3和图4所示掩埋层的qVDMOS晶体管结构，特别适用于降压变换器中的高端开关器件，而不具有掩埋层的qVDMOS晶体管结构可以用作低端开关器件，这将在下文中详细介绍。
图5表示同步降压转换器中开关电路的电路图。参见图5，同步降压转换器150含有两个功率MOSFET作为开关器件——一个作为高端（HS）开关器件，另一个作为低端（LS）开关器件。高端（HS）晶体管和低端（LS）晶体管交替接通和断开，使电流流经电感器L1，在输出节点156处，提供输出电压VOUT。电感器L1和电容器C1构成一个LC网络，过滤输出电压VOUT，产生振幅基本恒定的输出电压。利用输出电压VOUT驱动负载158。当开关电路用于非同步降压转换器时，开关电路可能只含有高端晶体管，低端可以使用一个二极管。
在同步降压转换器150中，高端晶体管和低端晶体管串联在输入电压VIN（节点152）和接地端之间。高端晶体管和低端晶体管之间的公共节点154为开关电压VSW，它可以在地电压和输入电压VIN之间摆动。例如，当输入电压VIN为6V时，开关电压VSW可以在0V至16V之间摆动。低端晶体管的漏极端连接到开关电压，源极和本体端连接到地电压。因此，低端晶体管的漏极节点从地电压和输入电压VIN之间摆动。同时，高端晶体管的漏极端连接到输入电压VIN，而源极和本体端连接到开关电压VSW。因此，高端晶体管的源极和本体的电压在地电压和输入电压VIN之间摆动。
对于低端晶体管来说，晶体管的本体与P-衬底合并在一起。对于高端晶体管来说，晶体管的本体必须通过N-掩埋层，与P-衬底绝缘。
在本发明的实施例中，无需N-掩埋层，就能制备准VDMOS晶体管，因此准VDMOS晶体管可以用作降压转换器中的低端晶体管。此外，在本发明的实施例中，形成在掩埋层上的准VDMOS晶体管，以及无需掩埋层就能制备的准VDMOS形成在同一个集成电路中，因此该集成电路可以用作降压转换器的功率开关晶体管。
图6表示依据本发明的一个实施例，含有无需掩埋层就能制备的qVDMOS晶体管以及带有掩埋层的qVDMOS晶体管的集成电路剖面图。参见图6，集成电路包含一个无需掩埋层就能制备的qVDMOS晶体管200以及形成在掩埋层上的qVDMOS晶体管250。集成电路形成在P-型衬底52和外延层56上。qVDMOS晶体管200形成在外延层中的P-阱257中。P-阱257可以是高压P-阱，比标准的P-阱掺杂浓度更轻而且更深。
qVDMOS晶体管200的制备方式与上述N-型轻掺杂侧壁区272的制备方式基本相同，N-型轻掺杂侧壁区272沿沟槽270的侧壁形成，作为垂直漏极电流通路。在没有N-掩埋层的情况下，沟槽270也作为沟槽漏极电极，接收来自轻掺杂侧壁区272的漏极电流。在本实施例中，所形成的沟槽带有底部掺杂区282。在本发明的实施例中，利用两步注入工艺，制备底部掺杂区282，以形成一个分级的结。然后，沟槽内衬薄氧化层276。沉积底部氧化层274之后，再沉积多晶硅层278，以构成一个导电场板。多晶硅层可以依据与上述相同的方式，连接到栅极电极62，利用多晶硅层278作为场板，以降低漏极电流通路的电阻。还可选择，将多晶硅层278连接到源极/本体电极66/68，使栅漏重叠电容达到最小。
为了在同一个沟槽270中形成漏极电极，利用第二沟槽刻蚀工艺，穿过多晶硅层278刻蚀。沉积氧化层，使多晶硅层绝缘。然后，利用另一个沟槽刻蚀工艺，形成一个沟槽开口，穿过底部氧化层274，一直到底部掺杂区282。用导电层（例如铝或钨）填充沟槽开口，以形成沟槽漏极电极284。在这种情况下，漏极电流沿轻掺杂侧壁区272的垂直漏极电流通路，流至底部掺杂区282，然后通过沟槽漏极电极284起动。
可以镜像qVDMOS晶体管200，无需N-型掩埋层，就可制备并联qVDMOS晶体管的一个阵列，每一对晶体管结构共享一个沟槽结构270。
qVDMOS晶体管250形成在P-衬底52上，一个N-型掩埋层54形成在上面。qVDMOS晶体管200根据与上述相同的方式形成在外延层56中，轻掺杂侧壁区272沿沟槽270的侧壁，用作垂直漏极电流通路。垂直漏极电流通路连接在N-掩埋层54中，N-掩埋层54可以是一片连接到qVDMOS晶体管阵列上的N-掩埋层。沟槽270也作为沟槽漏极电极，接收来自轻掺杂侧壁区272的漏极电流，漏极电流传输至N-掩埋层54，底部掺杂区282，沟槽漏极电极284。
可以镜像qVDMOS晶体管250，在N-型掩埋层上，形成一个并联qVDMOS晶体管的阵列，每一对晶体管结构共享一个沟槽结构270。
因此，qVDMOS晶体管200可以用作降压转换器的低端晶体管，而qVDMOS 250可以用作降压转换器的高端晶体管。依据本发明的一个实施例，利用准垂直DMOS晶体管结构，集成电路的低端晶体管和高端晶体管都可以集成在同一个衬底上。更重要的是，无需N-掩埋层就能制备低端晶体管。从而降低了漏极节点和P-衬底之间的结电容。由于低端开关器件的漏极在地电压和输入电压VIN之间摆动，因此降低漏极节点和P-衬底之间的结电容对于低端开关器件来说尤其重要。N-掩埋层在两个电压极值之间摆动是不良的。
在上述实施例中，qVDMOS晶体管形成在带有N-型外延层56的P-型衬底52上。当使用N-型掩埋层时，qVDMOS器件250形成在N-外延层56中，本体形成在P-阱58中。当没有使用掩埋层时，qVDMOS器件200形成在高压P-阱257中，本体形成在低压P-阱58中，高压P-阱比低压P-阱掺杂浓度更小而且更深。在本发明的实施例中，qVDMOS晶体管形成在带有P-型外延层的P-型衬底52上。在这种情况下，轻掺杂侧壁区272构成N-型漏极延伸区，用于漏极电流。
带有漏极延伸物的NMOS晶体管
在上述DMOS晶体管结构中，构成本体区的P-阱对准到有源扩散区，也就是源极扩散。栅极电极也对准到有源扩散区。因此，P-阱和栅极电极不会相互自对准，而是具有各自的对准过程。当这两个层都对准到有源扩散区时，可以有单独的不对准误差。当在沟槽附近如上所述地镜像晶体管结构制备DMOS晶体管阵列时，不对准误差会使沟槽一侧晶体管的导通电阻RdsON较大，沟槽另一侧晶体管的RdsON较小。导通电阻的这种不对称性是不良的。
依据本发明的另一方面，制备NMOS晶体管，其漏极延伸物在沿沟槽侧壁的垂直漏极电流通路中。更重要的是，NMOS晶体管可以对称形成在沟槽附近，从而避免任何不对准误差可能引起镜像器件中的器件失配。漏极延伸物的作用是降低栅极电极边缘处的漏极电压，可以缩短NMOS晶体管的通道长度，而不会影响器件的可靠性。
图7表示依据本发明的一个实施例，在中间工艺步骤中带有漏极延伸物的NMOS晶体管剖面图。图8表示依据本发明的一个实施例，一种带有漏极延伸物的NMOS晶体管剖面图。参见图7，NMOS晶体管300和300A形成在P-型衬底52上，N-型掩埋层54形成在上面。外延层形成在衬底52上，衬底52可以为N-型或P-型。NMOS晶体管300和300A形成在P-阱58中，P-阱58可以是一片外延层中的P-阱。NMOS晶体管300和300A为传统的NMOS晶体管，栅极电极62形成在栅极氧化层60上方。沿栅极电极62的侧壁制备垫片64之前，先制备轻掺杂漏极扩散区65。然后，制备N+源极扩散区66、漏极扩散区367以及P+本体接触扩散区68。横向通道形成在栅极电极和栅极氧化层以下，通道长度用“LCH”表示。
在本实施例中，制备NMOS晶体管300和300A，作为并联NMOS晶体管的一个阵列。制备漏极扩散区367，作为一个细长的扩散区，连接两个相邻的NMOS晶体管。在本发明的实施例中，在漏极扩散区367中制备沟槽370，如图7中虚线所示。安排沟槽370的位置，使漏极扩散区367位于沟槽的任意一侧。
参见图8，沟槽370细长在漏极扩散区367和P-阱58中，并且触及N-掩埋层54。利用N-型侧壁注入，沿沟槽侧壁形成轻掺杂侧壁区372。制备薄侧壁氧化层376，内衬沟槽370的侧壁，然后在沟槽底部沉积很厚的氧化层374。用导电层（例如多晶硅层378）填充沟槽，形成导电场板。导电场板378可以电连接到栅极电极或源极电极。导电场板的工作方式与上述图3相同，在累加态下导电场板可以偏置，以降低垂直漏极电流通路的导通电阻，或者通过偏置降低栅漏重叠电容。
因此，NMOS晶体管300和300A在栅极电极62下方具有传统的横向通道，以源极和漏极扩散区为界，晶体管在漏极扩散区367中具有一个漏极端。漏极端接收的漏极电流流向轻掺杂侧壁区372中形成的垂直漏极电流通路。在本实施例中，N-掩埋层54收集漏极电流，漏极粘损电极（例如沟槽漏极电极）可以形成在集成电路中的任何地方，以便用图3所示相同的方式连接到N-掩埋层54。
NMOS晶体管具有许多优势。首先，在沟槽的两侧都有漏极扩散区，使晶体管的通道成为对称的，器件性能不会受到不对准误差的影响。此外，由于漏极扩散区是重掺杂的，漏极扩散区电阻率很低。因此漏极扩散区中沟槽370的绝对位置并不重要。仍然位于沟槽370任意一侧的漏极扩散区可以更长或更短，而不会影响晶体管器件的性能。
带有漏极延伸物的NMOS晶体管的一个重要特点是，只要轻掺杂侧壁区具有足够高的电阻率，栅极电极边缘处的漏极扩散区就不会受到高电压。因此，可以减小晶体管的通道长度LCH或者晶体管的源极/本体间距，在不牺牲器件性能的前提下，制备更小的器件。实际上，凭借漏极延伸物，NMOS晶体管在漏极扩散区处将最多只有几伏的电压。排除了穿通或热载流子注入等问题。
在本发明的可选实施例中，无需掩埋层，就能制备带有上述漏极延伸物的NMOS晶体管。图9表示依据本发明的一个可选实施例，带有漏极延伸物的NMOS晶体管剖面图。参见图9，NMOS晶体管400和400A的制备方式除了在P-衬底52上没有制备N-型掩埋层之外，其他都与晶体管300/300A的制备方式基本相同。在这种情况下，沟槽漏极电极形成在沟槽470中，以便与垂直漏极电流通路形成电接触，垂直漏极电流通路形成在轻掺杂侧壁区472中。沟槽结构含有一个导电场板476和一个沟槽漏极电极484，其制备方式与上述图6所示的制备方式相同。因此，来自通道的漏极电流流经漏极扩散区467，向下穿过轻掺杂侧壁区472中的垂直漏极电流通路，流经沟槽底部扩散区482，由漏极电极484起动漏极电流。
图8所示的晶体管300/300A以及图9所示的晶体管400/400A可以制备在同一个集成电路上，用作降压转换器的功率开关器件。带有掩埋层的NMOS晶体管300/300A可以用作高端开关器件，而不带有掩埋层的NMOS晶体管400/400A可以用作低端开关器件。
虽然为了解释说明，上述实施例给出了许多具体细节，但是本发明不应局限于上述细节。实施本发明还有许多可选方式。上述实施例仅用于解释说明，不具有局限性。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (23)

1.一种晶体管，其特征在于，该晶体管包含包含：
一个半导体本体；
一个第一导电类型的本体区，形成在半导体本体中；
一个栅极电极，与本体区部分重叠，并且通过栅极电介质层，与半导体本体绝缘；
一个第二导电类型的源极扩散区，形成在栅极电极第一侧的本体区中；
一个沟槽，形成在栅极电极第二侧的半导体本体中，栅极电极的第二侧与第一侧相对，沟槽内衬侧壁电介质层；以及
一个第二导电类型的掺杂侧壁区，沿沟槽侧壁形成在半导体本体中，掺杂侧壁区构成晶体管的垂直漏极电流通路。
2.如权利要求1所述的晶体管，其特征在于，其中沟槽内衬一个薄电介质层，作为侧壁电介质层，一个底部电介质层填充在沟槽底部，一个导电层填充在底部电介质层上方，导电层电连接到栅极电极或源极电极。
3.如权利要求2所述的晶体管，其特征在于，其中导电层电连接到栅极电极，构成垂直漏极电流通路的沟槽导电场板，当晶体管接通时，场板偏置到累加态，以降低垂直漏极电流通路的电阻率。
4.如权利要求2所述的晶体管，其特征在于，其中薄电介质层包含一个薄氧化层，沟槽中的导电层包含一个多晶硅层。
5.如权利要求2所述的晶体管，其特征在于，其中半导体本体包含：
一个第一导电类型的衬底；
一个第二导电类型的掩埋层，形成在衬底上；以及
一个第二导电类型的外延层，形成在衬底上，
其中沟槽至少触及掩埋层，晶体管的漏极电流穿过掺杂侧壁区，流至掩埋层。
6.如权利要求5所述的晶体管，其特征在于，该晶体管还包含： 
一个第二沟槽，形成在半导体本体中，远离沟槽，至少触及掩埋层，第二沟槽内衬侧壁电介质层，并用导电层填充；以及
一个第二导电类型的沟槽底部掺杂区，形成在第二沟槽以下的半导体本体中，
其中第二沟槽的导电层与沟槽底部掺杂区和掩埋层电接触，构成沟槽漏极电极的导电层传导晶体管的漏极电流。
7.如权利要求6所述的晶体管，其特征在于，其中导电层是由铝或钨的其中一种构成的。
8.如权利要求1所述的晶体管，其特征在于，该晶体管还包含一个第二导电类型的沟槽底部掺杂区，形成在沟槽以下的半导体本体中，并且与掺杂侧壁区电接触，掺杂侧壁区沿沟槽侧壁，形成在半导体本体中，
其中沟槽的侧壁电介质层足够厚，使得导电层与掺杂侧壁区电绝缘，用导电层填充沟槽，导电层与沟槽底部掺杂区电接触，导电层构成沟槽漏极电极；并且
其中垂直漏极电流通路中的晶体管漏极电流，直接流至沟槽底部掺杂区和沟槽漏极电极。
9.如权利要求8所述的晶体管，其特征在于，其中导电层包含铝或钨的其中一种。
10.如权利要求8所述的晶体管，其特征在于，其中半导体本体包含：
一个第一导电类型的衬底；
一个第二导电类型的掩埋层，形成在衬底上；
一个第二导电类型的外延层，形成在衬底上，
其中本体区作为第一导电类型的阱区，
沟槽至少触及掩埋层，晶体管的漏极电流流经掺杂侧壁区，流至掩埋层或沟槽底部掺杂区，然后流至沟槽漏极电极。
11.如权利要求8所述的晶体管，其特征在于，其中半导体本体包含：
一个第一导电类型的衬底；
一个形成在衬底上的外延层；以及
一个第一导电类型的阱区，形成在外延层中，
其中本体区和沟槽都形成在阱区中。
12.如权利要求1所述的晶体管，其特征在于，该晶体管还包含一个第二导电类型的沟槽底部掺杂区，形成在沟槽以下的半导体本体中，并且与掺杂侧壁区电接触，掺杂侧壁区沿沟槽的侧壁形成在半导体本体中，
其中沟槽内衬薄电介质层，作为侧壁电介质层，在沟槽的底部，用底部电介质层填充在沟槽的周边部分，第一导电层在底部电介质层上方，导电层电连接到栅极电极或源极电极；并且
其中沟槽的剩余部分用第二导电层填充，第二导电层与沟槽底部掺杂区电接触，第二导电层通过电介质层，与第一导电层电绝缘，第二导电层构成沟槽漏极电极；并且
其中垂直漏极电流通路中的晶体管漏极电流，直接流至沟槽底部掺杂区和沟槽漏极电极。
13.如权利要求12所述的晶体管，其特征在于，其中半导体本体包含：
一个第一导电类型的衬底；
一个第二导电类型的掩埋层，形成在衬底上；
一个第二导电类型的外延层，形成在衬底上，
其中本体区作为第一导电类型的阱区，
沟槽至少触及掩埋层，晶体管的漏极电流流经掺杂侧壁区，流至掩埋层或沟槽底部掺杂区，然后流至沟槽漏极电极。
14.如权利要求12所述的晶体管，其特征在于，其中半导体本体包含：
一个第一导电类型的衬底；
一个形成在衬底上的外延层；以及
一个第一导电类型的阱区，形成在外延层中，
其中本体区和沟槽都形成在阱区中。
15.如权利要求12所述的晶体管，其特征在于，其中第一导电层包含多晶硅层，第二导电层包含铝或钨的其中一种。
16.如权利要求1所述的晶体管，其特征在于，其中晶体管包含一个双扩散MOS晶体管，其中一个横向通道在栅极电极下方，垂直漏极电流通路沿沟槽的侧壁，在掺杂侧壁区中。
17.如权利要求1所述的晶体管，其特征在于，其中晶体管包含一个MOS晶体管，本体区包含一个第一导电类型的阱区，阱区形成在半导体本体中，MOS晶体管还包含一个第二导电类型的漏极扩散区，形成在栅极电极和沟槽之间的栅极电极第二侧上的本体区中，其中MOS晶体管在栅极电极下方具有一个横向通道，漏极电流从漏极扩散区，沿沟槽侧壁，流至掺杂侧壁区中的垂直漏极电流通路。
18.一种制备晶体管的方法，其特征在于，该方法包含：
制备一个半导体本体；
在半导体本体中，制备一个第一导电类型的本体区；
制备一个栅极电极，与本体区部分重叠，栅极电极通过栅极电介质层，与半导体本体绝缘；
在栅极电极第一侧的本体区中，制备一个第二导电类型的源极扩散区；
在栅极电极第二侧的半导体本体中，制备一个沟槽，栅极电极第二侧与栅极电极第一侧相对；
制备一个侧壁电介质层，内衬沟槽的侧壁；并且
沿沟槽的侧壁，在半导体本体中注入第二导电类型的掺杂物，以构成掺杂侧壁区，掺杂侧壁区构成晶体管的垂直漏极电流通路。
19.如权利要求18所述的方法，其特征在于，该方法还包含：
在沟槽底部，制备一个底部电介质层；
在底部电介质层上方的沟槽中，制备一个导电层；并且
将导电层电连接到栅极电极或源极电极。
20.如权利要求18所述的方法，其特征在于，其中制备半导体本体包含：
制备一个第一导电类型的衬底；
在衬底上制备一个第二导电类型的掩埋层；并且
在衬底上制备一个第二导电类型的外延层，
其中沟槽至少触及掩埋层，晶体管的漏极电流流经掺杂侧壁区，流至掩埋层。
21.如权利要求20所述的方法，其特征在于，该方法还包含：
在半导体本体中，制备一个第二沟槽，远离沟槽，至少触及掩埋层；
在第二沟槽中，制备一个侧壁电介质层；
在第二沟槽以下的半导体本体中，制备一个第二导电类型的沟槽底部掺杂区；并且
在第二沟槽中，制备一个导电层，
其中第二沟槽的导电层与沟槽底部掺杂区和掩埋层电接触，导电层构成一个沟槽漏极电极，传输晶体管的漏极电流。
22.如权利要求18所述的方法，其特征在于，该方法还包含：
在沟槽以下的半导体本体中，制备一个第二导电类型的沟槽底部掺杂区，并且沿沟槽的侧壁，与半导体本体中的掺杂侧壁区电接触；
制备一个厚电介质层，作为侧壁电介质层，内衬沟槽的侧壁；并且
在沟槽中制备一个导电层，与沟槽底部掺杂区电接触，导电层构成一个沟槽漏极电极，
其中在垂直漏极电流通路中流动的晶体管漏极电流，直接流至沟槽底部掺杂区和沟槽漏极电极。
23.如权利要求18所述的方法，其特征在于，该方法还包含：
在沟槽以下的半导体本体中，制备一个第二导电类型的沟槽底部掺杂区，并且沿沟槽的侧壁，与半导体本体中的掺杂侧壁区电接触；
在沟槽底部，制备一个底部电介质层；
在底部电介质层上方的沟槽中，制备一个第一导电层；
刻蚀第一导电层和底部电介质层中形成第一内部沟槽；
在第一内部沟槽中，制备一个电介质层；
在电介质层中，刻蚀第二内部沟槽，刻蚀到沟槽底部；
在第二内部沟槽中，制备一个第二导电层，与沟槽底部掺杂区电接触，剩余的电介质层使第一导电层与第二导电层绝缘，第二导电层构成一个沟槽栅极电极；并且
将第一导电层电连接到栅极电极或源极电极，
其中在垂直漏极电流通路中流动的晶体管漏极电流，直接流至沟槽底部掺杂区和沟槽漏极电极。
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655308A (zh) * 2014-11-28 2016-06-08 英飞凌科技德累斯顿有限责任公司 具有掩埋掺杂区域和接触结构的半导体器件
CN106847749A (zh) * 2017-01-19 2017-06-13 上海宝芯源功率半导体有限公司 一种用于锂电保护的开关器件及其制作方法
CN107611089A (zh) * 2017-09-19 2018-01-19 上海宝芯源功率半导体有限公司 用于锂电保护的开关器件及其制作方法
CN108231886A (zh) * 2016-12-22 2018-06-29 意法半导体股份有限公司 制造半导体器件的方法以及半导体器件
CN109216276A (zh) * 2018-09-17 2019-01-15 深圳市心版图科技有限公司 一种mos管及其制造方法
CN109524395A (zh) * 2017-09-19 2019-03-26 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN110379845A (zh) * 2019-07-22 2019-10-25 无锡新洁能股份有限公司 可抑制非线性电容的功率半导体器件
CN108346701B (zh) * 2018-04-12 2020-05-26 电子科技大学 一种屏蔽栅功率dmos器件
CN112510095A (zh) * 2020-12-01 2021-03-16 无锡先瞳半导体科技有限公司 一种生产nldmos器件的方法及nldmos器件
CN112614891A (zh) * 2020-03-04 2021-04-06 许曙明 具有增强的高频性能的金属氧化物半导体场效应晶体管
CN115714138A (zh) * 2022-11-10 2023-02-24 上海功成半导体科技有限公司 Igbt器件及其制备方法
WO2023173919A1 (zh) * 2022-03-16 2023-09-21 华为数字能源技术有限公司 半导体器件及其制备方法、集成电路和电子设备
CN117038738A (zh) * 2023-10-10 2023-11-10 艾科微电子(深圳)有限公司 半导体器件及其制造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793153B2 (en) 2011-09-20 2017-10-17 Alpha And Omega Semiconductor Incorporated Low cost and mask reduction method for high voltage devices
US9634135B2 (en) * 2012-03-02 2017-04-25 Microchip Technology Incorporated Power field effect transistor
US9735243B2 (en) * 2013-11-18 2017-08-15 Infineon Technologies Ag Semiconductor device, integrated circuit and method of forming a semiconductor device
US9006820B2 (en) * 2012-12-19 2015-04-14 Alpha And Omega Semiconductor Incorporated Vertical DMOS transistor
US9537000B2 (en) * 2013-03-11 2017-01-03 Freescale Semiconductor, Inc. Semiconductor device with increased safe operating area
EP3061124A4 (en) * 2013-09-26 2017-04-26 Intel Corporation Vertical non-planar semiconductor device for system-on-chip (soc) applications
US9245998B2 (en) * 2013-12-29 2016-01-26 Texas Instruments Incorporated High voltage multiple channel LDMOS
US9543292B2 (en) 2015-02-27 2017-01-10 Alpha And Omega Semiconductor Incorporated Field effect transistor with integrated Zener diode
CN104900704A (zh) * 2015-05-15 2015-09-09 四川广义微电子股份有限公司 一种纵向dmos器件
DE102015119771A1 (de) * 2015-11-16 2017-05-18 Infineon Technologies Ag Halbleitervorrichtung mit einem ersten Transistor und einem zweiten Transistor
US9922881B2 (en) 2016-01-12 2018-03-20 United Microelectronics Corp. Method for fabricating semiconductor device structure and product thereof
US10326013B2 (en) 2016-11-23 2019-06-18 Microchip Technology Incorporated Method of forming a field-effect transistor (FET) or other semiconductor device with front-side source and drain contacts
US20180145171A1 (en) * 2016-11-23 2018-05-24 Microchip Technology Incorporated Field Effect Transistor (FET) or Other Semiconductor Device with Front-Side Source and Drain Contacts
TWI676291B (zh) * 2017-02-08 2019-11-01 世界先進積體電路股份有限公司 半導體基底結構及其形成方法和半導體裝置
CN107302025B (zh) * 2017-07-27 2019-11-01 电子科技大学 一种具有抗单粒子效应的vdmos器件
CN108847423B (zh) * 2018-05-30 2022-10-21 矽力杰半导体技术(杭州)有限公司 半导体器件及其制造方法
US11018244B2 (en) * 2018-10-19 2021-05-25 Infineon Technologies Dresden GmbH & Co. KG Lateral trench transistor device
FR3106697A1 (fr) * 2020-01-23 2021-07-30 Stmicroelectronics (Rousset) Sas Structure de transistor
TWI824342B (zh) * 2021-11-24 2023-12-01 新唐科技股份有限公司 半導體結構及其形成方法
TWI835376B (zh) * 2022-10-31 2024-03-11 力晶積成電子製造股份有限公司 半導體裝置及形成屏蔽結構的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050112822A1 (en) * 2003-11-21 2005-05-26 Andrej Litwin Method in the fabrication of a monolithically integrated high frequency circuit
US7411266B2 (en) * 2006-05-30 2008-08-12 Semiconductor Components Industries, L.L.C. Semiconductor device having trench charge compensation regions and method
US20090096021A1 (en) * 2005-02-15 2009-04-16 Loechelt Gary H Semiconductor device having deep trench charge compensation regions and method
US20110006361A1 (en) * 2009-07-13 2011-01-13 Maxpower Semiconductor Inc. Integrated Power Supplies and Combined High-Side Plus Low-Side Switches
US8004039B2 (en) * 2009-07-31 2011-08-23 Micrel, Inc. Field effect transistor with trench-isolated drain

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102050758A (zh) 2000-09-14 2011-05-11 田边三菱制药株式会社 酰胺衍生物及其制备药物的用途
US7183193B2 (en) 2001-12-28 2007-02-27 Micrel, Inc. Integrated device technology using a buried power buss for major device and circuit advantages
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US8227860B2 (en) 2003-02-28 2012-07-24 Micrel, Inc. System for vertical DMOS with slots
US7087491B1 (en) 2003-02-28 2006-08-08 Micrel, Inc. Method and system for vertical DMOS with slots
US7285822B2 (en) 2005-02-11 2007-10-23 Alpha & Omega Semiconductor, Inc. Power MOS device
US7566931B2 (en) 2005-04-18 2009-07-28 Fairchild Semiconductor Corporation Monolithically-integrated buck converter
JP2010021388A (ja) * 2008-07-11 2010-01-28 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
US7989857B2 (en) 2008-12-17 2011-08-02 Semiconductor Components Industries, Llc Electronic device including an insulating layer having different thicknesses and a conductive electrode and a process of forming the same
US7868379B2 (en) 2008-12-17 2011-01-11 Semiconductor Components Industries, Llc Electronic device including a trench and a conductive structure therein
US8039897B2 (en) 2008-12-19 2011-10-18 Fairchild Semiconductor Corporation Lateral MOSFET with substrate drain connection
US8304825B2 (en) 2010-09-22 2012-11-06 Monolithic Power Systems, Inc. Vertical discrete devices with trench contacts and associated methods of manufacturing
US8679919B2 (en) * 2011-12-15 2014-03-25 Semiconductor Components Industries, Llc Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same
US9006820B2 (en) * 2012-12-19 2015-04-14 Alpha And Omega Semiconductor Incorporated Vertical DMOS transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050112822A1 (en) * 2003-11-21 2005-05-26 Andrej Litwin Method in the fabrication of a monolithically integrated high frequency circuit
US20090096021A1 (en) * 2005-02-15 2009-04-16 Loechelt Gary H Semiconductor device having deep trench charge compensation regions and method
US7411266B2 (en) * 2006-05-30 2008-08-12 Semiconductor Components Industries, L.L.C. Semiconductor device having trench charge compensation regions and method
US20110006361A1 (en) * 2009-07-13 2011-01-13 Maxpower Semiconductor Inc. Integrated Power Supplies and Combined High-Side Plus Low-Side Switches
US8004039B2 (en) * 2009-07-31 2011-08-23 Micrel, Inc. Field effect transistor with trench-isolated drain

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655308A (zh) * 2014-11-28 2016-06-08 英飞凌科技德累斯顿有限责任公司 具有掩埋掺杂区域和接触结构的半导体器件
CN108231886A (zh) * 2016-12-22 2018-06-29 意法半导体股份有限公司 制造半导体器件的方法以及半导体器件
CN108231886B (zh) * 2016-12-22 2021-06-04 意法半导体股份有限公司 制造半导体器件的方法以及半导体器件
CN106847749A (zh) * 2017-01-19 2017-06-13 上海宝芯源功率半导体有限公司 一种用于锂电保护的开关器件及其制作方法
CN106847749B (zh) * 2017-01-19 2020-04-03 上海宝芯源功率半导体有限公司 一种用于锂电保护的开关器件及其制作方法
CN107611089A (zh) * 2017-09-19 2018-01-19 上海宝芯源功率半导体有限公司 用于锂电保护的开关器件及其制作方法
CN107611089B (zh) * 2017-09-19 2024-03-26 宁波宝芯源功率半导体有限公司 用于锂电保护的开关器件及其制作方法
CN109524395A (zh) * 2017-09-19 2019-03-26 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN109524395B (zh) * 2017-09-19 2020-09-11 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN108346701B (zh) * 2018-04-12 2020-05-26 电子科技大学 一种屏蔽栅功率dmos器件
CN109216276B (zh) * 2018-09-17 2020-10-23 上海芯龙半导体技术股份有限公司 一种mos管及其制造方法
CN109216276A (zh) * 2018-09-17 2019-01-15 深圳市心版图科技有限公司 一种mos管及其制造方法
CN110379845A (zh) * 2019-07-22 2019-10-25 无锡新洁能股份有限公司 可抑制非线性电容的功率半导体器件
CN112614891A (zh) * 2020-03-04 2021-04-06 许曙明 具有增强的高频性能的金属氧化物半导体场效应晶体管
TWI805991B (zh) * 2020-03-04 2023-06-21 大陸商上海晶豐明源半導體股份有限公司 金屬氧化物半導體場效應電晶體元件
CN112510095A (zh) * 2020-12-01 2021-03-16 无锡先瞳半导体科技有限公司 一种生产nldmos器件的方法及nldmos器件
WO2023173919A1 (zh) * 2022-03-16 2023-09-21 华为数字能源技术有限公司 半导体器件及其制备方法、集成电路和电子设备
CN115714138A (zh) * 2022-11-10 2023-02-24 上海功成半导体科技有限公司 Igbt器件及其制备方法
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