JP5360829B2 - 低オン抵抗のmosデバイス配置 - Google Patents
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- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000013500 data storage Methods 0.000 description 27
- 238000012545 processing Methods 0.000 description 25
- 230000001413 cellular effect Effects 0.000 description 11
- 229910044991 metal oxide Inorganic materials 0.000 description 9
- 150000004706 metal oxides Chemical class 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 7
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Description
本発明は、低オン抵抗のデバイスを製造する金属酸化膜半導体(MOS)デバイスの配置に係り、特に、このような配置を有する方形型二重拡散金属酸化物半導体(SQDMOS)デバイスに係る。
Claims (20)
- 基板上に形成された方形型DMOS(SQDMOS)の形状を有するSQDMOSデバイスであって、
正方形または矩形の形状を有するドレイン領域と、
前記ドレイン領域を取り囲み、前記ドレイン領域の形状に対応しており、前記ドレイン領域の周りに閉ループ状に形成されたゲート領域と、
前記ゲート領域の周りに配置され、前記SQDMOSデバイスの外周に位置する複数のソース領域であって、複数のソース領域のそれぞれが矩形の形状を有する複数のソース領域と、
前記ゲート領域の周りに、前記複数のソース領域を分離するよう配置された複数のバルク領域であって、前記ドレイン領域の一辺と整列しないように設けられ、前記SQDMOSデバイスの隅に配置されて前記ゲート領域と接触していない複数のバルク領域と、を備え、前記SQDMOSデバイスの構造により前記SQDMOSデバイスのオン抵抗が小さくなるSQDMOSデバイス。 - 前記ゲート領域の周りの前記複数のソース領域と前記複数のバルク領域との間に配置されている複数の領域をさらに備え、
前記複数の領域のそれぞれは、対応するソース領域と、対応するバルク領域との間に配置されている、請求項1に記載のSQDMOSデバイス。 - 前記複数の領域のそれぞれは、前記ゲート領域に電気的に連結されたゲート端子を含む、請求項2に記載のSQDMOSデバイス。
- 前記複数のソース領域のうちの2つのソース領域は、前記ドレイン領域の対向する2辺と対向するように配置されており、前記2つのソース領域は、前記ドレイン領域の辺より大きい幅を有する、請求項1から3のいずれか1項に記載のSQDMOSデバイス。
- 前記ゲート領域の下にチャネル領域が形成される、請求項1から4のいずれか1項に記載のSQDMOSデバイス。
- 前記チャネル領域は、電流が各ソース領域から前記ドレイン領域へ流れるよう構成される、請求項5に記載のSQDMOSデバイス。
- 前記SQDMOSデバイスはトランジスタである、請求項1から6のいずれか1項に記載のSQDMOSデバイス。
- 前記基板はシリコン基板であり、前記ゲート領域はポリシリコンを含む、請求項1から7のいずれか1項に記載のSQDMOSデバイス。
- 前記ドレイン領域はドレイン端子を有し、
前記複数のソース領域の少なくとも1つは、ソース端子を有し、
前記ドレイン端子と、前記ゲート領域との間の距離は、前記ソース端子と、前記ゲート領域との間の距離より長い、請求項1から8のいずれか1項に記載のSQDMOSデバイス。 - 基板上にアレイ状に形成された複数のMOSトランジスタセルを含み、方形型DMOS(SQDMOS)の形状を有するSQDMOSデバイスであって、
各MOSトランジスタセルは、
正方形または矩形の形状を有するドレイン領域と、
前記ドレイン領域を取り囲み、前記ドレイン領域の形状に対応しており、前記ドレイン領域の周りに閉ループ状に形成されたゲート領域と、
前記ゲート領域の周りに配置され、前記SQDMOSデバイスの外周に位置する複数のソース領域であって、複数のソース領域のそれぞれが矩形の形状を有する複数のソース領域と、
前記ゲート領域の周りに、前記複数のソース領域を分離するよう配置された複数のバルク領域であって、前記ドレイン領域の一辺と整列しないように設けられ、前記SQDMOSデバイスの隅に配置されて前記ゲート領域と接触していない複数のバルク領域と、を有し、
前記複数のソース領域は、隣接するMOSトランジスタセルにおいて対応する複数のソース領域と重なり、前記SQDMOSデバイスの構造により前記SQDMOSデバイスのオン抵抗が小さくなる、SQDMOSデバイス。 - 基板上に方形型DMOS(SQDMOS)の形状を有するSQDMOSデバイスを形成する方法であって、
正方形または矩形の形状を有するドレイン領域を形成する工程と、
前記ドレイン領域を取り囲み、前記ドレイン領域の形状に対応しており、前記ドレイン領域の周りに閉ループ状に形成されたゲート領域を形成する工程と、
前記ゲート領域の周りに配置され、前記SQDMOSデバイスの外周に位置する複数のソース領域であって、複数のソース領域のそれぞれが矩形の形状を有する複数のソース領域を形成する工程と、
前記ゲート領域の周りに、前記複数のソース領域を分離する複数のバルク領域であって、前記ドレイン領域の一辺と整列しないように設けられ、前記SQDMOSデバイスの隅に配置されて前記ゲート領域と接触していない複数のバルク領域を形成する工程と、を備え、前記SQDMOSデバイスの構造により前記SQDMOSデバイスのオン抵抗が小さくなる、方法。 - 前記ゲート領域の周りの前記複数のソース領域と前記複数のバルク領域との間に複数の領域を形成する工程をさらに備え、
前記複数の領域のそれぞれは、対応するソース領域と、対応するバルク領域との間に配置される、請求項11に記載の方法。 - 前記複数の領域のそれぞれは、前記ゲート領域に電気的に連結されたゲート端子を含む、請求項12に記載の方法。
- 前記複数のソース領域のうちの2つのソース領域は、前記ドレイン領域の対向する2辺と対向するように配置されており、前記2つのソース領域は、前記ドレイン領域の辺より大きい幅を有する、請求項11から13のいずれか1項に記載の方法。
- 前記ゲート領域の下にチャネル領域を形成する工程をさらに備える、請求項11から14のいずれか1項に記載の方法。
- 前記チャネル領域は、電流が各ソース領域から前記ドレイン領域へ流れるよう構成される、請求項15に記載の方法。
- 前記SQDMOSデバイスは、トランジスタである、請求項11から16のいずれか1項に記載の方法。
- 前記基板はシリコン基板であり、前記ゲート領域はポリシリコンを含む、請求項11から17のいずれか1項に記載の方法。
- 前記ドレイン領域はドレイン端子を有し、
前記複数のソース領域の少なくとも1つはソース端子を有し、
前記ドレイン端子と、前記ゲート領域との間の距離は、前記ソース端子と、前記ゲート領域との間の距離より長い、請求項11から18のいずれか1項に記載の方法。 - 方形型DMOS(SQDMOS)の形状を有するMOSトランジスタデバイスを基板上に形成する方法であって、
複数のMOSトランジスタセルを前記基板上に形成する工程を備え、
各MOSトランジスタセルは、
正方形または矩形の形状を有するドレイン領域を形成する工程と、
前記ドレイン領域を取り囲み、前記ドレイン領域の形状に対応しており、前記ドレイン領域の周りに閉ループ状に形成されたゲート領域を形成する工程と、
前記ゲート領域の周りに配置され、前記MOSトランジスタセルの外周に位置する複数のソース領域であって、複数のソース領域のそれぞれが矩形の形状を有する複数のソース領域を形成する工程と、
前記ゲート領域の周りに、前記複数のソース領域を分離する複数のバルク領域であって、前記ドレイン領域の一辺と整列しないように設けられ、前記MOSトランジスタセルの隅に配置されて前記ゲート領域と接触していない複数のバルク領域を形成する工程と、により形成され、
前記複数のソース領域は、隣接するMOSトランジスタセルの対応するソース領域に重なり、前記MOSトランジスタデバイスの構造により前記MOSトランジスタデバイスのオン抵抗が小さくなる、方法。
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US88225006P | 2006-12-28 | 2006-12-28 | |
US60/882,250 | 2006-12-28 | ||
PCT/US2007/088866 WO2008083180A2 (en) | 2006-12-28 | 2007-12-26 | Geometry of mos device with low on-resistance |
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JP2013098733A Expired - Fee Related JP5726230B2 (ja) | 2006-12-28 | 2013-05-08 | 低オン抵抗のmosデバイス配置 |
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US (1) | US9466596B2 (ja) |
EP (1) | EP2100334B1 (ja) |
JP (2) | JP5360829B2 (ja) |
CN (2) | CN101657901B (ja) |
TW (1) | TWI456758B (ja) |
WO (1) | WO2008083180A2 (ja) |
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EP2400552A1 (en) | 2010-06-24 | 2011-12-28 | Dialog Semiconductor GmbH | Mos transistor structure with easy access to all nodes |
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CN102142462B (zh) * | 2011-02-25 | 2012-08-29 | 北京大学 | 一种非对称结构的功率mos晶体管及其阵列 |
EP2710637B1 (en) * | 2011-05-19 | 2019-09-04 | Hewlett-Packard Development Company, L.P. | Device with active channel length/width greater than channel length/width |
KR20150092828A (ko) * | 2014-02-06 | 2015-08-17 | 정덕영 | 배터리의 충방전 제어회로를 위한 4-단자 fet |
CN105097916A (zh) | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管器件及其制作方法 |
CN104409503B (zh) * | 2014-11-21 | 2017-05-17 | 中国科学院上海微系统与信息技术研究所 | 多叉指栅极结构mosfet的版图设计 |
US9356105B1 (en) * | 2014-12-29 | 2016-05-31 | Macronix International Co., Ltd. | Ring gate transistor design for flash memory |
EP3062349B1 (en) | 2015-02-25 | 2019-10-09 | Nxp B.V. | Semiconductor device comprising a switch |
CN106328508B (zh) * | 2016-08-22 | 2019-02-01 | 上海华力微电子有限公司 | 改善有源区边界处的栅极拐角的方法 |
EP3352224B1 (en) * | 2017-01-24 | 2020-03-11 | Nxp B.V. | Semiconductor device comprising a switch |
US10811497B2 (en) | 2018-04-17 | 2020-10-20 | Silanna Asia Pte Ltd | Tiled lateral BJT |
US11309353B2 (en) * | 2020-04-30 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer-defined back-end transistor as memory selector |
CN111599807B (zh) * | 2020-05-22 | 2023-09-01 | 赛卓电子科技(上海)股份有限公司 | 一种标准mos工艺下提升性能的差分输入对管及提升方法 |
CN116344530B (zh) * | 2021-12-24 | 2024-09-20 | 长鑫存储技术有限公司 | 晶体管单元及其阵列、集成电路 |
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-
2007
- 2007-12-26 WO PCT/US2007/088866 patent/WO2008083180A2/en active Application Filing
- 2007-12-26 CN CN2007800519011A patent/CN101657901B/zh not_active Expired - Fee Related
- 2007-12-26 EP EP07866042.0A patent/EP2100334B1/en not_active Not-in-force
- 2007-12-26 US US11/964,696 patent/US9466596B2/en not_active Expired - Fee Related
- 2007-12-26 CN CN201210147239.2A patent/CN102709285B/zh not_active Expired - Fee Related
- 2007-12-26 JP JP2009544252A patent/JP5360829B2/ja not_active Expired - Fee Related
- 2007-12-28 TW TW096150732A patent/TWI456758B/zh not_active IP Right Cessation
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2013
- 2013-05-08 JP JP2013098733A patent/JP5726230B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2008083180A2 (en) | 2008-07-10 |
TW200849591A (en) | 2008-12-16 |
EP2100334A2 (en) | 2009-09-16 |
US20080157195A1 (en) | 2008-07-03 |
CN101657901B (zh) | 2012-07-04 |
JP2013179336A (ja) | 2013-09-09 |
EP2100334A4 (en) | 2011-03-23 |
JP5726230B2 (ja) | 2015-05-27 |
CN102709285A (zh) | 2012-10-03 |
CN102709285B (zh) | 2015-09-16 |
US9466596B2 (en) | 2016-10-11 |
JP2010515274A (ja) | 2010-05-06 |
EP2100334B1 (en) | 2016-04-13 |
CN101657901A (zh) | 2010-02-24 |
WO2008083180A3 (en) | 2008-08-28 |
TWI456758B (zh) | 2014-10-11 |
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