JP5726230B2 - 低オン抵抗のmosデバイス配置 - Google Patents
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- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims description 12
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000013500 data storage Methods 0.000 description 27
- 238000012545 processing Methods 0.000 description 25
- 230000001413 cellular effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
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- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
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Description
本発明は、低オン抵抗のデバイスを製造する金属酸化膜半導体(MOS)デバイスの配置に係り、特に、このような配置を有する方形型二重拡散金属酸化物半導体(SQDMOS)デバイスに係る。
Claims (22)
- 基板上に形成された金属酸化膜半導体デバイス(MOSデバイス)であって、
正方形または矩形の形状を有するドレイン領域と、
(i)前記ドレイン領域を取り囲み、(ii)前記ドレイン領域の周りに閉ループ状に形成され、前記閉ループが前記ドレイン領域の形状に対応する形状を有するゲート領域と、
(i)前記ゲート領域の周りに配置され、(ii)前記ドレイン領域と対向する複数のソース領域と、
(i)前記ゲート領域の周りに配置され、(ii)前記複数のソース領域を分離する、正方形または矩形の形状を有する複数のバルク領域と
を備え
前記ドレイン領域の対向する2辺と対向するように配置された前記複数のソース領域のうちの2つのソース領域のそれぞれは、前記ドレイン領域の前記対向する2辺のそれぞれと同じ幅を有し、
前記ドレイン領域の対向する他の2辺と対向するように配置された前記複数のソース領域のうちの他の2つのソース領域のそれぞれは、前記ドレイン領域の前記対向する他の2辺のそれぞれより大きい幅を有する、MOSデバイス。 - 前記複数のバルク領域のうちの第1のバルク領域は、
前記複数のソース領域のうちの第1のソース領域の表面と隣接する第1の表面と、
前記ゲート領域に隣接する第1の隅と
を有する、請求項1に記載のMOSデバイス。 - 前記基板は、前記ドレイン領域の形状に対応する形状を有する、請求項1または2に記載のMOSデバイス。
- 前記複数のバルク領域は、前記基板の複数の隅にそれぞれ配置されている、請求項1から3のいずれか1項に記載のMOSデバイス。
- 前記ゲート領域の下にチャネル領域が形成される、請求項1から4のいずれか1項に記載のMOSデバイス。
- 前記チャネル領域は、電流が前記複数のソース領域の各ソース領域から前記ドレイン領域へ流れるよう構成される、請求項5に記載のMOSデバイス。
- 前記MOSデバイスはトランジスタである、請求項1から6のいずれか1項に記載のMOSデバイス。
- 前記基板はシリコン基板であり、前記ゲート領域はポリシリコンを含む、請求項1から7のいずれか1項に記載のMOSデバイス。
- 前記MOSデバイスは方形型Double−Diffused Metal Oxide Semiconductor(SQDMOS)である、請求項1から8のいずれか1項に記載のMOSデバイス。
- 前記ドレイン領域はドレイン端子を有し、
前記複数のソース領域の第1のソース領域は、ソース端子を有し、
前記ドレイン端子と、前記ゲート領域との間の距離は、前記ソース端子と、前記ゲート領域との間の距離より長い、請求項1から9のいずれか1項に記載のMOSデバイス。 - 前記MOSデバイスが前記ドレイン領域の周りに閉ループ状に形成された前記ゲート領域を備えることによって、前記MOSデバイスの構造が、前記ゲート領域が前記ドレイン領域の周りに閉ループ状に形成されない場合に比べて、前記MOSデバイスのオン抵抗(Ron)を小さくする、請求項1から10のいずれか1項に記載のMOSデバイス。
- 前記ゲート領域の周りの前記複数のソース領域と前記複数のバルク領域との間に配置されている複数の領域をさらに備え、前記複数の領域のそれぞれは、前記ゲート領域に電気的に連結されたゲート端子を含む、請求項1から11のいずれか1項に記載のMOSデバイス。
- 基板上に金属酸化膜半導体デバイス(MOSデバイス)を形成する方法であって、
正方形又は矩形の形状を有するドレイン領域を形成する工程と、
(i)前記ドレイン領域を取り囲み、(ii)前記ドレイン領域の周りに閉ループ状に形成され、前記閉ループが前記ドレイン領域の形状に対応する形状を有するゲート領域を形成する工程と、
(i)前記ゲート領域の周りに配置され、(ii)前記ドレイン領域と対向する複数のソース領域を形成する工程と、
(i)前記ゲート領域の周りに配置され、(ii)前記複数のソース領域を分離する、正方形又は矩形の形状を有する複数のバルク領域を形成する工程と
を備え、
前記ドレイン領域の対向する2辺と対向するように配置された前記複数のソース領域のうちの2つのソース領域のそれぞれは、前記ドレイン領域の前記対向する2辺のそれぞれと同じ幅を有し、
前記ドレイン領域の対向する他の2辺と対向するように配置された前記複数のソース領域のうちの他の2つのソース領域のそれぞれは、前記ドレイン領域の前記対向する他の2辺のそれぞれより大きい幅を有する、方法。 - 前記複数のバルク領域のうちの第1のバルク領域は、
前記複数のソース領域のうちの第1のソース領域の表面と隣接する第1の表面と、
前記ゲート領域に隣接する第1の隅と
を有する、請求項13に記載の方法。 - 前記基板は、前記ドレイン領域の形状に対応する形状を有する、請求項13または14に記載の方法。
- 前記複数のバルク領域は、前記基板の複数の隅にそれぞれ配置されている、請求項13から15のいずれか1項に記載の方法。
- 前記ゲート領域の下にチャネル領域を形成する工程をさらに備える、請求項13から16のいずれか1項に記載の方法。
- 前記チャネル領域は、電流が前記複数のソース領域の各ソース領域から前記ドレイン領域へ流れるよう構成される、請求項17に記載の方法。
- 前記MOSデバイスはトランジスタである、請求項13から18のいずれか1項に記載の方法。
- 前記ドレイン領域はドレイン端子を有し、
前記複数のソース領域の第1のソース領域はソース端子を有し、
前記ドレイン端子と、前記ゲート領域との間の距離は、前記ソース端子と、前記ゲート領域との間の距離より長い、請求項13から19のいずれか1項に記載の方法。 - 前記MOSデバイスが前記ドレイン領域の周りに閉ループ状に形成された前記ゲート領域を備えることによって、前記MOSデバイスの構造が、前記ゲート領域が前記ドレイン領域の周りに閉ループ状に形成されない場合に比べて、前記MOSデバイスのオン抵抗(Ron)を小さくする、請求項13から20のいずれか1項に記載の方法。
- 前記ゲート領域の周りの前記複数のソース領域と前記複数のバルク領域との間に配置される複数の領域を形成する工程をさらに備え、
前記複数の領域のそれぞれは、前記ゲート領域に電気的に連結されたゲート端子を含む、請求項13から21のいずれか1項に記載の方法。
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US (1) | US9466596B2 (ja) |
EP (1) | EP2100334B1 (ja) |
JP (2) | JP5360829B2 (ja) |
CN (2) | CN102709285B (ja) |
TW (1) | TWI456758B (ja) |
WO (1) | WO2008083180A2 (ja) |
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US7932577B2 (en) * | 2007-12-31 | 2011-04-26 | Silicon Laboratories, Inc. | Circuit device and method of forming a circuit device having a reduced peak current density |
US8076724B2 (en) * | 2008-10-09 | 2011-12-13 | Hvvi Semiconductors, Inc. | Transistor structure having an active region and a dielectric platform region |
EP2400552A1 (en) * | 2010-06-24 | 2011-12-28 | Dialog Semiconductor GmbH | Mos transistor structure with easy access to all nodes |
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CN102142462B (zh) * | 2011-02-25 | 2012-08-29 | 北京大学 | 一种非对称结构的功率mos晶体管及其阵列 |
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EP2100334A4 (en) | 2011-03-23 |
EP2100334A2 (en) | 2009-09-16 |
CN101657901B (zh) | 2012-07-04 |
WO2008083180A3 (en) | 2008-08-28 |
JP2013179336A (ja) | 2013-09-09 |
CN102709285B (zh) | 2015-09-16 |
CN102709285A (zh) | 2012-10-03 |
CN101657901A (zh) | 2010-02-24 |
EP2100334B1 (en) | 2016-04-13 |
TWI456758B (zh) | 2014-10-11 |
US20080157195A1 (en) | 2008-07-03 |
US9466596B2 (en) | 2016-10-11 |
JP5360829B2 (ja) | 2013-12-04 |
WO2008083180A2 (en) | 2008-07-10 |
TW200849591A (en) | 2008-12-16 |
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